2 * Copyright (C) 2000, 2001 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 #include <linux/clockchips.h>
19 #include <linux/interrupt.h>
20 #include <linux/percpu.h>
22 #include <asm/addrspace.h>
26 #include <asm/sibyte/sb1250.h>
27 #include <asm/sibyte/sb1250_regs.h>
28 #include <asm/sibyte/sb1250_int.h>
29 #include <asm/sibyte/sb1250_scd.h>
31 #define IMR_IP2_VAL K_INT_MAP_I0
32 #define IMR_IP3_VAL K_INT_MAP_I1
33 #define IMR_IP4_VAL K_INT_MAP_I2
35 #define SB1250_HPT_NUM 3
36 #define SB1250_HPT_VALUE M_SCD_TIMER_CNT /* max value */
39 * The general purpose timer ticks at 1MHz independent if
40 * the rest of the system
42 static void sibyte_set_mode(enum clock_event_mode mode,
43 struct clock_event_device *evt)
45 unsigned int cpu = smp_processor_id();
46 void __iomem *cfg, *init;
48 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
49 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
52 case CLOCK_EVT_MODE_PERIODIC:
54 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init);
55 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
59 case CLOCK_EVT_MODE_ONESHOT:
60 /* Stop the timer until we actually program a shot */
61 case CLOCK_EVT_MODE_SHUTDOWN:
65 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
66 case CLOCK_EVT_MODE_RESUME:
71 static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
73 unsigned int cpu = smp_processor_id();
74 void __iomem *cfg, *init;
76 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
77 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
79 __raw_writeq(delta - 1, init);
80 __raw_writeq(M_SCD_TIMER_ENABLE, cfg);
85 static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
87 unsigned int cpu = smp_processor_id();
88 struct clock_event_device *cd = dev_id;
92 if (cd->mode == CLOCK_EVT_MODE_PERIODIC)
93 tmode = M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS;
98 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
99 ____raw_writeq(tmode, cfg);
101 cd->event_handler(cd);
106 static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
107 static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction);
108 static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
110 void __cpuinit sb1250_clockevent_init(void)
112 unsigned int cpu = smp_processor_id();
113 unsigned int irq = K_INT_TIMER_0 + cpu;
114 struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu);
115 struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
116 unsigned char *name = per_cpu(sibyte_hpt_name, cpu);
118 /* Only have 4 general purpose timers, and we use last one as hpt */
121 sprintf(name, "sb1250-counter-%d", cpu);
123 cd->features = CLOCK_EVT_FEAT_PERIODIC |
124 CLOCK_EVT_FEAT_ONESHOT;
125 clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
126 cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd);
127 cd->min_delta_ns = clockevent_delta2ns(1, cd);
130 cd->cpumask = cpumask_of_cpu(cpu);
131 cd->set_next_event = sibyte_next_event;
132 cd->set_mode = sibyte_set_mode;
133 clockevents_register_device(cd);
135 sb1250_mask_irq(cpu, irq);
138 * Map the timer interrupt to IP[4] of this cpu
140 __raw_writeq(IMR_IP4_VAL,
141 IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
144 sb1250_unmask_irq(cpu, irq);
146 action->handler = sibyte_counter_handler;
147 action->flags = IRQF_DISABLED | IRQF_PERCPU;
150 setup_irq(irq, action);
154 * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
157 static cycle_t sb1250_hpt_read(void)
161 count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT))));
163 return SB1250_HPT_VALUE - count;
166 struct clocksource bcm1250_clocksource = {
169 .read = sb1250_hpt_read,
170 .mask = CLOCKSOURCE_MASK(23),
171 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
174 void __init sb1250_clocksource_init(void)
176 struct clocksource *cs = &bcm1250_clocksource;
178 /* Setup hpt using timer #3 but do not enable irq for it */
180 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
182 __raw_writeq(SB1250_HPT_VALUE,
183 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
185 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
186 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
189 clocksource_set_clock(cs, V_SCD_TIMER_FREQ);
190 clocksource_register(cs);
193 void __init plat_time_init(void)
195 sb1250_clocksource_init();
196 sb1250_clockevent_init();