2 * Copyright (C) 2000,2001,2004 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 #include <linux/clockchips.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/percpu.h>
22 #include <linux/spinlock.h>
24 #include <asm/addrspace.h>
28 #include <asm/sibyte/bcm1480_regs.h>
29 #include <asm/sibyte/sb1250_regs.h>
30 #include <asm/sibyte/bcm1480_int.h>
31 #include <asm/sibyte/bcm1480_scd.h>
33 #include <asm/sibyte/sb1250.h>
36 #define IMR_IP2_VAL K_BCM1480_INT_MAP_I0
37 #define IMR_IP3_VAL K_BCM1480_INT_MAP_I1
38 #define IMR_IP4_VAL K_BCM1480_INT_MAP_I2
41 * The general purpose timer ticks at 1MHz independent if
42 * the rest of the system
44 static void sibyte_set_mode(enum clock_event_mode mode,
45 struct clock_event_device *evt)
47 unsigned int cpu = smp_processor_id();
48 void __iomem *timer_cfg, *timer_init;
50 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
51 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
54 case CLOCK_EVT_MODE_PERIODIC:
55 __raw_writeq(0, timer_cfg);
56 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init);
57 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
61 case CLOCK_EVT_MODE_ONESHOT:
62 /* Stop the timer until we actually program a shot */
63 case CLOCK_EVT_MODE_SHUTDOWN:
64 __raw_writeq(0, timer_cfg);
67 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
68 case CLOCK_EVT_MODE_RESUME:
73 static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
75 unsigned int cpu = smp_processor_id();
76 void __iomem *timer_init;
80 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
81 cnt = __raw_readq(timer_init);
83 __raw_writeq(cnt, timer_init);
84 res = ((long)(__raw_readq(timer_init) - cnt ) > 0) ? -ETIME : 0;
89 static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
91 unsigned int cpu = smp_processor_id();
92 struct clock_event_device *cd = dev_id;
93 void __iomem *timer_cfg;
95 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
98 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
100 cd->event_handler(cd);
105 static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
106 static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction);
107 static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
109 void __cpuinit sb1480_clockevent_init(void)
111 unsigned int cpu = smp_processor_id();
112 unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu;
113 struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu);
114 struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
115 unsigned char *name = per_cpu(sibyte_hpt_name, cpu);
117 BUG_ON(cpu > 3); /* Only have 4 general purpose timers */
119 sprintf(name, "bcm1480-counter %d", cpu);
121 cd->features = CLOCK_EVT_FEAT_PERIODIC |
122 CLOCK_EVT_FEAT_ONESHOT;
123 clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
124 cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd);
125 cd->min_delta_ns = clockevent_delta2ns(1, cd);
128 cd->cpumask = cpumask_of_cpu(cpu);
129 cd->set_next_event = sibyte_next_event;
130 cd->set_mode = sibyte_set_mode;
131 clockevents_register_device(cd);
133 bcm1480_mask_irq(cpu, irq);
136 * Map timer interrupt to IP[4] of this cpu
138 __raw_writeq(IMR_IP4_VAL,
139 IOADDR(A_BCM1480_IMR_REGISTER(cpu,
140 R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (irq << 3)));
142 bcm1480_unmask_irq(cpu, irq);
144 action->handler = sibyte_counter_handler;
145 action->flags = IRQF_DISABLED | IRQF_PERCPU;
148 setup_irq(irq, action);
151 static cycle_t bcm1480_hpt_read(void)
153 return (cycle_t) __raw_readq(IOADDR(A_SCD_ZBBUS_CYCLE_COUNT));
156 struct clocksource bcm1480_clocksource = {
157 .name = "zbbus-cycles",
159 .read = bcm1480_hpt_read,
160 .mask = CLOCKSOURCE_MASK(64),
161 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
164 void __init sb1480_clocksource_init(void)
166 struct clocksource *cs = &bcm1480_clocksource;
170 plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));
171 zbbus = ((plldiv >> 1) * 50000000) + ((plldiv & 1) * 25000000);
172 clocksource_set_clock(cs, zbbus);
173 clocksource_register(cs);
176 void __init plat_time_init(void)
178 sb1480_clocksource_init();
179 sb1480_clockevent_init();