2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
4 * Copyright (C) 2001 Ralf Baechle
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 * Routines for generic manipulation of the interrupts found on the MIPS
21 * The interrupt controller is located in the South Bridge a PIIX4 device
22 * with two internal 82C95 interrupt controllers.
24 #include <linux/init.h>
25 #include <linux/irq.h>
26 #include <linux/sched.h>
27 #include <linux/smp.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
31 #include <linux/kernel_stat.h>
32 #include <linux/kernel.h>
33 #include <linux/random.h>
35 #include <asm/traps.h>
36 #include <asm/i8259.h>
37 #include <asm/irq_cpu.h>
38 #include <asm/irq_regs.h>
39 #include <asm/mips-boards/malta.h>
40 #include <asm/mips-boards/maltaint.h>
41 #include <asm/mips-boards/piix4.h>
42 #include <asm/gt64120.h>
43 #include <asm/mips-boards/generic.h>
44 #include <asm/mips-boards/msc01_pci.h>
45 #include <asm/msc01_ic.h>
47 #include <asm/gcmpregs.h>
49 int gcmp_present = -1;
51 static unsigned long _msc01_biu_base;
52 static unsigned long _gcmp_base;
53 static unsigned int ipi_map[NR_CPUS];
55 static DEFINE_SPINLOCK(mips_irq_lock);
57 static inline int mips_pcibios_iack(void)
63 * Determine highest priority pending interrupt by performing
64 * a PCI Interrupt Acknowledge cycle.
66 switch (mips_revision_sconid) {
67 case MIPS_REVISION_SCON_SOCIT:
68 case MIPS_REVISION_SCON_ROCIT:
69 case MIPS_REVISION_SCON_SOCITSC:
70 case MIPS_REVISION_SCON_SOCITSCP:
71 MSC_READ(MSC01_PCI_IACK, irq);
74 case MIPS_REVISION_SCON_GT64120:
75 irq = GT_READ(GT_PCI0_IACK_OFS);
78 case MIPS_REVISION_SCON_BONITO:
79 /* The following will generate a PCI IACK cycle on the
80 * Bonito controller. It's a little bit kludgy, but it
81 * was the easiest way to implement it in hardware at
84 BONITO_PCIMAP_CFG = 0x20000;
86 /* Flush Bonito register block */
87 dummy = BONITO_PCIMAP_CFG;
90 irq = readl((u32 *)_pcictrl_bonito_pcicfg);
93 BONITO_PCIMAP_CFG = 0;
96 printk(KERN_WARNING "Unknown system controller.\n");
102 static inline int get_int(void)
106 spin_lock_irqsave(&mips_irq_lock, flags);
108 irq = mips_pcibios_iack();
111 * The only way we can decide if an interrupt is spurious
112 * is by checking the 8259 registers. This needs a spinlock
113 * on an SMP system, so leave it up to the generic code...
116 spin_unlock_irqrestore(&mips_irq_lock, flags);
121 static void malta_hw0_irqdispatch(void)
127 /* interrupt has already been cleared */
131 do_IRQ(MALTA_INT_BASE + irq);
134 static void malta_ipi_irqdispatch(void)
140 return; /* interrupt has already been cleared */
142 do_IRQ(MIPS_GIC_IRQ_BASE + irq);
145 static void corehi_irqdispatch(void)
147 unsigned int intedge, intsteer, pcicmd, pcibadaddr;
148 unsigned int pcimstat, intisr, inten, intpol;
149 unsigned int intrcause, datalo, datahi;
150 struct pt_regs *regs = get_irq_regs();
152 printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n");
153 printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n"
154 "Cause : %08lx\nbadVaddr : %08lx\n",
155 regs->cp0_epc, regs->cp0_status,
156 regs->cp0_cause, regs->cp0_badvaddr);
158 /* Read all the registers and then print them as there is a
159 problem with interspersed printk's upsetting the Bonito controller.
160 Do it for the others too.
163 switch (mips_revision_sconid) {
164 case MIPS_REVISION_SCON_SOCIT:
165 case MIPS_REVISION_SCON_ROCIT:
166 case MIPS_REVISION_SCON_SOCITSC:
167 case MIPS_REVISION_SCON_SOCITSCP:
170 case MIPS_REVISION_SCON_GT64120:
171 intrcause = GT_READ(GT_INTRCAUSE_OFS);
172 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
173 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
174 printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause);
175 printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n",
178 case MIPS_REVISION_SCON_BONITO:
179 pcibadaddr = BONITO_PCIBADADDR;
180 pcimstat = BONITO_PCIMSTAT;
181 intisr = BONITO_INTISR;
182 inten = BONITO_INTEN;
183 intpol = BONITO_INTPOL;
184 intedge = BONITO_INTEDGE;
185 intsteer = BONITO_INTSTEER;
186 pcicmd = BONITO_PCICMD;
187 printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr);
188 printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten);
189 printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol);
190 printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge);
191 printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer);
192 printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd);
193 printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr);
194 printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat);
198 die("CoreHi interrupt", regs);
201 static inline int clz(unsigned long x)
215 * Version of ffs that only looks at bits 12..15.
217 static inline unsigned int irq_ffs(unsigned int pending)
219 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
220 return -clz(pending) + 31 - CAUSEB_IP;
225 t0 = pending & 0xf000;
229 pending = pending << t0;
231 t0 = pending & 0xc000;
235 pending = pending << t0;
237 t0 = pending & 0x8000;
241 /* pending = pending << t0; */
248 * IRQs on the Malta board look basically (barring software IRQs which we
249 * don't use at all and all external interrupt sources are combined together
250 * on hardware interrupt 0 (MIPS IRQ 2)) like:
254 * 0 Software (ignored)
255 * 1 Software (ignored)
256 * 2 Combined hardware interrupt (hw0)
257 * 3 Hardware (ignored)
258 * 4 Hardware (ignored)
259 * 5 Hardware (ignored)
260 * 6 Hardware (ignored)
261 * 7 R4k timer (what we use)
263 * We handle the IRQ according to _our_ priority which is:
265 * Highest ---- R4k Timer
266 * Lowest ---- Combined hardware interrupt
268 * then we just return, if multiple IRQs are pending then we will just take
269 * another exception, big deal.
272 asmlinkage void plat_irq_dispatch(void)
274 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
277 irq = irq_ffs(pending);
279 if (irq == MIPSCPU_INT_I8259A)
280 malta_hw0_irqdispatch();
281 else if (gic_present && ((1 << irq) & ipi_map[smp_processor_id()]))
282 malta_ipi_irqdispatch();
284 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
286 spurious_interrupt();
289 #ifdef CONFIG_MIPS_MT_SMP
292 #define GIC_MIPS_CPU_IPI_RESCHED_IRQ 3
293 #define GIC_MIPS_CPU_IPI_CALL_IRQ 4
295 #define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */
296 #define C_RESCHED C_SW0
297 #define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */
299 static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
301 static void ipi_resched_dispatch(void)
303 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
306 static void ipi_call_dispatch(void)
308 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
311 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
316 static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
318 smp_call_function_interrupt();
323 static struct irqaction irq_resched = {
324 .handler = ipi_resched_interrupt,
325 .flags = IRQF_DISABLED|IRQF_PERCPU,
326 .name = "IPI_resched"
329 static struct irqaction irq_call = {
330 .handler = ipi_call_interrupt,
331 .flags = IRQF_DISABLED|IRQF_PERCPU,
335 static int gic_resched_int_base;
336 static int gic_call_int_base;
337 #define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
338 #define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
339 #endif /* CONFIG_MIPS_MT_SMP */
341 static struct irqaction i8259irq = {
342 .handler = no_action,
343 .name = "XT-PIC cascade"
346 static struct irqaction corehi_irqaction = {
347 .handler = no_action,
351 static msc_irqmap_t __initdata msc_irqmap[] = {
352 {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
353 {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
355 static int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap);
357 static msc_irqmap_t __initdata msc_eicirqmap[] = {
358 {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
359 {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
360 {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0},
361 {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0},
362 {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0},
363 {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0},
364 {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
365 {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
366 {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
367 {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
370 static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
372 #if defined(CONFIG_MIPS_MT_SMP)
374 * This GIC specific tabular array defines the association between External
375 * Interrupts and CPUs/Core Interrupts. The nature of the External
376 * Interrupts is also defined here - polarity/trigger.
378 static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
379 { GIC_EXT_INTR(0), X, X, X, X, 0 },
380 { GIC_EXT_INTR(1), X, X, X, X, 0 },
381 { GIC_EXT_INTR(2), X, X, X, X, 0 },
382 { GIC_EXT_INTR(3), 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, 0 },
383 { GIC_EXT_INTR(4), 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, 0 },
384 { GIC_EXT_INTR(5), 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, 0 },
385 { GIC_EXT_INTR(6), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 },
386 { GIC_EXT_INTR(7), 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, 0 },
387 { GIC_EXT_INTR(8), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 },
388 { GIC_EXT_INTR(9), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 },
389 { GIC_EXT_INTR(10), X, X, X, X, 0 },
390 { GIC_EXT_INTR(11), X, X, X, X, 0 },
391 { GIC_EXT_INTR(12), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 },
392 { GIC_EXT_INTR(13), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 },
393 { GIC_EXT_INTR(14), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 },
394 { GIC_EXT_INTR(15), X, X, X, X, 0 },
395 /* This is the end of the general interrupts now we do IPI ones */
400 * GCMP needs to be detected before any SMP initialisation
402 static int __init gcmp_probe(unsigned long addr, unsigned long size)
404 if (gcmp_present >= 0)
407 _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
408 _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ);
409 gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR;
412 printk(KERN_DEBUG "GCMP present\n");
416 #if defined(CONFIG_MIPS_MT_SMP)
417 static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
419 int intr = baseintr + cpu;
420 gic_intr_map[intr].intrnum = GIC_EXT_INTR(intr);
421 gic_intr_map[intr].cpunum = cpu;
422 gic_intr_map[intr].pin = cpupin;
423 gic_intr_map[intr].polarity = GIC_POL_POS;
424 gic_intr_map[intr].trigtype = GIC_TRIG_EDGE;
425 gic_intr_map[intr].ipiflag = 1;
426 ipi_map[cpu] |= (1 << (cpupin + 2));
429 static void __init fill_ipi_map(void)
433 for (cpu = 0; cpu < NR_CPUS; cpu++) {
434 fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1);
435 fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2);
440 void __init arch_init_irq(void)
442 int gic_present, gcmp_present;
449 gcmp_present = gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
451 GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
454 _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ);
455 gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) &
456 MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF;
459 printk(KERN_DEBUG "GIC present\n");
461 switch (mips_revision_sconid) {
462 case MIPS_REVISION_SCON_SOCIT:
463 case MIPS_REVISION_SCON_ROCIT:
465 init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
466 MSC01E_INT_BASE, msc_eicirqmap,
469 init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
470 MSC01C_INT_BASE, msc_irqmap,
474 case MIPS_REVISION_SCON_SOCITSC:
475 case MIPS_REVISION_SCON_SOCITSCP:
477 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
478 MSC01E_INT_BASE, msc_eicirqmap,
481 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
482 MSC01C_INT_BASE, msc_irqmap,
487 set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch);
488 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
489 setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
490 setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
491 } else if (cpu_has_vint) {
492 set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
493 set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch);
494 #ifdef CONFIG_MIPS_MT_SMTC
495 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
496 (0x100 << MIPSCPU_INT_I8259A));
497 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
498 &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
500 * Temporary hack to ensure that the subsidiary device
501 * interrupts coing in via the i8259A, but associated
502 * with low IRQ numbers, will restore the Status.IM
503 * value associated with the i8259A.
508 for (i = 0; i < 16; i++)
509 irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A);
512 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
513 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
515 #endif /* CONFIG_MIPS_MT_SMTC */
517 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
518 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
522 #if defined(CONFIG_MIPS_MT_SMP)
527 gic_call_int_base = GIC_NUM_INTRS - NR_CPUS;
528 gic_resched_int_base = gic_call_int_base - NR_CPUS;
531 gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
534 i = REG(_msc01_biu_base, MSC01_SC_CFG);
535 REG(_msc01_biu_base, MSC01_SC_CFG) =
536 (i | (0x1 << MSC01_SC_CFG_GICENA_SHF));
537 pr_debug("GIC Enabled\n");
540 /* set up ipi interrupts */
542 set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch);
543 set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch);
545 /* Argh.. this really needs sorting out.. */
546 printk("CPU%d: status register was %08x\n", smp_processor_id(), read_c0_status());
547 write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4);
548 printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status());
549 write_c0_status(0x1100dc00);
550 printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
551 for (i = 0; i < NR_CPUS; i++) {
552 setup_irq(MIPS_GIC_IRQ_BASE +
553 GIC_RESCHED_INT(i), &irq_resched);
554 setup_irq(MIPS_GIC_IRQ_BASE +
555 GIC_CALL_INT(i), &irq_call);
556 set_irq_handler(MIPS_GIC_IRQ_BASE +
557 GIC_RESCHED_INT(i), handle_percpu_irq);
558 set_irq_handler(MIPS_GIC_IRQ_BASE +
559 GIC_CALL_INT(i), handle_percpu_irq);
562 /* set up ipi interrupts */
564 set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
565 set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch);
566 cpu_ipi_resched_irq = MSC01E_INT_SW0;
567 cpu_ipi_call_irq = MSC01E_INT_SW1;
570 set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
571 set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
573 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
574 cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
577 setup_irq(cpu_ipi_resched_irq, &irq_resched);
578 setup_irq(cpu_ipi_call_irq, &irq_call);
580 set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq);
581 set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq);
586 void malta_be_init(void)
589 /* Could change CM error mask register */
594 static char *tr[8] = {
595 "mem", "gcr", "gic", "mmio",
596 "0x04", "0x05", "0x06", "0x07"
599 static char *mcmd[32] = {
601 [0x01] = "Legacy Write",
602 [0x02] = "Legacy Read",
608 [0x08] = "Coherent Read Own",
609 [0x09] = "Coherent Read Share",
610 [0x0a] = "Coherent Read Discard",
611 [0x0b] = "Coherent Ready Share Always",
612 [0x0c] = "Coherent Upgrade",
613 [0x0d] = "Coherent Writeback",
616 [0x10] = "Coherent Copyback",
617 [0x11] = "Coherent Copyback Invalidate",
618 [0x12] = "Coherent Invalidate",
619 [0x13] = "Coherent Write Invalidate",
620 [0x14] = "Coherent Completion Sync",
634 static char *core[8] = {
635 "Invalid/OK", "Invalid/Data",
636 "Shared/OK", "Shared/Data",
637 "Modified/OK", "Modified/Data",
638 "Exclusive/OK", "Exclusive/Data"
641 static char *causes[32] = {
642 "None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
643 "COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
644 "0x08", "0x09", "0x0a", "0x0b",
645 "0x0c", "0x0d", "0x0e", "0x0f",
646 "0x10", "0x11", "0x12", "0x13",
647 "0x14", "0x15", "0x16", "INTVN_WR_ERR",
648 "INTVN_RD_ERR", "0x19", "0x1a", "0x1b",
649 "0x1c", "0x1d", "0x1e", "0x1f"
652 int malta_be_handler(struct pt_regs *regs, int is_fixup)
654 /* This duplicates the handling in do_be which seems wrong */
655 int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
658 unsigned long cm_error = GCMPGCB(GCMEC);
659 unsigned long cm_addr = GCMPGCB(GCMEA);
660 unsigned long cm_other = GCMPGCB(GCMEO);
661 unsigned long cause, ocause;
664 cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK);
666 cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF;
668 unsigned long cca_bits = (cm_error >> 15) & 7;
669 unsigned long tr_bits = (cm_error >> 12) & 7;
670 unsigned long mcmd_bits = (cm_error >> 7) & 0x1f;
671 unsigned long stag_bits = (cm_error >> 3) & 15;
672 unsigned long sport_bits = (cm_error >> 0) & 7;
674 snprintf(buf, sizeof(buf),
675 "CCA=%lu TR=%s MCmd=%s STag=%lu "
677 cca_bits, tr[tr_bits], mcmd[mcmd_bits],
678 stag_bits, sport_bits);
680 /* glob state & sresp together */
681 unsigned long c3_bits = (cm_error >> 18) & 7;
682 unsigned long c2_bits = (cm_error >> 15) & 7;
683 unsigned long c1_bits = (cm_error >> 12) & 7;
684 unsigned long c0_bits = (cm_error >> 9) & 7;
685 unsigned long sc_bit = (cm_error >> 8) & 1;
686 unsigned long mcmd_bits = (cm_error >> 3) & 0x1f;
687 unsigned long sport_bits = (cm_error >> 0) & 7;
688 snprintf(buf, sizeof(buf),
689 "C3=%s C2=%s C1=%s C0=%s SC=%s "
690 "MCmd=%s SPort=%lu\n",
691 core[c3_bits], core[c2_bits],
692 core[c1_bits], core[c0_bits],
693 sc_bit ? "True" : "False",
694 mcmd[mcmd_bits], sport_bits);
697 ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >>
698 GCMP_GCB_GMEO_ERROR_2ND_SHF;
700 printk("CM_ERROR=%08lx %s <%s>\n", cm_error,
702 printk("CM_ADDR =%08lx\n", cm_addr);
703 printk("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]);
705 /* reprime cause register */