2 * BRIEF MODULE DESCRIPTION
3 * Momentum Computer Ocelot-C and -CS board dependent boot routines
5 * Copyright (C) 1996, 1997, 2001 Ralf Baechle
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Copyright (C) 2001 Red Hat, Inc.
8 * Copyright (C) 2002 Momentum Computer
10 * Author: Matthew Dharm, Momentum Computer
13 * Louis Hamilton, Red Hat, Inc.
14 * hamilton@redhat.com [MIPS64 modifications]
16 * Author: RidgeRun, Inc.
17 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
19 * Copyright 2001 MontaVista Software Inc.
20 * Author: jsun@mvista.com or jsun@junsun.net
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms of the GNU General Public License as published by the
24 * Free Software Foundation; either version 2 of the License, or (at your
25 * option) any later version.
27 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
30 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
33 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
34 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * You should have received a copy of the GNU General Public License along
39 * with this program; if not, write to the Free Software Foundation, Inc.,
40 * 675 Mass Ave, Cambridge, MA 02139, USA.
43 #include <linux/bcd.h>
44 #include <linux/init.h>
45 #include <linux/kernel.h>
46 #include <linux/types.h>
48 #include <linux/swap.h>
49 #include <linux/ioport.h>
50 #include <linux/sched.h>
51 #include <linux/interrupt.h>
52 #include <linux/pci.h>
53 #include <linux/platform_device.h>
55 #include <linux/timex.h>
56 #include <linux/vmalloc.h>
57 #include <linux/mv643xx.h>
60 #include <asm/bootinfo.h>
65 #include <asm/processor.h>
66 #include <asm/reboot.h>
67 #include <asm/marvell.h>
68 #include <linux/bootmem.h>
69 #include <linux/blkdev.h>
70 #include "ocelot_c_fpga.h"
72 unsigned long marvell_base;
73 unsigned int cpu_clock;
75 /* These functions are used for rebooting or halting the machine*/
76 extern void momenco_ocelot_restart(char *command);
77 extern void momenco_ocelot_halt(void);
78 extern void momenco_ocelot_power_off(void);
80 void momenco_time_init(void);
82 static char reset_reason;
84 void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask);
86 static unsigned long ENTRYLO(unsigned long paddr)
88 return ((paddr & PAGE_MASK) |
89 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
90 _CACHE_UNCACHED)) >> 6;
93 /* setup code for a handoff from a version 2 PMON 2000 PROM */
94 void PMON_v2_setup(void)
96 /* Some wired TLB entries for the MV64340 and perhiperals. The
97 MV64340 is going to be hit on every IRQ anyway - there's
98 absolutely no point in letting it be a random TLB entry, as
99 it'll just cause needless churning of the TLB. And we use
100 the other half for the serial port, which is just a PITA
103 Device Physical Virtual
104 MV64340 Internal Regs 0xf4000000 0xf4000000
105 Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000
106 NVRAM (CS1) 0xfc800000 0xfc800000
107 UARTs (CS2) 0xfd000000 0xfd000000
108 Internal SRAM 0xfe000000 0xfe000000
109 M-Systems DOC (CS3) 0xff000000 0xff000000
111 printk("PMON_v2_setup\n");
114 /* marvell and extra space */
115 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xfffffffff4000000, PM_64K);
116 /* fpga, rtc, and uart */
117 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfffffffffc000000, PM_16M);
118 /* m-sys and internal SRAM */
119 add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfffffffffe000000, PM_16M);
121 marvell_base = 0xfffffffff4000000;
123 /* marvell and extra space */
124 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K);
125 /* fpga, rtc, and uart */
126 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfc000000, PM_16M);
127 /* m-sys and internal SRAM */
128 add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M);
130 marvell_base = 0xf4000000;
134 unsigned long m48t37y_get_time(void)
137 unsigned char *rtc_base = (unsigned char*)0xfffffffffc800000;
139 unsigned char* rtc_base = (unsigned char*)0xfc800000;
141 unsigned int year, month, day, hour, min, sec;
144 spin_lock_irqsave(&rtc_lock, flags);
145 /* stop the update */
146 rtc_base[0x7ff8] = 0x40;
148 year = BCD2BIN(rtc_base[0x7fff]);
149 year += BCD2BIN(rtc_base[0x7ff1]) * 100;
151 month = BCD2BIN(rtc_base[0x7ffe]);
153 day = BCD2BIN(rtc_base[0x7ffd]);
155 hour = BCD2BIN(rtc_base[0x7ffb]);
156 min = BCD2BIN(rtc_base[0x7ffa]);
157 sec = BCD2BIN(rtc_base[0x7ff9]);
159 /* start the update */
160 rtc_base[0x7ff8] = 0x00;
161 spin_unlock_irqrestore(&rtc_lock, flags);
163 return mktime(year, month, day, hour, min, sec);
166 int m48t37y_set_time(unsigned long sec)
169 unsigned char* rtc_base = (unsigned char*)0xfffffffffc800000;
171 unsigned char* rtc_base = (unsigned char*)0xfc800000;
176 /* convert to a more useful format -- note months count from 0 */
180 spin_lock_irqsave(&rtc_lock, flags);
182 rtc_base[0x7ff8] = 0x80;
185 rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
186 rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
189 rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
192 rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
195 rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
196 rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
197 rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
199 /* day of week -- not really used, but let's keep it up-to-date */
200 rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
202 /* disable writing */
203 rtc_base[0x7ff8] = 0x00;
204 spin_unlock_irqrestore(&rtc_lock, flags);
209 void __init plat_timer_setup(struct irqaction *irq)
214 void momenco_time_init(void)
216 #ifdef CONFIG_CPU_SR71000
217 mips_hpt_frequency = cpu_clock;
218 #elif defined(CONFIG_CPU_RM7000)
219 mips_hpt_frequency = cpu_clock / 2;
221 #error Unknown CPU for this board
223 printk("momenco_time_init cpu_clock=%d\n", cpu_clock);
225 rtc_mips_get_time = m48t37y_get_time;
226 rtc_mips_set_time = m48t37y_set_time;
229 void __init plat_mem_setup(void)
231 unsigned int tmpword;
233 board_time_init = momenco_time_init;
235 _machine_restart = momenco_ocelot_restart;
236 _machine_halt = momenco_ocelot_halt;
237 pm_power_off = momenco_ocelot_power_off;
240 * initrd_start = (unsigned long)ocelot_initrd_start;
241 * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size;
242 * initrd_below_start_ok = 1;
245 /* do handoff reconfiguration */
248 /* shut down ethernet ports, just to be sure our memory doesn't get
249 * corrupted by random ethernet traffic.
251 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
252 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
253 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
254 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
256 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
258 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
260 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
262 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
263 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
264 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
265 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
266 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
268 /* Turn off the Bit-Error LED */
269 OCELOT_FPGA_WRITE(0x80, CLR);
271 tmpword = OCELOT_FPGA_READ(BOARDREV);
272 #ifdef CONFIG_CPU_SR71000
274 printk("Momenco Ocelot-CS: Board Assembly Rev. %c\n",
277 printk("Momenco Ocelot-CS: Board Assembly Revision #0x%x\n",
281 printk("Momenco Ocelot-C: Board Assembly Rev. %c\n",
284 printk("Momenco Ocelot-C: Board Assembly Revision #0x%x\n",
288 tmpword = OCELOT_FPGA_READ(FPGA_REV);
289 printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
290 tmpword = OCELOT_FPGA_READ(RESET_STATUS);
291 printk("Reset reason: 0x%x\n", tmpword);
294 printk(" - Power-up reset\n");
297 printk(" - Push-button reset\n");
300 printk(" - cPCI bus reset\n");
303 printk(" - Watchdog reset\n");
306 printk(" - Software reset\n");
309 printk(" - Unknown reset cause\n");
311 reset_reason = tmpword;
312 OCELOT_FPGA_WRITE(0xff, RESET_STATUS);
314 tmpword = OCELOT_FPGA_READ(CPCI_ID);
315 printk("cPCI ID register: 0x%02x\n", tmpword);
316 printk(" - Slot number: %d\n", tmpword & 0x1f);
317 printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no");
318 printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no");
320 tmpword = OCELOT_FPGA_READ(BOARD_STATUS);
321 printk("Board Status register: 0x%02x\n", tmpword);
322 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
323 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
324 printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
325 printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
330 add_memory_region(0x0, 0x200<<20, BOOT_MEM_RAM);
334 add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
338 add_memory_region(0x0, 0x80<<20, BOOT_MEM_RAM);
341 /* 1GiB -- needs CONFIG_HIGHMEM */
342 add_memory_region(0x0, 0x400<<20, BOOT_MEM_RAM);
348 * This needs to be one of the first initcalls, because no I/O port access
349 * can work before this
351 static int io_base_ioremap(void)
353 void __iomem * io_remap_range = ioremap(0xc0000000UL, 0x10000);
356 panic("Could not ioremap I/O port range");
358 set_io_port_base((unsigned long) io_remap_range);
363 module_init(io_base_ioremap);
365 #if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
367 static struct resource mv643xx_eth_shared_resources[] = {
369 .name = "ethernet shared base",
370 .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
371 .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
372 MV643XX_ETH_SHARED_REGS_SIZE - 1,
373 .flags = IORESOURCE_MEM,
377 static struct platform_device mv643xx_eth_shared_device = {
378 .name = MV643XX_ETH_SHARED_NAME,
380 .num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
381 .resource = mv643xx_eth_shared_resources,
384 #define MV_SRAM_BASE 0xfe000000UL
385 #define MV_SRAM_SIZE (256 * 1024)
387 #define MV_SRAM_RXRING_SIZE (MV_SRAM_SIZE / 4)
388 #define MV_SRAM_TXRING_SIZE (MV_SRAM_SIZE / 4)
390 #define MV_SRAM_BASE_ETH0 MV_SRAM_BASE
391 #define MV_SRAM_BASE_ETH1 (MV_SRAM_BASE + (MV_SRAM_SIZE / 2))
393 #define MV64x60_IRQ_ETH_0 48
394 #define MV64x60_IRQ_ETH_1 49
396 #ifdef CONFIG_MV643XX_ETH_0
398 static struct resource mv64x60_eth0_resources[] = {
401 .start = MV64x60_IRQ_ETH_0,
402 .end = MV64x60_IRQ_ETH_0,
403 .flags = IORESOURCE_IRQ,
407 static struct mv643xx_eth_platform_data eth0_pd = {
408 .tx_sram_addr = MV_SRAM_BASE_ETH0,
409 .tx_sram_size = MV_SRAM_TXRING_SIZE,
410 .tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
412 .rx_sram_addr = MV_SRAM_BASE_ETH0 + MV_SRAM_TXRING_SIZE,
413 .rx_sram_size = MV_SRAM_RXRING_SIZE,
414 .rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
417 static struct platform_device eth0_device = {
418 .name = MV643XX_ETH_NAME,
420 .num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
421 .resource = mv64x60_eth0_resources,
423 .platform_data = ð0_pd,
426 #endif /* CONFIG_MV643XX_ETH_0 */
428 #ifdef CONFIG_MV643XX_ETH_1
430 static struct resource mv64x60_eth1_resources[] = {
433 .start = MV64x60_IRQ_ETH_1,
434 .end = MV64x60_IRQ_ETH_1,
435 .flags = IORESOURCE_IRQ,
439 static struct mv643xx_eth_platform_data eth1_pd = {
440 .tx_sram_addr = MV_SRAM_BASE_ETH1,
441 .tx_sram_size = MV_SRAM_TXRING_SIZE,
442 .tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
444 .rx_sram_addr = MV_SRAM_BASE_ETH1 + MV_SRAM_TXRING_SIZE,
445 .rx_sram_size = MV_SRAM_RXRING_SIZE,
446 .rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
449 static struct platform_device eth1_device = {
450 .name = MV643XX_ETH_NAME,
452 .num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
453 .resource = mv64x60_eth1_resources,
455 .platform_data = ð1_pd,
458 #endif /* CONFIG_MV643XX_ETH_1 */
460 static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
461 &mv643xx_eth_shared_device,
462 #ifdef CONFIG_MV643XX_ETH_0
465 #ifdef CONFIG_MV643XX_ETH_1
468 /* The third port is not wired up on the Ocelot C */
471 int mv643xx_eth_add_pds(void)
475 ret = platform_add_devices(mv643xx_eth_pd_devs,
476 ARRAY_SIZE(mv643xx_eth_pd_devs));
481 device_initcall(mv643xx_eth_add_pds);
483 #endif /* defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) */