2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Synthesize TLB refill handlers at runtime.
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
13 * ... and the days got worse and worse and now you see
14 * I've gone completly out of my mind.
16 * They're coming to take me a away haha
17 * they're coming to take me a away hoho hihi haha
18 * to the funny farm where code is beautiful all the time ...
20 * (Condolences to Napoleon XIV)
23 #include <linux/bug.h>
24 #include <linux/kernel.h>
25 #include <linux/types.h>
26 #include <linux/smp.h>
27 #include <linux/string.h>
28 #include <linux/init.h>
30 #include <asm/mmu_context.h>
34 static inline int r45k_bvahwbug(void)
36 /* XXX: We should probe for the presence of this bug, but we don't. */
40 static inline int r4k_250MHZhwbug(void)
42 /* XXX: We should probe for the presence of this bug, but we don't. */
46 static inline int __maybe_unused bcm1250_m3_war(void)
48 return BCM1250_M3_WAR;
51 static inline int __maybe_unused r10000_llsc_war(void)
53 return R10000_LLSC_WAR;
57 * Found by experiment: At least some revisions of the 4kc throw under
58 * some circumstances a machine check exception, triggered by invalid
59 * values in the index register. Delaying the tlbp instruction until
60 * after the next branch, plus adding an additional nop in front of
61 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
62 * why; it's not an issue caused by the core RTL.
65 static int __cpuinit m4kc_tlbp_war(void)
67 return (current_cpu_data.processor_id & 0xffff00) ==
68 (PRID_COMP_MIPS | PRID_IMP_4KC);
71 /* Handle labels (which must be positive integers). */
73 label_second_part = 1,
84 label_smp_pgtable_change,
85 label_r3000_write_probe_fail,
86 #ifdef CONFIG_HUGETLB_PAGE
87 label_tlb_huge_update,
91 UASM_L_LA(_second_part)
94 UASM_L_LA(_vmalloc_done)
95 UASM_L_LA(_tlbw_hazard)
97 UASM_L_LA(_tlbl_goaround1)
98 UASM_L_LA(_tlbl_goaround2)
99 UASM_L_LA(_nopage_tlbl)
100 UASM_L_LA(_nopage_tlbs)
101 UASM_L_LA(_nopage_tlbm)
102 UASM_L_LA(_smp_pgtable_change)
103 UASM_L_LA(_r3000_write_probe_fail)
104 #ifdef CONFIG_HUGETLB_PAGE
105 UASM_L_LA(_tlb_huge_update)
109 * For debug purposes.
111 static inline void dump_handler(const u32 *handler, int count)
115 pr_debug("\t.set push\n");
116 pr_debug("\t.set noreorder\n");
118 for (i = 0; i < count; i++)
119 pr_debug("\t%p\t.word 0x%08x\n", &handler[i], handler[i]);
121 pr_debug("\t.set pop\n");
124 /* The only general purpose registers allowed in TLB handlers. */
128 /* Some CP0 registers */
129 #define C0_INDEX 0, 0
130 #define C0_ENTRYLO0 2, 0
131 #define C0_TCBIND 2, 2
132 #define C0_ENTRYLO1 3, 0
133 #define C0_CONTEXT 4, 0
134 #define C0_PAGEMASK 5, 0
135 #define C0_BADVADDR 8, 0
136 #define C0_ENTRYHI 10, 0
138 #define C0_XCONTEXT 20, 0
141 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
143 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
146 /* The worst case length of the handler is around 18 instructions for
147 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
148 * Maximum space available is 32 instructions for R3000 and 64
149 * instructions for R4000.
151 * We deliberately chose a buffer size of 128, so we won't scribble
152 * over anything important on overflow before we panic.
154 static u32 tlb_handler[128] __cpuinitdata;
156 /* simply assume worst case size for labels and relocs */
157 static struct uasm_label labels[128] __cpuinitdata;
158 static struct uasm_reloc relocs[128] __cpuinitdata;
160 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
162 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
163 * we cannot do r3000 under these circumstances.
167 * The R3000 TLB handler is simple.
169 static void __cpuinit build_r3000_tlb_refill_handler(void)
171 long pgdc = (long)pgd_current;
174 memset(tlb_handler, 0, sizeof(tlb_handler));
177 uasm_i_mfc0(&p, K0, C0_BADVADDR);
178 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
179 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
180 uasm_i_srl(&p, K0, K0, 22); /* load delay */
181 uasm_i_sll(&p, K0, K0, 2);
182 uasm_i_addu(&p, K1, K1, K0);
183 uasm_i_mfc0(&p, K0, C0_CONTEXT);
184 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
185 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
186 uasm_i_addu(&p, K1, K1, K0);
187 uasm_i_lw(&p, K0, 0, K1);
188 uasm_i_nop(&p); /* load delay */
189 uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
190 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
191 uasm_i_tlbwr(&p); /* cp0 delay */
193 uasm_i_rfe(&p); /* branch delay */
195 if (p > tlb_handler + 32)
196 panic("TLB refill handler space exceeded");
198 pr_debug("Wrote TLB refill handler (%u instructions).\n",
199 (unsigned int)(p - tlb_handler));
201 memcpy((void *)ebase, tlb_handler, 0x80);
203 dump_handler((u32 *)ebase, 32);
205 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
208 * The R4000 TLB handler is much more complicated. We have two
209 * consecutive handler areas with 32 instructions space each.
210 * Since they aren't used at the same time, we can overflow in the
211 * other one.To keep things simple, we first assume linear space,
212 * then we relocate it to the final handler layout as needed.
214 static u32 final_handler[64] __cpuinitdata;
219 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
220 * 2. A timing hazard exists for the TLBP instruction.
222 * stalling_instruction
225 * The JTLB is being read for the TLBP throughout the stall generated by the
226 * previous instruction. This is not really correct as the stalling instruction
227 * can modify the address used to access the JTLB. The failure symptom is that
228 * the TLBP instruction will use an address created for the stalling instruction
229 * and not the address held in C0_ENHI and thus report the wrong results.
231 * The software work-around is to not allow the instruction preceding the TLBP
232 * to stall - make it an NOP or some other instruction guaranteed not to stall.
234 * Errata 2 will not be fixed. This errata is also on the R5000.
236 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
238 static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p)
240 switch (current_cpu_type()) {
241 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
258 * Write random or indexed TLB entry, and care about the hazards from
259 * the preceeding mtc0 and for the following eret.
261 enum tlb_write_entry { tlb_random, tlb_indexed };
263 static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
264 struct uasm_reloc **r,
265 enum tlb_write_entry wmode)
267 void(*tlbw)(u32 **) = NULL;
270 case tlb_random: tlbw = uasm_i_tlbwr; break;
271 case tlb_indexed: tlbw = uasm_i_tlbwi; break;
274 if (cpu_has_mips_r2) {
275 if (cpu_has_mips_r2_exec_hazard)
281 switch (current_cpu_type()) {
289 * This branch uses up a mtc0 hazard nop slot and saves
290 * two nops after the tlbw instruction.
292 uasm_il_bgezl(p, r, 0, label_tlbw_hazard);
294 uasm_l_tlbw_hazard(l, *p);
340 uasm_i_nop(p); /* QED specifies 2 nops hazard */
342 * This branch uses up a mtc0 hazard nop slot and saves
343 * a nop after the tlbw instruction.
345 uasm_il_bgezl(p, r, 0, label_tlbw_hazard);
347 uasm_l_tlbw_hazard(l, *p);
360 * When the JTLB is updated by tlbwi or tlbwr, a subsequent
361 * use of the JTLB for instructions should not occur for 4
362 * cpu cycles and use for data translations should not occur
397 panic("No TLB refill handler yet (CPU type: %d)",
398 current_cpu_data.cputype);
403 static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
406 if (kernel_uses_smartmips_rixi) {
407 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC));
408 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
410 #ifdef CONFIG_64BIT_PHYS_ADDR
411 uasm_i_dsrl(p, reg, reg, ilog2(_PAGE_GLOBAL));
413 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL));
418 #ifdef CONFIG_HUGETLB_PAGE
420 static __cpuinit void build_restore_pagemask(u32 **p,
421 struct uasm_reloc **r,
425 /* Reset default page size */
426 if (PM_DEFAULT_MASK >> 16) {
427 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
428 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
429 uasm_il_b(p, r, lid);
430 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
431 } else if (PM_DEFAULT_MASK) {
432 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
433 uasm_il_b(p, r, lid);
434 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
436 uasm_il_b(p, r, lid);
437 uasm_i_mtc0(p, 0, C0_PAGEMASK);
441 static __cpuinit void build_huge_tlb_write_entry(u32 **p,
442 struct uasm_label **l,
443 struct uasm_reloc **r,
445 enum tlb_write_entry wmode)
447 /* Set huge page tlb entry size */
448 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
449 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
450 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
452 build_tlb_write_entry(p, l, r, wmode);
454 build_restore_pagemask(p, r, tmp, label_leave);
458 * Check if Huge PTE is present, if so then jump to LABEL.
460 static void __cpuinit
461 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
462 unsigned int pmd, int lid)
464 UASM_i_LW(p, tmp, 0, pmd);
465 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
466 uasm_il_bnez(p, r, tmp, lid);
469 static __cpuinit void build_huge_update_entries(u32 **p,
476 * A huge PTE describes an area the size of the
477 * configured huge page size. This is twice the
478 * of the large TLB entry size we intend to use.
479 * A TLB entry half the size of the configured
480 * huge page size is configured into entrylo0
481 * and entrylo1 to cover the contiguous huge PTE
484 small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
486 /* We can clobber tmp. It isn't used after this.*/
488 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
490 build_convert_pte_to_entrylo(p, pte);
491 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */
492 /* convert to entrylo1 */
494 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
496 UASM_i_ADDU(p, pte, pte, tmp);
498 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */
501 static __cpuinit void build_huge_handler_tail(u32 **p,
502 struct uasm_reloc **r,
503 struct uasm_label **l,
508 UASM_i_SC(p, pte, 0, ptr);
509 uasm_il_beqz(p, r, pte, label_tlb_huge_update);
510 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
512 UASM_i_SW(p, pte, 0, ptr);
514 build_huge_update_entries(p, pte, ptr);
515 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed);
517 #endif /* CONFIG_HUGETLB_PAGE */
521 * TMP and PTR are scratch.
522 * TMP will be clobbered, PTR will hold the pmd entry.
524 static void __cpuinit
525 build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
526 unsigned int tmp, unsigned int ptr)
528 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
529 long pgdc = (long)pgd_current;
532 * The vmalloc handling is not in the hotpath.
534 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
535 uasm_il_bltz(p, r, tmp, label_vmalloc);
536 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
538 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
540 * &pgd << 11 stored in CONTEXT [23..63].
542 UASM_i_MFC0(p, ptr, C0_CONTEXT);
543 uasm_i_dins(p, ptr, 0, 0, 23); /* Clear lower 23 bits of context. */
544 uasm_i_ori(p, ptr, ptr, 0x540); /* 1 0 1 0 1 << 6 xkphys cached */
545 uasm_i_drotr(p, ptr, ptr, 11);
546 #elif defined(CONFIG_SMP)
547 # ifdef CONFIG_MIPS_MT_SMTC
549 * SMTC uses TCBind value as "CPU" index
551 uasm_i_mfc0(p, ptr, C0_TCBIND);
552 uasm_i_dsrl(p, ptr, ptr, 19);
555 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
558 uasm_i_dmfc0(p, ptr, C0_CONTEXT);
559 uasm_i_dsrl(p, ptr, ptr, 23);
561 UASM_i_LA_mostly(p, tmp, pgdc);
562 uasm_i_daddu(p, ptr, ptr, tmp);
563 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
564 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
566 UASM_i_LA_mostly(p, ptr, pgdc);
567 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
570 uasm_l_vmalloc_done(l, *p);
572 if (PGDIR_SHIFT - 3 < 32) /* get pgd offset in bytes */
573 uasm_i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3);
575 uasm_i_dsrl32(p, tmp, tmp, PGDIR_SHIFT - 3 - 32);
577 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
578 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
579 #ifndef __PAGETABLE_PMD_FOLDED
580 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
581 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
582 uasm_i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
583 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
584 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
589 * BVADDR is the faulting address, PTR is scratch.
590 * PTR will hold the pgd for vmalloc.
592 static void __cpuinit
593 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
594 unsigned int bvaddr, unsigned int ptr)
596 long swpd = (long)swapper_pg_dir;
598 uasm_l_vmalloc(l, *p);
600 if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) {
601 uasm_il_b(p, r, label_vmalloc_done);
602 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
604 UASM_i_LA_mostly(p, ptr, swpd);
605 uasm_il_b(p, r, label_vmalloc_done);
606 if (uasm_in_compat_space_p(swpd))
607 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
609 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
613 #else /* !CONFIG_64BIT */
616 * TMP and PTR are scratch.
617 * TMP will be clobbered, PTR will hold the pgd entry.
619 static void __cpuinit __maybe_unused
620 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
622 long pgdc = (long)pgd_current;
624 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
626 #ifdef CONFIG_MIPS_MT_SMTC
628 * SMTC uses TCBind value as "CPU" index
630 uasm_i_mfc0(p, ptr, C0_TCBIND);
631 UASM_i_LA_mostly(p, tmp, pgdc);
632 uasm_i_srl(p, ptr, ptr, 19);
635 * smp_processor_id() << 3 is stored in CONTEXT.
637 uasm_i_mfc0(p, ptr, C0_CONTEXT);
638 UASM_i_LA_mostly(p, tmp, pgdc);
639 uasm_i_srl(p, ptr, ptr, 23);
641 uasm_i_addu(p, ptr, tmp, ptr);
643 UASM_i_LA_mostly(p, ptr, pgdc);
645 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
646 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
647 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
648 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
649 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
652 #endif /* !CONFIG_64BIT */
654 static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx)
656 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
657 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
659 switch (current_cpu_type()) {
676 UASM_i_SRL(p, ctx, ctx, shift);
677 uasm_i_andi(p, ctx, ctx, mask);
680 static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
683 * Bug workaround for the Nevada. It seems as if under certain
684 * circumstances the move from cp0_context might produce a
685 * bogus result when the mfc0 instruction and its consumer are
686 * in a different cacheline or a load instruction, probably any
687 * memory reference, is between them.
689 switch (current_cpu_type()) {
691 UASM_i_LW(p, ptr, 0, ptr);
692 GET_CONTEXT(p, tmp); /* get context reg */
696 GET_CONTEXT(p, tmp); /* get context reg */
697 UASM_i_LW(p, ptr, 0, ptr);
701 build_adjust_context(p, tmp);
702 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
705 static void __cpuinit build_update_entries(u32 **p, unsigned int tmp,
709 * 64bit address support (36bit on a 32bit CPU) in a 32bit
710 * Kernel is a special case. Only a few CPUs use it.
712 #ifdef CONFIG_64BIT_PHYS_ADDR
713 if (cpu_has_64bits) {
714 uasm_i_ld(p, tmp, 0, ptep); /* get even pte */
715 uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
716 if (kernel_uses_smartmips_rixi) {
717 UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC));
718 UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC));
719 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
720 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
721 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
723 uasm_i_dsrl(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */
724 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
725 uasm_i_dsrl(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */
727 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
729 int pte_off_even = sizeof(pte_t) / 2;
730 int pte_off_odd = pte_off_even + sizeof(pte_t);
732 /* The pte entries are pre-shifted */
733 uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */
734 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
735 uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */
736 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
739 UASM_i_LW(p, tmp, 0, ptep); /* get even pte */
740 UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
742 build_tlb_probe_entry(p);
743 if (kernel_uses_smartmips_rixi) {
744 UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC));
745 UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC));
746 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
747 if (r4k_250MHZhwbug())
748 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
749 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
750 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
752 UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */
753 if (r4k_250MHZhwbug())
754 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
755 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
756 UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */
758 uasm_i_mfc0(p, tmp, C0_INDEX);
760 if (r4k_250MHZhwbug())
761 UASM_i_MTC0(p, 0, C0_ENTRYLO1);
762 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
767 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
768 * because EXL == 0. If we wrap, we can also use the 32 instruction
769 * slots before the XTLB refill exception handler which belong to the
770 * unused TLB refill exception.
772 #define MIPS64_REFILL_INSNS 32
774 static void __cpuinit build_r4000_tlb_refill_handler(void)
776 u32 *p = tlb_handler;
777 struct uasm_label *l = labels;
778 struct uasm_reloc *r = relocs;
780 unsigned int final_len;
782 memset(tlb_handler, 0, sizeof(tlb_handler));
783 memset(labels, 0, sizeof(labels));
784 memset(relocs, 0, sizeof(relocs));
785 memset(final_handler, 0, sizeof(final_handler));
788 * create the plain linear handler
790 if (bcm1250_m3_war()) {
791 UASM_i_MFC0(&p, K0, C0_BADVADDR);
792 UASM_i_MFC0(&p, K1, C0_ENTRYHI);
793 uasm_i_xor(&p, K0, K0, K1);
794 UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
795 uasm_il_bnez(&p, &r, K0, label_leave);
796 /* No need for uasm_i_nop */
800 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
802 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
805 #ifdef CONFIG_HUGETLB_PAGE
806 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
809 build_get_ptep(&p, K0, K1);
810 build_update_entries(&p, K0, K1);
811 build_tlb_write_entry(&p, &l, &r, tlb_random);
813 uasm_i_eret(&p); /* return from trap */
815 #ifdef CONFIG_HUGETLB_PAGE
816 uasm_l_tlb_huge_update(&l, p);
817 UASM_i_LW(&p, K0, 0, K1);
818 build_huge_update_entries(&p, K0, K1);
819 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random);
823 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1);
827 * Overflow check: For the 64bit handler, we need at least one
828 * free instruction slot for the wrap-around branch. In worst
829 * case, if the intended insertion point is a delay slot, we
830 * need three, with the second nop'ed and the third being
833 /* Loongson2 ebase is different than r4k, we have more space */
834 #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
835 if ((p - tlb_handler) > 64)
836 panic("TLB refill handler space exceeded");
838 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
839 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
840 && uasm_insn_has_bdelay(relocs,
841 tlb_handler + MIPS64_REFILL_INSNS - 3)))
842 panic("TLB refill handler space exceeded");
846 * Now fold the handler in the TLB refill handler space.
848 #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
850 /* Simplest case, just copy the handler. */
851 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
852 final_len = p - tlb_handler;
853 #else /* CONFIG_64BIT */
854 f = final_handler + MIPS64_REFILL_INSNS;
855 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
856 /* Just copy the handler. */
857 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
858 final_len = p - tlb_handler;
860 #if defined(CONFIG_HUGETLB_PAGE)
861 const enum label_id ls = label_tlb_huge_update;
863 const enum label_id ls = label_vmalloc;
869 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
871 BUG_ON(i == ARRAY_SIZE(labels));
872 split = labels[i].addr;
875 * See if we have overflown one way or the other.
877 if (split > tlb_handler + MIPS64_REFILL_INSNS ||
878 split < p - MIPS64_REFILL_INSNS)
883 * Split two instructions before the end. One
884 * for the branch and one for the instruction
887 split = tlb_handler + MIPS64_REFILL_INSNS - 2;
890 * If the branch would fall in a delay slot,
891 * we must back up an additional instruction
892 * so that it is no longer in a delay slot.
894 if (uasm_insn_has_bdelay(relocs, split - 1))
897 /* Copy first part of the handler. */
898 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
899 f += split - tlb_handler;
903 uasm_l_split(&l, final_handler);
904 uasm_il_b(&f, &r, label_split);
905 if (uasm_insn_has_bdelay(relocs, split))
908 uasm_copy_handler(relocs, labels,
909 split, split + 1, f);
910 uasm_move_labels(labels, f, f + 1, -1);
916 /* Copy the rest of the handler. */
917 uasm_copy_handler(relocs, labels, split, p, final_handler);
918 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
921 #endif /* CONFIG_64BIT */
923 uasm_resolve_relocs(relocs, labels);
924 pr_debug("Wrote TLB refill handler (%u instructions).\n",
927 memcpy((void *)ebase, final_handler, 0x100);
929 dump_handler((u32 *)ebase, 64);
933 * TLB load/store/modify handlers.
935 * Only the fastpath gets synthesized at runtime, the slowpath for
936 * do_page_fault remains normal asm.
938 extern void tlb_do_page_fault_0(void);
939 extern void tlb_do_page_fault_1(void);
942 * 128 instructions for the fastpath handler is generous and should
945 #define FASTPATH_SIZE 128
947 u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned;
948 u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned;
949 u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned;
951 static void __cpuinit
952 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
955 # ifdef CONFIG_64BIT_PHYS_ADDR
957 uasm_i_lld(p, pte, 0, ptr);
960 UASM_i_LL(p, pte, 0, ptr);
962 # ifdef CONFIG_64BIT_PHYS_ADDR
964 uasm_i_ld(p, pte, 0, ptr);
967 UASM_i_LW(p, pte, 0, ptr);
971 static void __cpuinit
972 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
975 #ifdef CONFIG_64BIT_PHYS_ADDR
976 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
979 uasm_i_ori(p, pte, pte, mode);
981 # ifdef CONFIG_64BIT_PHYS_ADDR
983 uasm_i_scd(p, pte, 0, ptr);
986 UASM_i_SC(p, pte, 0, ptr);
988 if (r10000_llsc_war())
989 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
991 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
993 # ifdef CONFIG_64BIT_PHYS_ADDR
994 if (!cpu_has_64bits) {
995 /* no uasm_i_nop needed */
996 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
997 uasm_i_ori(p, pte, pte, hwmode);
998 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
999 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1000 /* no uasm_i_nop needed */
1001 uasm_i_lw(p, pte, 0, ptr);
1008 # ifdef CONFIG_64BIT_PHYS_ADDR
1010 uasm_i_sd(p, pte, 0, ptr);
1013 UASM_i_SW(p, pte, 0, ptr);
1015 # ifdef CONFIG_64BIT_PHYS_ADDR
1016 if (!cpu_has_64bits) {
1017 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
1018 uasm_i_ori(p, pte, pte, hwmode);
1019 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1020 uasm_i_lw(p, pte, 0, ptr);
1027 * Check if PTE is present, if not then jump to LABEL. PTR points to
1028 * the page table where this PTE is located, PTE will be re-loaded
1029 * with it's original value.
1031 static void __cpuinit
1032 build_pte_present(u32 **p, struct uasm_reloc **r,
1033 unsigned int pte, unsigned int ptr, enum label_id lid)
1035 if (kernel_uses_smartmips_rixi) {
1036 uasm_i_andi(p, pte, pte, _PAGE_PRESENT);
1037 uasm_il_beqz(p, r, pte, lid);
1039 uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
1040 uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
1041 uasm_il_bnez(p, r, pte, lid);
1043 iPTE_LW(p, pte, ptr);
1046 /* Make PTE valid, store result in PTR. */
1047 static void __cpuinit
1048 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
1051 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1053 iPTE_SW(p, r, pte, ptr, mode);
1057 * Check if PTE can be written to, if not branch to LABEL. Regardless
1058 * restore PTE with value from PTR when done.
1060 static void __cpuinit
1061 build_pte_writable(u32 **p, struct uasm_reloc **r,
1062 unsigned int pte, unsigned int ptr, enum label_id lid)
1064 uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
1065 uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
1066 uasm_il_bnez(p, r, pte, lid);
1067 iPTE_LW(p, pte, ptr);
1070 /* Make PTE writable, update software status bits as well, then store
1073 static void __cpuinit
1074 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
1077 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1080 iPTE_SW(p, r, pte, ptr, mode);
1084 * Check if PTE can be modified, if not branch to LABEL. Regardless
1085 * restore PTE with value from PTR when done.
1087 static void __cpuinit
1088 build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1089 unsigned int pte, unsigned int ptr, enum label_id lid)
1091 uasm_i_andi(p, pte, pte, _PAGE_WRITE);
1092 uasm_il_beqz(p, r, pte, lid);
1093 iPTE_LW(p, pte, ptr);
1096 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1098 * R3000 style TLB load/store/modify handlers.
1102 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1105 static void __cpuinit
1106 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1108 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1109 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1112 uasm_i_rfe(p); /* branch delay */
1116 * This places the pte into ENTRYLO0 and writes it with tlbwi
1117 * or tlbwr as appropriate. This is because the index register
1118 * may have the probe fail bit set as a result of a trap on a
1119 * kseg2 access, i.e. without refill. Then it returns.
1121 static void __cpuinit
1122 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
1123 struct uasm_reloc **r, unsigned int pte,
1126 uasm_i_mfc0(p, tmp, C0_INDEX);
1127 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1128 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1129 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
1130 uasm_i_tlbwi(p); /* cp0 delay */
1132 uasm_i_rfe(p); /* branch delay */
1133 uasm_l_r3000_write_probe_fail(l, *p);
1134 uasm_i_tlbwr(p); /* cp0 delay */
1136 uasm_i_rfe(p); /* branch delay */
1139 static void __cpuinit
1140 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1143 long pgdc = (long)pgd_current;
1145 uasm_i_mfc0(p, pte, C0_BADVADDR);
1146 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
1147 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
1148 uasm_i_srl(p, pte, pte, 22); /* load delay */
1149 uasm_i_sll(p, pte, pte, 2);
1150 uasm_i_addu(p, ptr, ptr, pte);
1151 uasm_i_mfc0(p, pte, C0_CONTEXT);
1152 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
1153 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
1154 uasm_i_addu(p, ptr, ptr, pte);
1155 uasm_i_lw(p, pte, 0, ptr);
1156 uasm_i_tlbp(p); /* load delay */
1159 static void __cpuinit build_r3000_tlb_load_handler(void)
1161 u32 *p = handle_tlbl;
1162 struct uasm_label *l = labels;
1163 struct uasm_reloc *r = relocs;
1165 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1166 memset(labels, 0, sizeof(labels));
1167 memset(relocs, 0, sizeof(relocs));
1169 build_r3000_tlbchange_handler_head(&p, K0, K1);
1170 build_pte_present(&p, &r, K0, K1, label_nopage_tlbl);
1171 uasm_i_nop(&p); /* load delay */
1172 build_make_valid(&p, &r, K0, K1);
1173 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1175 uasm_l_nopage_tlbl(&l, p);
1176 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1179 if ((p - handle_tlbl) > FASTPATH_SIZE)
1180 panic("TLB load handler fastpath space exceeded");
1182 uasm_resolve_relocs(relocs, labels);
1183 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1184 (unsigned int)(p - handle_tlbl));
1186 dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
1189 static void __cpuinit build_r3000_tlb_store_handler(void)
1191 u32 *p = handle_tlbs;
1192 struct uasm_label *l = labels;
1193 struct uasm_reloc *r = relocs;
1195 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1196 memset(labels, 0, sizeof(labels));
1197 memset(relocs, 0, sizeof(relocs));
1199 build_r3000_tlbchange_handler_head(&p, K0, K1);
1200 build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs);
1201 uasm_i_nop(&p); /* load delay */
1202 build_make_write(&p, &r, K0, K1);
1203 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1205 uasm_l_nopage_tlbs(&l, p);
1206 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1209 if ((p - handle_tlbs) > FASTPATH_SIZE)
1210 panic("TLB store handler fastpath space exceeded");
1212 uasm_resolve_relocs(relocs, labels);
1213 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1214 (unsigned int)(p - handle_tlbs));
1216 dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
1219 static void __cpuinit build_r3000_tlb_modify_handler(void)
1221 u32 *p = handle_tlbm;
1222 struct uasm_label *l = labels;
1223 struct uasm_reloc *r = relocs;
1225 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1226 memset(labels, 0, sizeof(labels));
1227 memset(relocs, 0, sizeof(relocs));
1229 build_r3000_tlbchange_handler_head(&p, K0, K1);
1230 build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm);
1231 uasm_i_nop(&p); /* load delay */
1232 build_make_write(&p, &r, K0, K1);
1233 build_r3000_pte_reload_tlbwi(&p, K0, K1);
1235 uasm_l_nopage_tlbm(&l, p);
1236 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1239 if ((p - handle_tlbm) > FASTPATH_SIZE)
1240 panic("TLB modify handler fastpath space exceeded");
1242 uasm_resolve_relocs(relocs, labels);
1243 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1244 (unsigned int)(p - handle_tlbm));
1246 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
1248 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
1251 * R4000 style TLB load/store/modify handlers.
1253 static void __cpuinit
1254 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
1255 struct uasm_reloc **r, unsigned int pte,
1259 build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
1261 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
1264 #ifdef CONFIG_HUGETLB_PAGE
1266 * For huge tlb entries, pmd doesn't contain an address but
1267 * instead contains the tlb pte. Check the PAGE_HUGE bit and
1268 * see if we need to jump to huge tlb processing.
1270 build_is_huge_pte(p, r, pte, ptr, label_tlb_huge_update);
1273 UASM_i_MFC0(p, pte, C0_BADVADDR);
1274 UASM_i_LW(p, ptr, 0, ptr);
1275 UASM_i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
1276 uasm_i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
1277 UASM_i_ADDU(p, ptr, ptr, pte);
1280 uasm_l_smp_pgtable_change(l, *p);
1282 iPTE_LW(p, pte, ptr); /* get even pte */
1283 if (!m4kc_tlbp_war())
1284 build_tlb_probe_entry(p);
1287 static void __cpuinit
1288 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
1289 struct uasm_reloc **r, unsigned int tmp,
1292 uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
1293 uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
1294 build_update_entries(p, tmp, ptr);
1295 build_tlb_write_entry(p, l, r, tlb_indexed);
1296 uasm_l_leave(l, *p);
1297 uasm_i_eret(p); /* return from trap */
1300 build_get_pgd_vmalloc64(p, l, r, tmp, ptr);
1304 static void __cpuinit build_r4000_tlb_load_handler(void)
1306 u32 *p = handle_tlbl;
1307 struct uasm_label *l = labels;
1308 struct uasm_reloc *r = relocs;
1310 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1311 memset(labels, 0, sizeof(labels));
1312 memset(relocs, 0, sizeof(relocs));
1314 if (bcm1250_m3_war()) {
1315 UASM_i_MFC0(&p, K0, C0_BADVADDR);
1316 UASM_i_MFC0(&p, K1, C0_ENTRYHI);
1317 uasm_i_xor(&p, K0, K0, K1);
1318 UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
1319 uasm_il_bnez(&p, &r, K0, label_leave);
1320 /* No need for uasm_i_nop */
1323 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1324 build_pte_present(&p, &r, K0, K1, label_nopage_tlbl);
1325 if (m4kc_tlbp_war())
1326 build_tlb_probe_entry(&p);
1328 if (kernel_uses_smartmips_rixi) {
1330 * If the page is not _PAGE_VALID, RI or XI could not
1331 * have triggered it. Skip the expensive test..
1333 uasm_i_andi(&p, K0, K0, _PAGE_VALID);
1334 uasm_il_beqz(&p, &r, K0, label_tlbl_goaround1);
1338 /* Examine entrylo 0 or 1 based on ptr. */
1339 uasm_i_andi(&p, K0, K1, sizeof(pte_t));
1340 uasm_i_beqz(&p, K0, 8);
1342 UASM_i_MFC0(&p, K0, C0_ENTRYLO0); /* load it in the delay slot*/
1343 UASM_i_MFC0(&p, K0, C0_ENTRYLO1); /* load it if ptr is odd */
1345 * If the entryLo (now in K0) is valid (bit 1), RI or
1346 * XI must have triggered it.
1348 uasm_i_andi(&p, K0, K0, 2);
1349 uasm_il_bnez(&p, &r, K0, label_nopage_tlbl);
1351 uasm_l_tlbl_goaround1(&l, p);
1352 /* Reload the PTE value */
1353 iPTE_LW(&p, K0, K1);
1355 build_make_valid(&p, &r, K0, K1);
1356 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1358 #ifdef CONFIG_HUGETLB_PAGE
1360 * This is the entry point when build_r4000_tlbchange_handler_head
1361 * spots a huge page.
1363 uasm_l_tlb_huge_update(&l, p);
1364 iPTE_LW(&p, K0, K1);
1365 build_pte_present(&p, &r, K0, K1, label_nopage_tlbl);
1366 build_tlb_probe_entry(&p);
1368 if (kernel_uses_smartmips_rixi) {
1370 * If the page is not _PAGE_VALID, RI or XI could not
1371 * have triggered it. Skip the expensive test..
1373 uasm_i_andi(&p, K0, K0, _PAGE_VALID);
1374 uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2);
1378 /* Examine entrylo 0 or 1 based on ptr. */
1379 uasm_i_andi(&p, K0, K1, sizeof(pte_t));
1380 uasm_i_beqz(&p, K0, 8);
1382 UASM_i_MFC0(&p, K0, C0_ENTRYLO0); /* load it in the delay slot*/
1383 UASM_i_MFC0(&p, K0, C0_ENTRYLO1); /* load it if ptr is odd */
1385 * If the entryLo (now in K0) is valid (bit 1), RI or
1386 * XI must have triggered it.
1388 uasm_i_andi(&p, K0, K0, 2);
1389 uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2);
1390 /* Reload the PTE value */
1391 iPTE_LW(&p, K0, K1);
1394 * We clobbered C0_PAGEMASK, restore it. On the other branch
1395 * it is restored in build_huge_tlb_write_entry.
1397 build_restore_pagemask(&p, &r, K0, label_nopage_tlbl);
1399 uasm_l_tlbl_goaround2(&l, p);
1401 uasm_i_ori(&p, K0, K0, (_PAGE_ACCESSED | _PAGE_VALID));
1402 build_huge_handler_tail(&p, &r, &l, K0, K1);
1405 uasm_l_nopage_tlbl(&l, p);
1406 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1409 if ((p - handle_tlbl) > FASTPATH_SIZE)
1410 panic("TLB load handler fastpath space exceeded");
1412 uasm_resolve_relocs(relocs, labels);
1413 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1414 (unsigned int)(p - handle_tlbl));
1416 dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
1419 static void __cpuinit build_r4000_tlb_store_handler(void)
1421 u32 *p = handle_tlbs;
1422 struct uasm_label *l = labels;
1423 struct uasm_reloc *r = relocs;
1425 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1426 memset(labels, 0, sizeof(labels));
1427 memset(relocs, 0, sizeof(relocs));
1429 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1430 build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs);
1431 if (m4kc_tlbp_war())
1432 build_tlb_probe_entry(&p);
1433 build_make_write(&p, &r, K0, K1);
1434 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1436 #ifdef CONFIG_HUGETLB_PAGE
1438 * This is the entry point when
1439 * build_r4000_tlbchange_handler_head spots a huge page.
1441 uasm_l_tlb_huge_update(&l, p);
1442 iPTE_LW(&p, K0, K1);
1443 build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs);
1444 build_tlb_probe_entry(&p);
1445 uasm_i_ori(&p, K0, K0,
1446 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
1447 build_huge_handler_tail(&p, &r, &l, K0, K1);
1450 uasm_l_nopage_tlbs(&l, p);
1451 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1454 if ((p - handle_tlbs) > FASTPATH_SIZE)
1455 panic("TLB store handler fastpath space exceeded");
1457 uasm_resolve_relocs(relocs, labels);
1458 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1459 (unsigned int)(p - handle_tlbs));
1461 dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
1464 static void __cpuinit build_r4000_tlb_modify_handler(void)
1466 u32 *p = handle_tlbm;
1467 struct uasm_label *l = labels;
1468 struct uasm_reloc *r = relocs;
1470 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1471 memset(labels, 0, sizeof(labels));
1472 memset(relocs, 0, sizeof(relocs));
1474 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1475 build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm);
1476 if (m4kc_tlbp_war())
1477 build_tlb_probe_entry(&p);
1478 /* Present and writable bits set, set accessed and dirty bits. */
1479 build_make_write(&p, &r, K0, K1);
1480 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1482 #ifdef CONFIG_HUGETLB_PAGE
1484 * This is the entry point when
1485 * build_r4000_tlbchange_handler_head spots a huge page.
1487 uasm_l_tlb_huge_update(&l, p);
1488 iPTE_LW(&p, K0, K1);
1489 build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm);
1490 build_tlb_probe_entry(&p);
1491 uasm_i_ori(&p, K0, K0,
1492 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
1493 build_huge_handler_tail(&p, &r, &l, K0, K1);
1496 uasm_l_nopage_tlbm(&l, p);
1497 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1500 if ((p - handle_tlbm) > FASTPATH_SIZE)
1501 panic("TLB modify handler fastpath space exceeded");
1503 uasm_resolve_relocs(relocs, labels);
1504 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1505 (unsigned int)(p - handle_tlbm));
1507 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
1510 void __cpuinit build_tlb_refill_handler(void)
1513 * The refill handler is generated per-CPU, multi-node systems
1514 * may have local storage for it. The other handlers are only
1517 static int run_once = 0;
1519 switch (current_cpu_type()) {
1527 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1528 build_r3000_tlb_refill_handler();
1530 build_r3000_tlb_load_handler();
1531 build_r3000_tlb_store_handler();
1532 build_r3000_tlb_modify_handler();
1536 panic("No R3000 TLB refill handler");
1542 panic("No R6000 TLB refill handler yet");
1546 panic("No R8000 TLB refill handler yet");
1550 build_r4000_tlb_refill_handler();
1552 build_r4000_tlb_load_handler();
1553 build_r4000_tlb_store_handler();
1554 build_r4000_tlb_modify_handler();
1560 void __cpuinit flush_tlb_handlers(void)
1562 local_flush_icache_range((unsigned long)handle_tlbl,
1563 (unsigned long)handle_tlbl + sizeof(handle_tlbl));
1564 local_flush_icache_range((unsigned long)handle_tlbs,
1565 (unsigned long)handle_tlbs + sizeof(handle_tlbs));
1566 local_flush_icache_range((unsigned long)handle_tlbm,
1567 (unsigned long)handle_tlbm + sizeof(handle_tlbm));