SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/mips/mm/c-r4k.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
   7  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  */
  10 #include <linux/config.h>
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/sched.h>
  14 #include <linux/mm.h>
  15 #include <linux/bitops.h>
  16
  17 #include <asm/bcache.h>
  18 #include <asm/bootinfo.h>
  19 #include <asm/cacheops.h>
  20 #include <asm/cpu.h>
  21 #include <asm/cpu-features.h>
  22 #include <asm/io.h>
  23 #include <asm/page.h>
  24 #include <asm/pgtable.h>
  25 #include <asm/r4kcache.h>
  26 #include <asm/system.h>
  27 #include <asm/mmu_context.h>
  28 #include <asm/war.h>
  29 #include <asm/cacheflush.h> /* for run_uncached() */
  30
  31 static unsigned long icache_size, dcache_size, scache_size;
  32
  33 /*
  34  * Dummy cache handling routines for machines without boardcaches
  35  */
  36 static void no_sc_noop(void) {}
  37
  38 static struct bcache_ops no_sc_ops = {
  39         .bc_enable = (void *)no_sc_noop,
  40         .bc_disable = (void *)no_sc_noop,
  41         .bc_wback_inv = (void *)no_sc_noop,
  42         .bc_inv = (void *)no_sc_noop
  43 };
  44
  45 struct bcache_ops *bcops = &no_sc_ops;
  46
  47 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x2010)
  48 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x2020)
  49
  50 #define R4600_HIT_CACHEOP_WAR_IMPL                                      \
  51 do {                                                                    \
  52         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())            \
  53                 *(volatile unsigned long *)CKSEG1;                      \
  54         if (R4600_V1_HIT_CACHEOP_WAR)                                   \
  55                 __asm__ __volatile__("nop;nop;nop;nop");                \
  56 } while (0)
  57
  58 static void (*r4k_blast_dcache_page)(unsigned long addr);
  59
  60 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
  61 {
  62         R4600_HIT_CACHEOP_WAR_IMPL;
  63         blast_dcache32_page(addr);
  64 }
  65
  66 static inline void r4k_blast_dcache_page_setup(void)
  67 {
  68         unsigned long  dc_lsize = cpu_dcache_line_size();
  69
  70         if (dc_lsize == 16)
  71                 r4k_blast_dcache_page = blast_dcache16_page;
  72         else if (dc_lsize == 32)
  73                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
  74 }
  75
  76 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
  77
  78 static inline void r4k_blast_dcache_page_indexed_setup(void)
  79 {
  80         unsigned long dc_lsize = cpu_dcache_line_size();
  81
  82         if (dc_lsize == 16)
  83                 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
  84         else if (dc_lsize == 32)
  85                 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
  86 }
  87
  88 static void (* r4k_blast_dcache)(void);
  89
  90 static inline void r4k_blast_dcache_setup(void)
  91 {
  92         unsigned long dc_lsize = cpu_dcache_line_size();
  93
  94         if (dc_lsize == 16)
  95                 r4k_blast_dcache = blast_dcache16;
  96         else if (dc_lsize == 32)
  97                 r4k_blast_dcache = blast_dcache32;
  98 }
  99
 100 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
 101 #define JUMP_TO_ALIGN(order) \
 102         __asm__ __volatile__( \
 103                 "b\t1f\n\t" \
 104                 ".align\t" #order "\n\t" \
 105                 "1:\n\t" \
 106                 )
 107 #define CACHE32_UNROLL32_ALIGN  JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
 108 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
 109
 110 static inline void blast_r4600_v1_icache32(void)
 111 {
 112         unsigned long flags;
 113
 114         local_irq_save(flags);
 115         blast_icache32();
 116         local_irq_restore(flags);
 117 }
 118
 119 static inline void tx49_blast_icache32(void)
 120 {
 121         unsigned long start = INDEX_BASE;
 122         unsigned long end = start + current_cpu_data.icache.waysize;
 123         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 124         unsigned long ws_end = current_cpu_data.icache.ways <<
 125                                current_cpu_data.icache.waybit;
 126         unsigned long ws, addr;
 127
 128         CACHE32_UNROLL32_ALIGN2;
 129         /* I'm in even chunk.  blast odd chunks */
 130         for (ws = 0; ws < ws_end; ws += ws_inc)
 131                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 132                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 133         CACHE32_UNROLL32_ALIGN;
 134         /* I'm in odd chunk.  blast even chunks */
 135         for (ws = 0; ws < ws_end; ws += ws_inc)
 136                 for (addr = start; addr < end; addr += 0x400 * 2)
 137                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 138 }
 139
 140 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
 141 {
 142         unsigned long flags;
 143
 144         local_irq_save(flags);
 145         blast_icache32_page_indexed(page);
 146         local_irq_restore(flags);
 147 }
 148
 149 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
 150 {
 151         unsigned long start = page;
 152         unsigned long end = start + PAGE_SIZE;
 153         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 154         unsigned long ws_end = current_cpu_data.icache.ways <<
 155                                current_cpu_data.icache.waybit;
 156         unsigned long ws, addr;
 157
 158         CACHE32_UNROLL32_ALIGN2;
 159         /* I'm in even chunk.  blast odd chunks */
 160         for (ws = 0; ws < ws_end; ws += ws_inc)
 161                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 162                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 163         CACHE32_UNROLL32_ALIGN;
 164         /* I'm in odd chunk.  blast even chunks */
 165         for (ws = 0; ws < ws_end; ws += ws_inc)
 166                 for (addr = start; addr < end; addr += 0x400 * 2)
 167                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 168 }
 169
 170 static void (* r4k_blast_icache_page)(unsigned long addr);
 171
 172 static inline void r4k_blast_icache_page_setup(void)
 173 {
 174         unsigned long ic_lsize = cpu_icache_line_size();
 175
 176         if (ic_lsize == 16)
 177                 r4k_blast_icache_page = blast_icache16_page;
 178         else if (ic_lsize == 32)
 179                 r4k_blast_icache_page = blast_icache32_page;
 180         else if (ic_lsize == 64)
 181                 r4k_blast_icache_page = blast_icache64_page;
 182 }
 183
 184
 185 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
 186
 187 static inline void r4k_blast_icache_page_indexed_setup(void)
 188 {
 189         unsigned long ic_lsize = cpu_icache_line_size();
 190
 191         if (ic_lsize == 16)
 192                 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
 193         else if (ic_lsize == 32) {
 194                 if (TX49XX_ICACHE_INDEX_INV_WAR)
 195                         r4k_blast_icache_page_indexed =
 196                                 tx49_blast_icache32_page_indexed;
 197                 else if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 198                         r4k_blast_icache_page_indexed =
 199                                 blast_icache32_r4600_v1_page_indexed;
 200                 else
 201                         r4k_blast_icache_page_indexed =
 202                                 blast_icache32_page_indexed;
 203         } else if (ic_lsize == 64)
 204                 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
 205 }
 206
 207 static void (* r4k_blast_icache)(void);
 208
 209 static inline void r4k_blast_icache_setup(void)
 210 {
 211         unsigned long ic_lsize = cpu_icache_line_size();
 212
 213         if (ic_lsize == 16)
 214                 r4k_blast_icache = blast_icache16;
 215         else if (ic_lsize == 32) {
 216                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 217                         r4k_blast_icache = blast_r4600_v1_icache32;
 218                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 219                         r4k_blast_icache = tx49_blast_icache32;
 220                 else
 221                         r4k_blast_icache = blast_icache32;
 222         } else if (ic_lsize == 64)
 223                 r4k_blast_icache = blast_icache64;
 224 }
 225
 226 static void (* r4k_blast_scache_page)(unsigned long addr);
 227
 228 static inline void r4k_blast_scache_page_setup(void)
 229 {
 230         unsigned long sc_lsize = cpu_scache_line_size();
 231
 232         if (sc_lsize == 16)
 233                 r4k_blast_scache_page = blast_scache16_page;
 234         else if (sc_lsize == 32)
 235                 r4k_blast_scache_page = blast_scache32_page;
 236         else if (sc_lsize == 64)
 237                 r4k_blast_scache_page = blast_scache64_page;
 238         else if (sc_lsize == 128)
 239                 r4k_blast_scache_page = blast_scache128_page;
 240 }
 241
 242 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
 243
 244 static inline void r4k_blast_scache_page_indexed_setup(void)
 245 {
 246         unsigned long sc_lsize = cpu_scache_line_size();
 247
 248         if (sc_lsize == 16)
 249                 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
 250         else if (sc_lsize == 32)
 251                 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
 252         else if (sc_lsize == 64)
 253                 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
 254         else if (sc_lsize == 128)
 255                 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
 256 }
 257
 258 static void (* r4k_blast_scache)(void);
 259
 260 static inline void r4k_blast_scache_setup(void)
 261 {
 262         unsigned long sc_lsize = cpu_scache_line_size();
 263
 264         if (sc_lsize == 16)
 265                 r4k_blast_scache = blast_scache16;
 266         else if (sc_lsize == 32)
 267                 r4k_blast_scache = blast_scache32;
 268         else if (sc_lsize == 64)
 269                 r4k_blast_scache = blast_scache64;
 270         else if (sc_lsize == 128)
 271                 r4k_blast_scache = blast_scache128;
 272 }
 273
 274 /*
 275  * This is former mm's flush_cache_all() which really should be
 276  * flush_cache_vunmap these days ...
 277  */
 278 static inline void local_r4k_flush_cache_all(void * args)
 279 {
 280         r4k_blast_dcache();
 281         r4k_blast_icache();
 282 }
 283
 284 static void r4k_flush_cache_all(void)
 285 {
 286         if (!cpu_has_dc_aliases)
 287                 return;
 288
 289         on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
 290 }
 291
 292 static inline void local_r4k___flush_cache_all(void * args)
 293 {
 294         r4k_blast_dcache();
 295         r4k_blast_icache();
 296
 297         switch (current_cpu_data.cputype) {
 298         case CPU_R4000SC:
 299         case CPU_R4000MC:
 300         case CPU_R4400SC:
 301         case CPU_R4400MC:
 302         case CPU_R10000:
 303         case CPU_R12000:
 304                 r4k_blast_scache();
 305         }
 306 }
 307
 308 static void r4k___flush_cache_all(void)
 309 {
 310         on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1);
 311 }
 312
 313 static inline void local_r4k_flush_cache_range(void * args)
 314 {
 315         struct vm_area_struct *vma = args;
 316         int exec;
 317
 318         if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
 319                 return;
 320
 321         exec = vma->vm_flags & VM_EXEC;
 322         if (cpu_has_dc_aliases || exec)
 323                 r4k_blast_dcache();
 324         if (exec)
 325                 r4k_blast_icache();
 326 }
 327
 328 static void r4k_flush_cache_range(struct vm_area_struct *vma,
 329         unsigned long start, unsigned long end)
 330 {
 331         on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
 332 }
 333
 334 static inline void local_r4k_flush_cache_mm(void * args)
 335 {
 336         struct mm_struct *mm = args;
 337
 338         if (!cpu_context(smp_processor_id(), mm))
 339                 return;
 340
 341         r4k_blast_dcache();
 342         r4k_blast_icache();
 343
 344         /*
 345          * Kludge alert.  For obscure reasons R4000SC and R4400SC go nuts if we
 346          * only flush the primary caches but R10000 and R12000 behave sane ...
 347          */
 348         if (current_cpu_data.cputype == CPU_R4000SC ||
 349             current_cpu_data.cputype == CPU_R4000MC ||
 350             current_cpu_data.cputype == CPU_R4400SC ||
 351             current_cpu_data.cputype == CPU_R4400MC)
 352                 r4k_blast_scache();
 353 }
 354
 355 static void r4k_flush_cache_mm(struct mm_struct *mm)
 356 {
 357         if (!cpu_has_dc_aliases)
 358                 return;
 359
 360         on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);
 361 }
 362
 363 struct flush_cache_page_args {
 364         struct vm_area_struct *vma;
 365         unsigned long page;
 366 };
 367
 368 static inline void local_r4k_flush_cache_page(void *args)
 369 {
 370         struct flush_cache_page_args *fcp_args = args;
 371         struct vm_area_struct *vma = fcp_args->vma;
 372         unsigned long page = fcp_args->page;
 373         int exec = vma->vm_flags & VM_EXEC;
 374         struct mm_struct *mm = vma->vm_mm;
 375         pgd_t *pgdp;
 376         pud_t *pudp;
 377         pmd_t *pmdp;
 378         pte_t *ptep;
 379
 380         /*
 381          * If ownes no valid ASID yet, cannot possibly have gotten
 382          * this page into the cache.
 383          */
 384         if (cpu_context(smp_processor_id(), mm) == 0)
 385                 return;
 386
 387         page &= PAGE_MASK;
 388         pgdp = pgd_offset(mm, page);
 389         pudp = pud_offset(pgdp, page);
 390         pmdp = pmd_offset(pudp, page);
 391         ptep = pte_offset(pmdp, page);
 392
 393         /*
 394          * If the page isn't marked valid, the page cannot possibly be
 395          * in the cache.
 396          */
 397         if (!(pte_val(*ptep) & _PAGE_PRESENT))
 398                 return;
 399
 400         /*
 401          * Doing flushes for another ASID than the current one is
 402          * too difficult since stupid R4k caches do a TLB translation
 403          * for every cache flush operation.  So we do indexed flushes
 404          * in that case, which doesn't overly flush the cache too much.
 405          */
 406         if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
 407                 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
 408                         r4k_blast_dcache_page(page);
 409                         if (exec && !cpu_icache_snoops_remote_store)
 410                                 r4k_blast_scache_page(page);
 411                 }
 412                 if (exec)
 413                         r4k_blast_icache_page(page);
 414
 415                 return;
 416         }
 417
 418         /*
 419          * Do indexed flush, too much work to get the (possible) TLB refills
 420          * to work correctly.
 421          */
 422         page = INDEX_BASE + (page & (dcache_size - 1));
 423         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
 424                 r4k_blast_dcache_page_indexed(page);
 425                 if (exec && !cpu_icache_snoops_remote_store)
 426                         r4k_blast_scache_page_indexed(page);
 427         }
 428         if (exec) {
 429                 if (cpu_has_vtag_icache) {
 430                         int cpu = smp_processor_id();
 431
 432                         if (cpu_context(cpu, mm) != 0)
 433                                 drop_mmu_context(mm, cpu);
 434                 } else
 435                         r4k_blast_icache_page_indexed(page);
 436         }
 437 }
 438
 439 static void r4k_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn)
 440 {
 441         struct flush_cache_page_args args;
 442
 443         args.vma = vma;
 444         args.page = page;
 445
 446         on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);
 447 }
 448
 449 static inline void local_r4k_flush_data_cache_page(void * addr)
 450 {
 451         r4k_blast_dcache_page((unsigned long) addr);
 452 }
 453
 454 static void r4k_flush_data_cache_page(unsigned long addr)
 455 {
 456         on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1);
 457 }
 458
 459 struct flush_icache_range_args {
 460         unsigned long __user start;
 461         unsigned long __user end;
 462 };
 463
 464 static inline void local_r4k_flush_icache_range(void *args)
 465 {
 466         struct flush_icache_range_args *fir_args = args;
 467         unsigned long dc_lsize = current_cpu_data.dcache.linesz;
 468         unsigned long ic_lsize = current_cpu_data.icache.linesz;
 469         unsigned long sc_lsize = current_cpu_data.scache.linesz;
 470         unsigned long start = fir_args->start;
 471         unsigned long end = fir_args->end;
 472         unsigned long addr, aend;
 473
 474         if (!cpu_has_ic_fills_f_dc) {
 475                 if (end - start > dcache_size) {
 476                         r4k_blast_dcache();
 477                 } else {
 478                         addr = start & ~(dc_lsize - 1);
 479                         aend = (end - 1) & ~(dc_lsize - 1);
 480
 481                         while (1) {
 482                                 /* Hit_Writeback_Inv_D */
 483                                 protected_writeback_dcache_line(addr);
 484                                 if (addr == aend)
 485                                         break;
 486                                 addr += dc_lsize;
 487                         }
 488                 }
 489
 490                 if (!cpu_icache_snoops_remote_store) {
 491                         if (end - start > scache_size) {
 492                                 r4k_blast_scache();
 493                         } else {
 494                                 addr = start & ~(sc_lsize - 1);
 495                                 aend = (end - 1) & ~(sc_lsize - 1);
 496
 497                                 while (1) {
 498                                         /* Hit_Writeback_Inv_D */
 499                                         protected_writeback_scache_line(addr);
 500                                         if (addr == aend)
 501                                                 break;
 502                                         addr += sc_lsize;
 503                                 }
 504                         }
 505                 }
 506         }
 507
 508         if (end - start > icache_size)
 509                 r4k_blast_icache();
 510         else {
 511                 addr = start & ~(ic_lsize - 1);
 512                 aend = (end - 1) & ~(ic_lsize - 1);
 513                 while (1) {
 514                         /* Hit_Invalidate_I */
 515                         protected_flush_icache_line(addr);
 516                         if (addr == aend)
 517                                 break;
 518                         addr += ic_lsize;
 519                 }
 520         }
 521 }
 522
 523 static void r4k_flush_icache_range(unsigned long __user start,
 524         unsigned long __user end)
 525 {
 526         struct flush_icache_range_args args;
 527
 528         args.start = start;
 529         args.end = end;
 530
 531         on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
 532         instruction_hazard();
 533 }
 534
 535 /*
 536  * Ok, this seriously sucks.  We use them to flush a user page but don't
 537  * know the virtual address, so we have to blast away the whole icache
 538  * which is significantly more expensive than the real thing.  Otoh we at
 539  * least know the kernel address of the page so we can flush it
 540  * selectivly.
 541  */
 542
 543 struct flush_icache_page_args {
 544         struct vm_area_struct *vma;
 545         struct page *page;
 546 };
 547
 548 static inline void local_r4k_flush_icache_page(void *args)
 549 {
 550         struct flush_icache_page_args *fip_args = args;
 551         struct vm_area_struct *vma = fip_args->vma;
 552         struct page *page = fip_args->page;
 553
 554         /*
 555          * Tricky ...  Because we don't know the virtual address we've got the
 556          * choice of either invalidating the entire primary and secondary
 557          * caches or invalidating the secondary caches also.  With the subset
 558          * enforcment on R4000SC, R4400SC, R10000 and R12000 invalidating the
 559          * secondary cache will result in any entries in the primary caches
 560          * also getting invalidated which hopefully is a bit more economical.
 561          */
 562         if (cpu_has_subset_pcaches) {
 563                 unsigned long addr = (unsigned long) page_address(page);
 564
 565                 r4k_blast_scache_page(addr);
 566                 ClearPageDcacheDirty(page);
 567
 568                 return;
 569         }
 570
 571         if (!cpu_has_ic_fills_f_dc) {
 572                 unsigned long addr = (unsigned long) page_address(page);
 573                 r4k_blast_dcache_page(addr);
 574                 if (!cpu_icache_snoops_remote_store)
 575                         r4k_blast_scache_page(addr);
 576                 ClearPageDcacheDirty(page);
 577         }
 578
 579         /*
 580          * We're not sure of the virtual address(es) involved here, so
 581          * we have to flush the entire I-cache.
 582          */
 583         if (cpu_has_vtag_icache) {
 584                 int cpu = smp_processor_id();
 585
 586                 if (cpu_context(cpu, vma->vm_mm) != 0)
 587                         drop_mmu_context(vma->vm_mm, cpu);
 588         } else
 589                 r4k_blast_icache();
 590 }
 591
 592 static void r4k_flush_icache_page(struct vm_area_struct *vma,
 593         struct page *page)
 594 {
 595         struct flush_icache_page_args args;
 596
 597         /*
 598          * If there's no context yet, or the page isn't executable, no I-cache
 599          * flush is needed.
 600          */
 601         if (!(vma->vm_flags & VM_EXEC))
 602                 return;
 603
 604         args.vma = vma;
 605         args.page = page;
 606
 607         on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1);
 608 }
 609
 610
 611 #ifdef CONFIG_DMA_NONCOHERENT
 612
 613 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 614 {
 615         unsigned long end, a;
 616
 617         /* Catch bad driver code */
 618         BUG_ON(size == 0);
 619
 620         if (cpu_has_subset_pcaches) {
 621                 unsigned long sc_lsize = current_cpu_data.scache.linesz;
 622
 623                 if (size >= scache_size) {
 624                         r4k_blast_scache();
 625                         return;
 626                 }
 627
 628                 a = addr & ~(sc_lsize - 1);
 629                 end = (addr + size - 1) & ~(sc_lsize - 1);
 630                 while (1) {
 631                         flush_scache_line(a);   /* Hit_Writeback_Inv_SD */
 632                         if (a == end)
 633                                 break;
 634                         a += sc_lsize;
 635                 }
 636                 return;
 637         }
 638
 639         /*
 640          * Either no secondary cache or the available caches don't have the
 641          * subset property so we have to flush the primary caches
 642          * explicitly
 643          */
 644         if (size >= dcache_size) {
 645                 r4k_blast_dcache();
 646         } else {
 647                 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
 648
 649                 R4600_HIT_CACHEOP_WAR_IMPL;
 650                 a = addr & ~(dc_lsize - 1);
 651                 end = (addr + size - 1) & ~(dc_lsize - 1);
 652                 while (1) {
 653                         flush_dcache_line(a);   /* Hit_Writeback_Inv_D */
 654                         if (a == end)
 655                                 break;
 656                         a += dc_lsize;
 657                 }
 658         }
 659
 660         bc_wback_inv(addr, size);
 661 }
 662
 663 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 664 {
 665         unsigned long end, a;
 666
 667         /* Catch bad driver code */
 668         BUG_ON(size == 0);
 669
 670         if (cpu_has_subset_pcaches) {
 671                 unsigned long sc_lsize = current_cpu_data.scache.linesz;
 672
 673                 if (size >= scache_size) {
 674                         r4k_blast_scache();
 675                         return;
 676                 }
 677
 678                 a = addr & ~(sc_lsize - 1);
 679                 end = (addr + size - 1) & ~(sc_lsize - 1);
 680                 while (1) {
 681                         flush_scache_line(a);   /* Hit_Writeback_Inv_SD */
 682                         if (a == end)
 683                                 break;
 684                         a += sc_lsize;
 685                 }
 686                 return;
 687         }
 688
 689         if (size >= dcache_size) {
 690                 r4k_blast_dcache();
 691         } else {
 692                 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
 693
 694                 R4600_HIT_CACHEOP_WAR_IMPL;
 695                 a = addr & ~(dc_lsize - 1);
 696                 end = (addr + size - 1) & ~(dc_lsize - 1);
 697                 while (1) {
 698                         flush_dcache_line(a);   /* Hit_Writeback_Inv_D */
 699                         if (a == end)
 700                                 break;
 701                         a += dc_lsize;
 702                 }
 703         }
 704
 705         bc_inv(addr, size);
 706 }
 707 #endif /* CONFIG_DMA_NONCOHERENT */
 708
 709 /*
 710  * While we're protected against bad userland addresses we don't care
 711  * very much about what happens in that case.  Usually a segmentation
 712  * fault will dump the process later on anyway ...
 713  */
 714 static void local_r4k_flush_cache_sigtramp(void * arg)
 715 {
 716         unsigned long ic_lsize = current_cpu_data.icache.linesz;
 717         unsigned long dc_lsize = current_cpu_data.dcache.linesz;
 718         unsigned long sc_lsize = current_cpu_data.scache.linesz;
 719         unsigned long addr = (unsigned long) arg;
 720
 721         R4600_HIT_CACHEOP_WAR_IMPL;
 722         protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
 723         if (!cpu_icache_snoops_remote_store)
 724                 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
 725         protected_flush_icache_line(addr & ~(ic_lsize - 1));
 726         if (MIPS4K_ICACHE_REFILL_WAR) {
 727                 __asm__ __volatile__ (
 728                         ".set push\n\t"
 729                         ".set noat\n\t"
 730                         ".set mips3\n\t"
 731 #ifdef CONFIG_32BIT
 732                         "la     $at,1f\n\t"
 733 #endif
 734 #ifdef CONFIG_64BIT
 735                         "dla    $at,1f\n\t"
 736 #endif
 737                         "cache  %0,($at)\n\t"
 738                         "nop; nop; nop\n"
 739                         "1:\n\t"
 740                         ".set pop"
 741                         :
 742                         : "i" (Hit_Invalidate_I));
 743         }
 744         if (MIPS_CACHE_SYNC_WAR)
 745                 __asm__ __volatile__ ("sync");
 746 }
 747
 748 static void r4k_flush_cache_sigtramp(unsigned long addr)
 749 {
 750         on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1);
 751 }
 752
 753 static void r4k_flush_icache_all(void)
 754 {
 755         if (cpu_has_vtag_icache)
 756                 r4k_blast_icache();
 757 }
 758
 759 static inline void rm7k_erratum31(void)
 760 {
 761         const unsigned long ic_lsize = 32;
 762         unsigned long addr;
 763
 764         /* RM7000 erratum #31. The icache is screwed at startup. */
 765         write_c0_taglo(0);
 766         write_c0_taghi(0);
 767
 768         for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
 769                 __asm__ __volatile__ (
 770                         ".set noreorder\n\t"
 771                         ".set mips3\n\t"
 772                         "cache\t%1, 0(%0)\n\t"
 773                         "cache\t%1, 0x1000(%0)\n\t"
 774                         "cache\t%1, 0x2000(%0)\n\t"
 775                         "cache\t%1, 0x3000(%0)\n\t"
 776                         "cache\t%2, 0(%0)\n\t"
 777                         "cache\t%2, 0x1000(%0)\n\t"
 778                         "cache\t%2, 0x2000(%0)\n\t"
 779                         "cache\t%2, 0x3000(%0)\n\t"
 780                         "cache\t%1, 0(%0)\n\t"
 781                         "cache\t%1, 0x1000(%0)\n\t"
 782                         "cache\t%1, 0x2000(%0)\n\t"
 783                         "cache\t%1, 0x3000(%0)\n\t"
 784                         ".set\tmips0\n\t"
 785                         ".set\treorder\n\t"
 786                         :
 787                         : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
 788         }
 789 }
 790
 791 static char *way_string[] __initdata = { NULL, "direct mapped", "2-way",
 792         "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
 793 };
 794
 795 static void __init probe_pcache(void)
 796 {
 797         struct cpuinfo_mips *c = &current_cpu_data;
 798         unsigned int config = read_c0_config();
 799         unsigned int prid = read_c0_prid();
 800         unsigned long config1;
 801         unsigned int lsize;
 802
 803         switch (c->cputype) {
 804         case CPU_R4600:                 /* QED style two way caches? */
 805         case CPU_R4700:
 806         case CPU_R5000:
 807         case CPU_NEVADA:
 808                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 809                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 810                 c->icache.ways = 2;
 811                 c->icache.waybit = ffs(icache_size/2) - 1;
 812
 813                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 814                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 815                 c->dcache.ways = 2;
 816                 c->dcache.waybit= ffs(dcache_size/2) - 1;
 817
 818                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 819                 break;
 820
 821         case CPU_R5432:
 822         case CPU_R5500:
 823                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 824                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 825                 c->icache.ways = 2;
 826                 c->icache.waybit= 0;
 827
 828                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 829                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 830                 c->dcache.ways = 2;
 831                 c->dcache.waybit = 0;
 832
 833                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 834                 break;
 835
 836         case CPU_TX49XX:
 837                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 838                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 839                 c->icache.ways = 4;
 840                 c->icache.waybit= 0;
 841
 842                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 843                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 844                 c->dcache.ways = 4;
 845                 c->dcache.waybit = 0;
 846
 847                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 848                 break;
 849
 850         case CPU_R4000PC:
 851         case CPU_R4000SC:
 852         case CPU_R4000MC:
 853         case CPU_R4400PC:
 854         case CPU_R4400SC:
 855         case CPU_R4400MC:
 856         case CPU_R4300:
 857                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 858                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 859                 c->icache.ways = 1;
 860                 c->icache.waybit = 0;   /* doesn't matter */
 861
 862                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 863                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 864                 c->dcache.ways = 1;
 865                 c->dcache.waybit = 0;   /* does not matter */
 866
 867                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 868                 break;
 869
 870         case CPU_R10000:
 871         case CPU_R12000:
 872                 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
 873                 c->icache.linesz = 64;
 874                 c->icache.ways = 2;
 875                 c->icache.waybit = 0;
 876
 877                 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
 878                 c->dcache.linesz = 32;
 879                 c->dcache.ways = 2;
 880                 c->dcache.waybit = 0;
 881
 882                 c->options |= MIPS_CPU_PREFETCH;
 883                 break;
 884
 885         case CPU_VR4133:
 886                 write_c0_config(config & ~CONF_EB);
 887         case CPU_VR4131:
 888                 /* Workaround for cache instruction bug of VR4131 */
 889                 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
 890                     c->processor_id == 0x0c82U) {
 891                         config &= ~0x00000030U;
 892                         config |= 0x00410000U;
 893                         write_c0_config(config);
 894                 }
 895                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
 896                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 897                 c->icache.ways = 2;
 898                 c->icache.waybit = ffs(icache_size/2) - 1;
 899
 900                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
 901                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 902                 c->dcache.ways = 2;
 903                 c->dcache.waybit = ffs(dcache_size/2) - 1;
 904
 905                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 906                 break;
 907
 908         case CPU_VR41XX:
 909         case CPU_VR4111:
 910         case CPU_VR4121:
 911         case CPU_VR4122:
 912         case CPU_VR4181:
 913         case CPU_VR4181A:
 914                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
 915                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 916                 c->icache.ways = 1;
 917                 c->icache.waybit = 0;   /* doesn't matter */
 918
 919                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
 920                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 921                 c->dcache.ways = 1;
 922                 c->dcache.waybit = 0;   /* does not matter */
 923
 924                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 925                 break;
 926
 927         case CPU_RM7000:
 928                 rm7k_erratum31();
 929
 930         case CPU_RM9000:
 931                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 932                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 933                 c->icache.ways = 4;
 934                 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
 935
 936                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 937                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 938                 c->dcache.ways = 4;
 939                 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
 940
 941 #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
 942                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 943 #endif
 944                 c->options |= MIPS_CPU_PREFETCH;
 945                 break;
 946
 947         default:
 948                 if (!(config & MIPS_CONF_M))
 949                         panic("Don't know how to probe P-caches on this cpu.");
 950
 951                 /*
 952                  * So we seem to be a MIPS32 or MIPS64 CPU
 953                  * So let's probe the I-cache ...
 954                  */
 955                 config1 = read_c0_config1();
 956
 957                 if ((lsize = ((config1 >> 19) & 7)))
 958                         c->icache.linesz = 2 << lsize;
 959                 else
 960                         c->icache.linesz = lsize;
 961                 c->icache.sets = 64 << ((config1 >> 22) & 7);
 962                 c->icache.ways = 1 + ((config1 >> 16) & 7);
 963
 964                 icache_size = c->icache.sets *
 965                               c->icache.ways *
 966                               c->icache.linesz;
 967                 c->icache.waybit = ffs(icache_size/c->icache.ways) - 1;
 968
 969                 if (config & 0x8)               /* VI bit */
 970                         c->icache.flags |= MIPS_CACHE_VTAG;
 971
 972                 /*
 973                  * Now probe the MIPS32 / MIPS64 data cache.
 974                  */
 975                 c->dcache.flags = 0;
 976
 977                 if ((lsize = ((config1 >> 10) & 7)))
 978                         c->dcache.linesz = 2 << lsize;
 979                 else
 980                         c->dcache.linesz= lsize;
 981                 c->dcache.sets = 64 << ((config1 >> 13) & 7);
 982                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
 983
 984                 dcache_size = c->dcache.sets *
 985                               c->dcache.ways *
 986                               c->dcache.linesz;
 987                 c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1;
 988
 989                 c->options |= MIPS_CPU_PREFETCH;
 990                 break;
 991         }
 992
 993         /*
 994          * Processor configuration sanity check for the R4000SC erratum
 995          * #5.  With page sizes larger than 32kB there is no possibility
 996          * to get a VCE exception anymore so we don't care about this
 997          * misconfiguration.  The case is rather theoretical anyway;
 998          * presumably no vendor is shipping his hardware in the "bad"
 999          * configuration.
1000          */
1001         if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
1002             !(config & CONF_SC) && c->icache.linesz != 16 &&
1003             PAGE_SIZE <= 0x8000)
1004                 panic("Improper R4000SC processor configuration detected");
1005
1006         /* compute a couple of other cache variables */
1007         c->icache.waysize = icache_size / c->icache.ways;
1008         c->dcache.waysize = dcache_size / c->dcache.ways;
1009
1010         c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
1011         c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
1012
1013         /*
1014          * R10000 and R12000 P-caches are odd in a positive way.  They're 32kB
1015          * 2-way virtually indexed so normally would suffer from aliases.  So
1016          * normally they'd suffer from aliases but magic in the hardware deals
1017          * with that for us so we don't need to take care ourselves.
1018          */
1019         switch (c->cputype) {
1020         case CPU_20KC:
1021         case CPU_25KF:
1022         case CPU_R10000:
1023         case CPU_R12000:
1024         case CPU_SB1:
1025                 break;
1026         case CPU_24K:
1027                 if (!(read_c0_config7() & (1 << 16)))
1028         default:
1029                         if (c->dcache.waysize > PAGE_SIZE)
1030                                 c->dcache.flags |= MIPS_CACHE_ALIASES;
1031         }
1032
1033         switch (c->cputype) {
1034         case CPU_20KC:
1035                 /*
1036                  * Some older 20Kc chips doesn't have the 'VI' bit in
1037                  * the config register.
1038                  */
1039                 c->icache.flags |= MIPS_CACHE_VTAG;
1040                 break;
1041
1042         case CPU_AU1000:
1043         case CPU_AU1500:
1044         case CPU_AU1100:
1045         case CPU_AU1550:
1046         case CPU_AU1200:
1047                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1048                 break;
1049         }
1050
1051         printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1052                icache_size >> 10,
1053                cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
1054                way_string[c->icache.ways], c->icache.linesz);
1055
1056         printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
1057                dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz);
1058 }
1059
1060 /*
1061  * If you even _breathe_ on this function, look at the gcc output and make sure
1062  * it does not pop things on and off the stack for the cache sizing loop that
1063  * executes in KSEG1 space or else you will crash and burn badly.  You have
1064  * been warned.
1065  */
1066 static int __init probe_scache(void)
1067 {
1068         extern unsigned long stext;
1069         unsigned long flags, addr, begin, end, pow2;
1070         unsigned int config = read_c0_config();
1071         struct cpuinfo_mips *c = &current_cpu_data;
1072         int tmp;
1073
1074         if (config & CONF_SC)
1075                 return 0;
1076
1077         begin = (unsigned long) &stext;
1078         begin &= ~((4 * 1024 * 1024) - 1);
1079         end = begin + (4 * 1024 * 1024);
1080
1081         /*
1082          * This is such a bitch, you'd think they would make it easy to do
1083          * this.  Away you daemons of stupidity!
1084          */
1085         local_irq_save(flags);
1086
1087         /* Fill each size-multiple cache line with a valid tag. */
1088         pow2 = (64 * 1024);
1089         for (addr = begin; addr < end; addr = (begin + pow2)) {
1090                 unsigned long *p = (unsigned long *) addr;
1091                 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1092                 pow2 <<= 1;
1093         }
1094
1095         /* Load first line with zero (therefore invalid) tag. */
1096         write_c0_taglo(0);
1097         write_c0_taghi(0);
1098         __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1099         cache_op(Index_Store_Tag_I, begin);
1100         cache_op(Index_Store_Tag_D, begin);
1101         cache_op(Index_Store_Tag_SD, begin);
1102
1103         /* Now search for the wrap around point. */
1104         pow2 = (128 * 1024);
1105         tmp = 0;
1106         for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1107                 cache_op(Index_Load_Tag_SD, addr);
1108                 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1109                 if (!read_c0_taglo())
1110                         break;
1111                 pow2 <<= 1;
1112         }
1113         local_irq_restore(flags);
1114         addr -= begin;
1115
1116         scache_size = addr;
1117         c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1118         c->scache.ways = 1;
1119         c->dcache.waybit = 0;           /* does not matter */
1120
1121         return 1;
1122 }
1123
1124 extern int r5k_sc_init(void);
1125 extern int rm7k_sc_init(void);
1126
1127 static void __init setup_scache(void)
1128 {
1129         struct cpuinfo_mips *c = &current_cpu_data;
1130         unsigned int config = read_c0_config();
1131         int sc_present = 0;
1132
1133         /*
1134          * Do the probing thing on R4000SC and R4400SC processors.  Other
1135          * processors don't have a S-cache that would be relevant to the
1136          * Linux memory managment.
1137          */
1138         switch (c->cputype) {
1139         case CPU_R4000SC:
1140         case CPU_R4000MC:
1141         case CPU_R4400SC:
1142         case CPU_R4400MC:
1143                 sc_present = run_uncached(probe_scache);
1144                 if (sc_present)
1145                         c->options |= MIPS_CPU_CACHE_CDEX_S;
1146                 break;
1147
1148         case CPU_R10000:
1149         case CPU_R12000:
1150                 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1151                 c->scache.linesz = 64 << ((config >> 13) & 1);
1152                 c->scache.ways = 2;
1153                 c->scache.waybit= 0;
1154                 sc_present = 1;
1155                 break;
1156
1157         case CPU_R5000:
1158         case CPU_NEVADA:
1159 #ifdef CONFIG_R5000_CPU_SCACHE
1160                 r5k_sc_init();
1161 #endif
1162                 return;
1163
1164         case CPU_RM7000:
1165         case CPU_RM9000:
1166 #ifdef CONFIG_RM7000_CPU_SCACHE
1167                 rm7k_sc_init();
1168 #endif
1169                 return;
1170
1171         default:
1172                 sc_present = 0;
1173         }
1174
1175         if (!sc_present)
1176                 return;
1177
1178         if ((c->isa_level == MIPS_CPU_ISA_M32 ||
1179              c->isa_level == MIPS_CPU_ISA_M64) &&
1180             !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1181                 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1182
1183         /* compute a couple of other cache variables */
1184         c->scache.waysize = scache_size / c->scache.ways;
1185
1186         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1187
1188         printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1189                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1190
1191         c->options |= MIPS_CPU_SUBSET_CACHES;
1192 }
1193
1194 static inline void coherency_setup(void)
1195 {
1196         change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
1197
1198         /*
1199          * c0_status.cu=0 specifies that updates by the sc instruction use
1200          * the coherency mode specified by the TLB; 1 means cachable
1201          * coherent update on write will be used.  Not all processors have
1202          * this bit and; some wire it to zero, others like Toshiba had the
1203          * silly idea of putting something else there ...
1204          */
1205         switch (current_cpu_data.cputype) {
1206         case CPU_R4000PC:
1207         case CPU_R4000SC:
1208         case CPU_R4000MC:
1209         case CPU_R4400PC:
1210         case CPU_R4400SC:
1211         case CPU_R4400MC:
1212                 clear_c0_config(CONF_CU);
1213                 break;
1214         }
1215 }
1216
1217 void __init ld_mmu_r4xx0(void)
1218 {
1219         extern void build_clear_page(void);
1220         extern void build_copy_page(void);
1221         extern char except_vec2_generic;
1222         struct cpuinfo_mips *c = &current_cpu_data;
1223
1224         /* Default cache error handler for R4000 and R5000 family */
1225         memcpy((void *)(CAC_BASE   + 0x100), &except_vec2_generic, 0x80);
1226         memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_generic, 0x80);
1227
1228         probe_pcache();
1229         setup_scache();
1230
1231         r4k_blast_dcache_page_setup();
1232         r4k_blast_dcache_page_indexed_setup();
1233         r4k_blast_dcache_setup();
1234         r4k_blast_icache_page_setup();
1235         r4k_blast_icache_page_indexed_setup();
1236         r4k_blast_icache_setup();
1237         r4k_blast_scache_page_setup();
1238         r4k_blast_scache_page_indexed_setup();
1239         r4k_blast_scache_setup();
1240
1241         /*
1242          * Some MIPS32 and MIPS64 processors have physically indexed caches.
1243          * This code supports virtually indexed processors and will be
1244          * unnecessarily inefficient on physically indexed processors.
1245          */
1246         shm_align_mask = max_t( unsigned long,
1247                                 c->dcache.sets * c->dcache.linesz - 1,
1248                                 PAGE_SIZE - 1);
1249
1250         flush_cache_all         = r4k_flush_cache_all;
1251         __flush_cache_all       = r4k___flush_cache_all;
1252         flush_cache_mm          = r4k_flush_cache_mm;
1253         flush_cache_page        = r4k_flush_cache_page;
1254         flush_icache_page       = r4k_flush_icache_page;
1255         flush_cache_range       = r4k_flush_cache_range;
1256
1257         flush_cache_sigtramp    = r4k_flush_cache_sigtramp;
1258         flush_icache_all        = r4k_flush_icache_all;
1259         flush_data_cache_page   = r4k_flush_data_cache_page;
1260         flush_icache_range      = r4k_flush_icache_range;
1261
1262 #ifdef CONFIG_DMA_NONCOHERENT
1263         _dma_cache_wback_inv    = r4k_dma_cache_wback_inv;
1264         _dma_cache_wback        = r4k_dma_cache_wback_inv;
1265         _dma_cache_inv          = r4k_dma_cache_inv;
1266 #endif
1267
1268         __flush_cache_all();
1269         coherency_setup();
1270
1271         build_clear_page();
1272         build_copy_page();
1273 }