2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 #include <linux/init.h>
19 #include <linux/sched.h>
20 #include <linux/ioport.h>
21 #include <linux/pci.h>
22 #include <linux/screen_info.h>
25 #include <asm/bootinfo.h>
27 #include <asm/mips-boards/generic.h>
28 #include <asm/mips-boards/prom.h>
29 #include <asm/mips-boards/malta.h>
30 #include <asm/mips-boards/maltaint.h>
33 #include <asm/traps.h>
35 #include <linux/console.h>
39 extern void kgdb_config(void);
42 struct resource standard_io_resources[] = {
47 .flags = IORESOURCE_BUSY
53 .flags = IORESOURCE_BUSY
59 .flags = IORESOURCE_BUSY
62 .name = "dma page reg",
65 .flags = IORESOURCE_BUSY
71 .flags = IORESOURCE_BUSY
75 const char *get_system_type(void)
80 #if defined(CONFIG_MIPS_MT_SMTC)
81 const char display_string[] = " SMTC LINUX ON MALTA ";
83 const char display_string[] = " LINUX ON MALTA ";
84 #endif /* CONFIG_MIPS_MT_SMTC */
86 #ifdef CONFIG_BLK_DEV_FD
87 void __init fd_activate(void)
90 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
92 * Done by YAMON 2.00 onwards
94 /* Entering config state. */
95 SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
97 /* Activate floppy controller. */
98 SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
99 SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
100 SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
101 SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
103 /* Exit config state. */
104 SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
108 #ifdef CONFIG_BLK_DEV_IDE
109 static void __init pci_clock_check(void)
111 unsigned int __iomem *jmpr_p =
112 (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
113 int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
114 static const int pciclocks[] __initdata = {
115 33, 20, 25, 30, 12, 16, 37, 10
117 int pciclock = pciclocks[jmpr];
118 char *argptr = prom_getcmdline();
120 if (pciclock != 33 && !strstr(argptr, "idebus=")) {
121 printk(KERN_WARNING "WARNING: PCI clock is %dMHz, "
122 "setting idebus\n", pciclock);
123 argptr += strlen(argptr);
124 sprintf(argptr, " idebus=%d", pciclock);
125 if (pciclock < 20 || pciclock > 66)
126 printk(KERN_WARNING "WARNING: IDE timing "
127 "calculations will be incorrect\n");
132 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
133 static void __init screen_info_setup(void)
135 screen_info = (struct screen_info) {
139 .orig_video_page = 0,
140 .orig_video_mode = 0,
141 .orig_video_cols = 80,
143 .orig_video_ega_bx = 0,
145 .orig_video_lines = 25,
146 .orig_video_isVGA = VIDEO_TYPE_VGAC,
147 .orig_video_points = 16
152 void __init plat_mem_setup(void)
158 /* Request I/O space for devices used on the Malta board. */
159 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
160 request_resource(&ioport_resource, standard_io_resources+i);
163 * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
171 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
174 argptr = prom_getcmdline();
175 if (strstr(argptr, "debug")) {
176 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
177 printk("Enabled Bonito debug mode\n");
180 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
182 #ifdef CONFIG_DMA_COHERENT
183 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
184 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
185 printk("Enabled Bonito CPU coherency\n");
187 argptr = prom_getcmdline();
188 if (strstr(argptr, "iobcuncached")) {
189 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
190 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
191 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
192 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
193 printk("Disabled Bonito IOBC coherency\n");
196 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
197 BONITO_PCIMEMBASECFG |=
198 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
199 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
200 printk("Enabled Bonito IOBC coherency\n");
204 panic("Hardware DMA cache coherency not supported");
208 #ifdef CONFIG_DMA_COHERENT
210 panic("Hardware DMA cache coherency not supported");
214 #ifdef CONFIG_BLK_DEV_IDE
217 #ifdef CONFIG_BLK_DEV_FD
220 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)