2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki
14 #include <linux/config.h>
15 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/smp.h>
20 #include <linux/smp_lock.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
24 #include <asm/bootinfo.h>
25 #include <asm/branch.h>
26 #include <asm/break.h>
29 #include <asm/module.h>
30 #include <asm/pgtable.h>
31 #include <asm/ptrace.h>
32 #include <asm/sections.h>
33 #include <asm/system.h>
34 #include <asm/tlbdebug.h>
35 #include <asm/traps.h>
36 #include <asm/uaccess.h>
37 #include <asm/mmu_context.h>
38 #include <asm/watch.h>
39 #include <asm/types.h>
41 extern asmlinkage void handle_tlbm(void);
42 extern asmlinkage void handle_tlbl(void);
43 extern asmlinkage void handle_tlbs(void);
44 extern asmlinkage void handle_adel(void);
45 extern asmlinkage void handle_ades(void);
46 extern asmlinkage void handle_ibe(void);
47 extern asmlinkage void handle_dbe(void);
48 extern asmlinkage void handle_sys(void);
49 extern asmlinkage void handle_bp(void);
50 extern asmlinkage void handle_ri(void);
51 extern asmlinkage void handle_cpu(void);
52 extern asmlinkage void handle_ov(void);
53 extern asmlinkage void handle_tr(void);
54 extern asmlinkage void handle_fpe(void);
55 extern asmlinkage void handle_mdmx(void);
56 extern asmlinkage void handle_watch(void);
57 extern asmlinkage void handle_mcheck(void);
58 extern asmlinkage void handle_reserved(void);
60 extern int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
61 struct mips_fpu_soft_struct *ctx);
63 void (*board_be_init)(void);
64 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
67 * These constant is for searching for possible module text segments.
68 * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
70 #define MODULE_RANGE (8*1024*1024)
73 * This routine abuses get_user()/put_user() to reference pointers
74 * with at least a bit of error checking ...
76 void show_stack(struct task_struct *task, unsigned long *sp)
78 const int field = 2 * sizeof(unsigned long);
83 if (task && task != current)
84 sp = (unsigned long *) task->thread.reg29;
86 sp = (unsigned long *) &sp;
91 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
92 if (i && ((i % (64 / field)) == 0))
99 if (__get_user(stackdata, sp++)) {
100 printk(" (Bad stack address)");
104 printk(" %0*lx", field, stackdata);
110 void show_trace(struct task_struct *task, unsigned long *stack)
112 const int field = 2 * sizeof(unsigned long);
116 if (task && task != current)
117 stack = (unsigned long *) task->thread.reg29;
119 stack = (unsigned long *) &stack;
122 printk("Call Trace:");
123 #ifdef CONFIG_KALLSYMS
126 while (!kstack_end(stack)) {
128 if (__kernel_text_address(addr)) {
129 printk(" [<%0*lx>] ", field, addr);
130 print_symbol("%s\n", addr);
137 * The architecture-independent dump_stack generator
139 void dump_stack(void)
143 show_trace(current, &stack);
146 EXPORT_SYMBOL(dump_stack);
148 void show_code(unsigned int *pc)
154 for(i = -3 ; i < 6 ; i++) {
156 if (__get_user(insn, pc + i)) {
157 printk(" (Bad address in epc)\n");
160 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
164 void show_regs(struct pt_regs *regs)
166 const int field = 2 * sizeof(unsigned long);
167 unsigned int cause = regs->cp0_cause;
170 printk("Cpu %d\n", smp_processor_id());
173 * Saved main processor registers
175 for (i = 0; i < 32; ) {
179 printk(" %0*lx", field, 0UL);
180 else if (i == 26 || i == 27)
181 printk(" %*s", field, "");
183 printk(" %0*lx", field, regs->regs[i]);
190 printk("Hi : %0*lx\n", field, regs->hi);
191 printk("Lo : %0*lx\n", field, regs->lo);
194 * Saved cp0 registers
196 printk("epc : %0*lx ", field, regs->cp0_epc);
197 print_symbol("%s ", regs->cp0_epc);
198 printk(" %s\n", print_tainted());
199 printk("ra : %0*lx ", field, regs->regs[31]);
200 print_symbol("%s\n", regs->regs[31]);
202 printk("Status: %08x ", (uint32_t) regs->cp0_status);
204 if (regs->cp0_status & ST0_KX)
206 if (regs->cp0_status & ST0_SX)
208 if (regs->cp0_status & ST0_UX)
210 switch (regs->cp0_status & ST0_KSU) {
215 printk("SUPERVISOR ");
224 if (regs->cp0_status & ST0_ERL)
226 if (regs->cp0_status & ST0_EXL)
228 if (regs->cp0_status & ST0_IE)
232 printk("Cause : %08x\n", cause);
234 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
235 if (1 <= cause && cause <= 5)
236 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
238 printk("PrId : %08x\n", read_c0_prid());
241 void show_registers(struct pt_regs *regs)
245 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
246 current->comm, current->pid, current_thread_info(), current);
247 show_stack(current, (long *) regs->regs[29]);
248 show_trace(current, (long *) regs->regs[29]);
249 show_code((unsigned int *) regs->cp0_epc);
253 static DEFINE_SPINLOCK(die_lock);
255 NORET_TYPE void __die(const char * str, struct pt_regs * regs,
256 const char * file, const char * func, unsigned long line)
258 static int die_counter;
261 spin_lock_irq(&die_lock);
264 printk(" in %s:%s, line %ld", file, func, line);
265 printk("[#%d]:\n", ++die_counter);
266 show_registers(regs);
267 spin_unlock_irq(&die_lock);
271 void __die_if_kernel(const char * str, struct pt_regs * regs,
272 const char * file, const char * func, unsigned long line)
274 if (!user_mode(regs))
275 __die(str, regs, file, func, line);
278 extern const struct exception_table_entry __start___dbe_table[];
279 extern const struct exception_table_entry __stop___dbe_table[];
281 void __declare_dbe_table(void)
283 __asm__ __volatile__(
284 ".section\t__dbe_table,\"a\"\n\t"
289 /* Given an address, look for it in the exception tables. */
290 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
292 const struct exception_table_entry *e;
294 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
296 e = search_module_dbetables(addr);
300 asmlinkage void do_be(struct pt_regs *regs)
302 const int field = 2 * sizeof(unsigned long);
303 const struct exception_table_entry *fixup = NULL;
304 int data = regs->cp0_cause & 4;
305 int action = MIPS_BE_FATAL;
307 /* XXX For now. Fixme, this searches the wrong table ... */
308 if (data && !user_mode(regs))
309 fixup = search_dbe_tables(exception_epc(regs));
312 action = MIPS_BE_FIXUP;
314 if (board_be_handler)
315 action = board_be_handler(regs, fixup != 0);
318 case MIPS_BE_DISCARD:
322 regs->cp0_epc = fixup->nextinsn;
331 * Assume it would be too dangerous to continue ...
333 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
334 data ? "Data" : "Instruction",
335 field, regs->cp0_epc, field, regs->regs[31]);
336 die_if_kernel("Oops", regs);
337 force_sig(SIGBUS, current);
340 static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
342 unsigned int __user *epc;
344 epc = (unsigned int __user *) regs->cp0_epc +
345 ((regs->cp0_cause & CAUSEF_BD) != 0);
346 if (!get_user(*opcode, epc))
349 force_sig(SIGSEGV, current);
357 #define OPCODE 0xfc000000
358 #define BASE 0x03e00000
359 #define RT 0x001f0000
360 #define OFFSET 0x0000ffff
361 #define LL 0xc0000000
362 #define SC 0xe0000000
365 * The ll_bit is cleared by r*_switch.S
368 unsigned long ll_bit;
370 static struct task_struct *ll_task = NULL;
372 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
374 unsigned long value, __user *vaddr;
379 * analyse the ll instruction that just caused a ri exception
380 * and put the referenced address to addr.
383 /* sign extend offset */
384 offset = opcode & OFFSET;
388 vaddr = (unsigned long __user *)
389 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
391 if ((unsigned long)vaddr & 3) {
395 if (get_user(value, vaddr)) {
402 if (ll_task == NULL || ll_task == current) {
411 regs->regs[(opcode & RT) >> 16] = value;
413 compute_return_epc(regs);
417 force_sig(signal, current);
420 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
422 unsigned long __user *vaddr;
428 * analyse the sc instruction that just caused a ri exception
429 * and put the referenced address to addr.
432 /* sign extend offset */
433 offset = opcode & OFFSET;
437 vaddr = (unsigned long __user *)
438 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
439 reg = (opcode & RT) >> 16;
441 if ((unsigned long)vaddr & 3) {
448 if (ll_bit == 0 || ll_task != current) {
451 compute_return_epc(regs);
457 if (put_user(regs->regs[reg], vaddr)) {
464 compute_return_epc(regs);
468 force_sig(signal, current);
472 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
473 * opcodes are supposed to result in coprocessor unusable exceptions if
474 * executed on ll/sc-less processors. That's the theory. In practice a
475 * few processors such as NEC's VR4100 throw reserved instruction exceptions
476 * instead, so we're doing the emulation thing in both exception handlers.
478 static inline int simulate_llsc(struct pt_regs *regs)
482 if (unlikely(get_insn_opcode(regs, &opcode)))
485 if ((opcode & OPCODE) == LL) {
486 simulate_ll(regs, opcode);
489 if ((opcode & OPCODE) == SC) {
490 simulate_sc(regs, opcode);
494 return -EFAULT; /* Strange things going on ... */
497 asmlinkage void do_ov(struct pt_regs *regs)
501 info.si_code = FPE_INTOVF;
502 info.si_signo = SIGFPE;
504 info.si_addr = (void __user *) regs->cp0_epc;
505 force_sig_info(SIGFPE, &info, current);
509 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
511 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
513 if (fcr31 & FPU_CSR_UNI_X) {
519 * Unimplemented operation exception. If we've got the full
520 * software emulator on-board, let's use it...
522 * Force FPU to dump state into task/thread context. We're
523 * moving a lot of data here for what is probably a single
524 * instruction, but the alternative is to pre-decode the FP
525 * register operands before invoking the emulator, which seems
526 * a bit extreme for what should be an infrequent event.
530 /* Run the emulator */
531 sig = fpu_emulator_cop1Handler (0, regs,
532 ¤t->thread.fpu.soft);
535 * We can't allow the emulated instruction to leave any of
536 * the cause bit set in $fcr31.
538 current->thread.fpu.soft.fcr31 &= ~FPU_CSR_ALL_X;
540 /* Restore the hardware register state */
545 /* If something went wrong, signal */
547 force_sig(sig, current);
552 force_sig(SIGFPE, current);
555 asmlinkage void do_bp(struct pt_regs *regs)
557 unsigned int opcode, bcode;
560 die_if_kernel("Break instruction in kernel code", regs);
562 if (get_insn_opcode(regs, &opcode))
566 * There is the ancient bug in the MIPS assemblers that the break
567 * code starts left to bit 16 instead to bit 6 in the opcode.
568 * Gas is bug-compatible, but not always, grrr...
569 * We handle both cases with a simple heuristics. --macro
571 bcode = ((opcode >> 6) & ((1 << 20) - 1));
572 if (bcode < (1 << 10))
576 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
577 * insns, even for break codes that indicate arithmetic failures.
579 * But should we continue the brokenness??? --macro
582 case BRK_OVERFLOW << 10:
583 case BRK_DIVZERO << 10:
584 if (bcode == (BRK_DIVZERO << 10))
585 info.si_code = FPE_INTDIV;
587 info.si_code = FPE_INTOVF;
588 info.si_signo = SIGFPE;
590 info.si_addr = (void __user *) regs->cp0_epc;
591 force_sig_info(SIGFPE, &info, current);
594 force_sig(SIGTRAP, current);
598 asmlinkage void do_tr(struct pt_regs *regs)
600 unsigned int opcode, tcode = 0;
603 die_if_kernel("Trap instruction in kernel code", regs);
605 if (get_insn_opcode(regs, &opcode))
608 /* Immediate versions don't provide a code. */
609 if (!(opcode & OPCODE))
610 tcode = ((opcode >> 6) & ((1 << 10) - 1));
613 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
614 * insns, even for trap codes that indicate arithmetic failures.
616 * But should we continue the brokenness??? --macro
621 if (tcode == BRK_DIVZERO)
622 info.si_code = FPE_INTDIV;
624 info.si_code = FPE_INTOVF;
625 info.si_signo = SIGFPE;
627 info.si_addr = (void __user *) regs->cp0_epc;
628 force_sig_info(SIGFPE, &info, current);
631 force_sig(SIGTRAP, current);
635 asmlinkage void do_ri(struct pt_regs *regs)
637 die_if_kernel("Reserved instruction in kernel code", regs);
640 if (!simulate_llsc(regs))
643 force_sig(SIGILL, current);
646 asmlinkage void do_cpu(struct pt_regs *regs)
650 die_if_kernel("do_cpu invoked from kernel context!", regs);
652 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
659 if (!simulate_llsc(regs))
667 if (used_math()) { /* Using the FPU again. */
669 } else { /* First time FPU user. */
675 int sig = fpu_emulator_cop1Handler(0, regs,
676 ¤t->thread.fpu.soft);
678 force_sig(sig, current);
690 force_sig(SIGILL, current);
693 asmlinkage void do_mdmx(struct pt_regs *regs)
695 force_sig(SIGILL, current);
698 asmlinkage void do_watch(struct pt_regs *regs)
701 * We use the watch exception where available to detect stack
706 panic("Caught WATCH exception - probably caused by stack overflow.");
709 asmlinkage void do_mcheck(struct pt_regs *regs)
714 * Some chips may have other causes of machine check (e.g. SB1
717 panic("Caught Machine Check exception - %scaused by multiple "
718 "matching entries in the TLB.",
719 (regs->cp0_status & ST0_TS) ? "" : "not ");
722 asmlinkage void do_reserved(struct pt_regs *regs)
725 * Game over - no way to handle this if it ever occurs. Most probably
726 * caused by a new unknown cpu type or after another deadly
727 * hard/software error.
730 panic("Caught reserved exception %ld - should not happen.",
731 (regs->cp0_cause & 0x7f) >> 2);
735 * Some MIPS CPUs can enable/disable for cache parity detection, but do
738 static inline void parity_protection_init(void)
740 switch (current_cpu_data.cputype) {
743 write_c0_ecc(0x80000000);
744 back_to_back_c0_hazard();
745 /* Set the PE bit (bit 31) in the c0_errctl register. */
746 printk(KERN_INFO "Cache parity protection %sabled\n",
747 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
751 /* Clear the DE bit (bit 16) in the c0_status register. */
752 printk(KERN_INFO "Enable cache parity protection for "
753 "MIPS 20KC/25KF CPUs.\n");
754 clear_c0_status(ST0_DE);
761 asmlinkage void cache_parity_error(void)
763 const int field = 2 * sizeof(unsigned long);
764 unsigned int reg_val;
766 /* For the moment, report the problem and hang. */
767 printk("Cache error exception:\n");
768 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
769 reg_val = read_c0_cacheerr();
770 printk("c0_cacheerr == %08x\n", reg_val);
772 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
773 reg_val & (1<<30) ? "secondary" : "primary",
774 reg_val & (1<<31) ? "data" : "insn");
775 printk("Error bits: %s%s%s%s%s%s%s\n",
776 reg_val & (1<<29) ? "ED " : "",
777 reg_val & (1<<28) ? "ET " : "",
778 reg_val & (1<<26) ? "EE " : "",
779 reg_val & (1<<25) ? "EB " : "",
780 reg_val & (1<<24) ? "EI " : "",
781 reg_val & (1<<23) ? "E1 " : "",
782 reg_val & (1<<22) ? "E0 " : "");
783 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
785 #if defined(CONFIG_CPU_MIPS32) || defined (CONFIG_CPU_MIPS64)
786 if (reg_val & (1<<22))
787 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
789 if (reg_val & (1<<23))
790 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
793 panic("Can't handle the cache error!");
797 * SDBBP EJTAG debug exception handler.
798 * We skip the instruction and return to the next instruction.
800 void ejtag_exception_handler(struct pt_regs *regs)
802 const int field = 2 * sizeof(unsigned long);
803 unsigned long depc, old_epc;
806 printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
807 depc = read_c0_depc();
808 debug = read_c0_debug();
809 printk("c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
810 if (debug & 0x80000000) {
812 * In branch delay slot.
813 * We cheat a little bit here and use EPC to calculate the
814 * debug return address (DEPC). EPC is restored after the
817 old_epc = regs->cp0_epc;
818 regs->cp0_epc = depc;
819 __compute_return_epc(regs);
820 depc = regs->cp0_epc;
821 regs->cp0_epc = old_epc;
827 printk("\n\n----- Enable EJTAG single stepping ----\n\n");
828 write_c0_debug(debug | 0x100);
833 * NMI exception handler.
835 void nmi_exception_handler(struct pt_regs *regs)
837 printk("NMI taken!!!!\n");
842 unsigned long exception_handlers[32];
845 * As a side effect of the way this is implemented we're limited
846 * to interrupt handlers in the address range from
847 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
849 void *set_except_vector(int n, void *addr)
851 unsigned long handler = (unsigned long) addr;
852 unsigned long old_handler = exception_handlers[n];
854 exception_handlers[n] = handler;
855 if (n == 0 && cpu_has_divec) {
856 *(volatile u32 *)(CAC_BASE + 0x200) = 0x08000000 |
857 (0x03ffffff & (handler >> 2));
858 flush_icache_range(CAC_BASE + 0x200, CAC_BASE + 0x204);
860 return (void *)old_handler;
864 * This is used by native signal handling
866 asmlinkage int (*save_fp_context)(struct sigcontext *sc);
867 asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
869 extern asmlinkage int _save_fp_context(struct sigcontext *sc);
870 extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
872 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
873 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
875 static inline void signal_init(void)
878 save_fp_context = _save_fp_context;
879 restore_fp_context = _restore_fp_context;
881 save_fp_context = fpu_emulator_save_context;
882 restore_fp_context = fpu_emulator_restore_context;
886 #ifdef CONFIG_MIPS32_COMPAT
889 * This is used by 32-bit signal stuff on the 64-bit kernel
891 asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
892 asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
894 extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
895 extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
897 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
898 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
900 static inline void signal32_init(void)
903 save_fp_context32 = _save_fp_context32;
904 restore_fp_context32 = _restore_fp_context32;
906 save_fp_context32 = fpu_emulator_save_context32;
907 restore_fp_context32 = fpu_emulator_restore_context32;
912 extern void cpu_cache_init(void);
913 extern void tlb_init(void);
915 void __init per_cpu_trap_init(void)
917 unsigned int cpu = smp_processor_id();
918 unsigned int status_set = ST0_CU0;
921 * Disable coprocessors and select 32-bit or 64-bit addressing
922 * and the 16/32 or 32/32 FPR register model. Reset the BEV
923 * flag that some firmware may have left set and the TS bit (for
924 * IP27). Set XX for ISA IV code to work.
927 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
929 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
930 status_set |= ST0_XX;
931 change_c0_status(ST0_CU|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
935 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
936 * interrupt processing overhead. Use it where available.
939 set_c0_cause(CAUSEF_IV);
941 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
942 TLBMISS_HANDLER_SETUP();
944 atomic_inc(&init_mm.mm_count);
945 current->active_mm = &init_mm;
947 enter_lazy_tlb(&init_mm, current);
953 void __init trap_init(void)
955 extern char except_vec3_generic, except_vec3_r4000;
956 extern char except_vec_ejtag_debug;
957 extern char except_vec4;
963 * Copy the generic exception handlers to their final destination.
964 * This will be overriden later as suitable for a particular
967 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
970 * Setup default vectors
972 for (i = 0; i <= 31; i++)
973 set_except_vector(i, handle_reserved);
976 * Copy the EJTAG debug exception vector handler code to it's final
980 memcpy((void *)(CAC_BASE + 0x300), &except_vec_ejtag_debug, 0x80);
983 * Only some CPUs have the watch exceptions.
986 set_except_vector(23, handle_watch);
989 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
990 * interrupt processing overhead. Use it where available.
993 memcpy((void *)(CAC_BASE + 0x200), &except_vec4, 0x8);
996 * Some CPUs can enable/disable for cache parity detection, but does
999 parity_protection_init();
1002 * The Data Bus Errors / Instruction Bus Errors are signaled
1003 * by external hardware. Therefore these two exceptions
1004 * may have board specific handlers.
1009 set_except_vector(1, handle_tlbm);
1010 set_except_vector(2, handle_tlbl);
1011 set_except_vector(3, handle_tlbs);
1013 set_except_vector(4, handle_adel);
1014 set_except_vector(5, handle_ades);
1016 set_except_vector(6, handle_ibe);
1017 set_except_vector(7, handle_dbe);
1019 set_except_vector(8, handle_sys);
1020 set_except_vector(9, handle_bp);
1021 set_except_vector(10, handle_ri);
1022 set_except_vector(11, handle_cpu);
1023 set_except_vector(12, handle_ov);
1024 set_except_vector(13, handle_tr);
1025 set_except_vector(22, handle_mdmx);
1027 if (cpu_has_fpu && !cpu_has_nofpuex)
1028 set_except_vector(15, handle_fpe);
1031 set_except_vector(24, handle_mcheck);
1034 /* Special exception: R4[04]00 uses also the divec space. */
1035 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1036 else if (cpu_has_4kex)
1037 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1039 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1041 if (current_cpu_data.cputype == CPU_R6000 ||
1042 current_cpu_data.cputype == CPU_R6000A) {
1044 * The R6000 is the only R-series CPU that features a machine
1045 * check exception (similar to the R4000 cache error) and
1046 * unaligned ldc1/sdc1 exception. The handlers have not been
1047 * written yet. Well, anyway there is no R6000 machine on the
1048 * current list of targets for Linux/MIPS.
1049 * (Duh, crap, there is someone with a triple R6k machine)
1051 //set_except_vector(14, handle_mc);
1052 //set_except_vector(15, handle_ndc);
1056 #ifdef CONFIG_MIPS32_COMPAT
1060 flush_icache_range(CAC_BASE, CAC_BASE + 0x400);