2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
14 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/sched.h>
18 #include <linux/smp.h>
19 #include <linux/smp_lock.h>
20 #include <linux/spinlock.h>
21 #include <linux/kallsyms.h>
22 #include <linux/bootmem.h>
23 #include <linux/interrupt.h>
25 #include <asm/bootinfo.h>
26 #include <asm/branch.h>
27 #include <asm/break.h>
31 #include <asm/mipsregs.h>
32 #include <asm/mipsmtregs.h>
33 #include <asm/module.h>
34 #include <asm/pgtable.h>
35 #include <asm/ptrace.h>
36 #include <asm/sections.h>
37 #include <asm/system.h>
38 #include <asm/tlbdebug.h>
39 #include <asm/traps.h>
40 #include <asm/uaccess.h>
41 #include <asm/mmu_context.h>
42 #include <asm/watch.h>
43 #include <asm/types.h>
45 extern asmlinkage void handle_int(void);
46 extern asmlinkage void handle_tlbm(void);
47 extern asmlinkage void handle_tlbl(void);
48 extern asmlinkage void handle_tlbs(void);
49 extern asmlinkage void handle_adel(void);
50 extern asmlinkage void handle_ades(void);
51 extern asmlinkage void handle_ibe(void);
52 extern asmlinkage void handle_dbe(void);
53 extern asmlinkage void handle_sys(void);
54 extern asmlinkage void handle_bp(void);
55 extern asmlinkage void handle_ri(void);
56 extern asmlinkage void handle_cpu(void);
57 extern asmlinkage void handle_ov(void);
58 extern asmlinkage void handle_tr(void);
59 extern asmlinkage void handle_fpe(void);
60 extern asmlinkage void handle_mdmx(void);
61 extern asmlinkage void handle_watch(void);
62 extern asmlinkage void handle_mt(void);
63 extern asmlinkage void handle_dsp(void);
64 extern asmlinkage void handle_mcheck(void);
65 extern asmlinkage void handle_reserved(void);
67 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
68 struct mips_fpu_struct *ctx);
70 void (*board_be_init)(void);
71 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
72 void (*board_nmi_handler_setup)(void);
73 void (*board_ejtag_handler_setup)(void);
74 void (*board_bind_eic_interrupt)(int irq, int regset);
77 * These constant is for searching for possible module text segments.
78 * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
80 #define MODULE_RANGE (8*1024*1024)
83 * This routine abuses get_user()/put_user() to reference pointers
84 * with at least a bit of error checking ...
86 void show_stack(struct task_struct *task, unsigned long *sp)
88 const int field = 2 * sizeof(unsigned long);
93 if (task && task != current)
94 sp = (unsigned long *) task->thread.reg29;
96 sp = (unsigned long *) &sp;
101 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
102 if (i && ((i % (64 / field)) == 0))
109 if (__get_user(stackdata, sp++)) {
110 printk(" (Bad stack address)");
114 printk(" %0*lx", field, stackdata);
120 void show_trace(struct task_struct *task, unsigned long *stack)
122 const int field = 2 * sizeof(unsigned long);
126 if (task && task != current)
127 stack = (unsigned long *) task->thread.reg29;
129 stack = (unsigned long *) &stack;
132 printk("Call Trace:");
133 #ifdef CONFIG_KALLSYMS
136 while (!kstack_end(stack)) {
138 if (__kernel_text_address(addr)) {
139 printk(" [<%0*lx>] ", field, addr);
140 print_symbol("%s\n", addr);
147 * The architecture-independent dump_stack generator
149 void dump_stack(void)
153 show_trace(current, &stack);
156 EXPORT_SYMBOL(dump_stack);
158 void show_code(unsigned int *pc)
164 for(i = -3 ; i < 6 ; i++) {
166 if (__get_user(insn, pc + i)) {
167 printk(" (Bad address in epc)\n");
170 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
174 void show_regs(struct pt_regs *regs)
176 const int field = 2 * sizeof(unsigned long);
177 unsigned int cause = regs->cp0_cause;
180 printk("Cpu %d\n", smp_processor_id());
183 * Saved main processor registers
185 for (i = 0; i < 32; ) {
189 printk(" %0*lx", field, 0UL);
190 else if (i == 26 || i == 27)
191 printk(" %*s", field, "");
193 printk(" %0*lx", field, regs->regs[i]);
200 printk("Hi : %0*lx\n", field, regs->hi);
201 printk("Lo : %0*lx\n", field, regs->lo);
204 * Saved cp0 registers
206 printk("epc : %0*lx ", field, regs->cp0_epc);
207 print_symbol("%s ", regs->cp0_epc);
208 printk(" %s\n", print_tainted());
209 printk("ra : %0*lx ", field, regs->regs[31]);
210 print_symbol("%s\n", regs->regs[31]);
212 printk("Status: %08x ", (uint32_t) regs->cp0_status);
214 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
215 if (regs->cp0_status & ST0_KUO)
217 if (regs->cp0_status & ST0_IEO)
219 if (regs->cp0_status & ST0_KUP)
221 if (regs->cp0_status & ST0_IEP)
223 if (regs->cp0_status & ST0_KUC)
225 if (regs->cp0_status & ST0_IEC)
228 if (regs->cp0_status & ST0_KX)
230 if (regs->cp0_status & ST0_SX)
232 if (regs->cp0_status & ST0_UX)
234 switch (regs->cp0_status & ST0_KSU) {
239 printk("SUPERVISOR ");
248 if (regs->cp0_status & ST0_ERL)
250 if (regs->cp0_status & ST0_EXL)
252 if (regs->cp0_status & ST0_IE)
257 printk("Cause : %08x\n", cause);
259 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
260 if (1 <= cause && cause <= 5)
261 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
263 printk("PrId : %08x\n", read_c0_prid());
266 void show_registers(struct pt_regs *regs)
270 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
271 current->comm, current->pid, current_thread_info(), current);
272 show_stack(current, (long *) regs->regs[29]);
273 show_trace(current, (long *) regs->regs[29]);
274 show_code((unsigned int *) regs->cp0_epc);
278 static DEFINE_SPINLOCK(die_lock);
280 NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs)
282 static int die_counter;
283 #ifdef CONFIG_MIPS_MT_SMTC
284 unsigned long dvpret = dvpe();
285 #endif /* CONFIG_MIPS_MT_SMTC */
288 spin_lock_irq(&die_lock);
290 #ifdef CONFIG_MIPS_MT_SMTC
291 mips_mt_regdump(dvpret);
292 #endif /* CONFIG_MIPS_MT_SMTC */
293 printk("%s[#%d]:\n", str, ++die_counter);
294 show_registers(regs);
295 spin_unlock_irq(&die_lock);
298 panic("Fatal exception in interrupt");
301 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
303 panic("Fatal exception");
309 extern const struct exception_table_entry __start___dbe_table[];
310 extern const struct exception_table_entry __stop___dbe_table[];
312 void __declare_dbe_table(void)
314 __asm__ __volatile__(
315 ".section\t__dbe_table,\"a\"\n\t"
320 /* Given an address, look for it in the exception tables. */
321 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
323 const struct exception_table_entry *e;
325 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
327 e = search_module_dbetables(addr);
331 asmlinkage void do_be(struct pt_regs *regs)
333 const int field = 2 * sizeof(unsigned long);
334 const struct exception_table_entry *fixup = NULL;
335 int data = regs->cp0_cause & 4;
336 int action = MIPS_BE_FATAL;
338 /* XXX For now. Fixme, this searches the wrong table ... */
339 if (data && !user_mode(regs))
340 fixup = search_dbe_tables(exception_epc(regs));
343 action = MIPS_BE_FIXUP;
345 if (board_be_handler)
346 action = board_be_handler(regs, fixup != 0);
349 case MIPS_BE_DISCARD:
353 regs->cp0_epc = fixup->nextinsn;
362 * Assume it would be too dangerous to continue ...
364 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
365 data ? "Data" : "Instruction",
366 field, regs->cp0_epc, field, regs->regs[31]);
367 die_if_kernel("Oops", regs);
368 force_sig(SIGBUS, current);
371 static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
373 unsigned int __user *epc;
375 epc = (unsigned int __user *) regs->cp0_epc +
376 ((regs->cp0_cause & CAUSEF_BD) != 0);
377 if (!get_user(*opcode, epc))
380 force_sig(SIGSEGV, current);
388 #define OPCODE 0xfc000000
389 #define BASE 0x03e00000
390 #define RT 0x001f0000
391 #define OFFSET 0x0000ffff
392 #define LL 0xc0000000
393 #define SC 0xe0000000
394 #define SPEC3 0x7c000000
395 #define RD 0x0000f800
396 #define FUNC 0x0000003f
397 #define RDHWR 0x0000003b
400 * The ll_bit is cleared by r*_switch.S
403 unsigned long ll_bit;
405 static struct task_struct *ll_task = NULL;
407 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
409 unsigned long value, __user *vaddr;
414 * analyse the ll instruction that just caused a ri exception
415 * and put the referenced address to addr.
418 /* sign extend offset */
419 offset = opcode & OFFSET;
423 vaddr = (unsigned long __user *)
424 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
426 if ((unsigned long)vaddr & 3) {
430 if (get_user(value, vaddr)) {
437 if (ll_task == NULL || ll_task == current) {
446 compute_return_epc(regs);
448 regs->regs[(opcode & RT) >> 16] = value;
453 force_sig(signal, current);
456 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
458 unsigned long __user *vaddr;
464 * analyse the sc instruction that just caused a ri exception
465 * and put the referenced address to addr.
468 /* sign extend offset */
469 offset = opcode & OFFSET;
473 vaddr = (unsigned long __user *)
474 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
475 reg = (opcode & RT) >> 16;
477 if ((unsigned long)vaddr & 3) {
484 if (ll_bit == 0 || ll_task != current) {
485 compute_return_epc(regs);
493 if (put_user(regs->regs[reg], vaddr)) {
498 compute_return_epc(regs);
504 force_sig(signal, current);
508 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
509 * opcodes are supposed to result in coprocessor unusable exceptions if
510 * executed on ll/sc-less processors. That's the theory. In practice a
511 * few processors such as NEC's VR4100 throw reserved instruction exceptions
512 * instead, so we're doing the emulation thing in both exception handlers.
514 static inline int simulate_llsc(struct pt_regs *regs)
518 if (unlikely(get_insn_opcode(regs, &opcode)))
521 if ((opcode & OPCODE) == LL) {
522 simulate_ll(regs, opcode);
525 if ((opcode & OPCODE) == SC) {
526 simulate_sc(regs, opcode);
530 return -EFAULT; /* Strange things going on ... */
534 * Simulate trapping 'rdhwr' instructions to provide user accessible
535 * registers not implemented in hardware. The only current use of this
536 * is the thread area pointer.
538 static inline int simulate_rdhwr(struct pt_regs *regs)
540 struct thread_info *ti = task_thread_info(current);
543 if (unlikely(get_insn_opcode(regs, &opcode)))
546 if (unlikely(compute_return_epc(regs)))
549 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
550 int rd = (opcode & RD) >> 11;
551 int rt = (opcode & RT) >> 16;
554 regs->regs[rt] = ti->tp_value;
565 asmlinkage void do_ov(struct pt_regs *regs)
569 die_if_kernel("Integer overflow", regs);
571 info.si_code = FPE_INTOVF;
572 info.si_signo = SIGFPE;
574 info.si_addr = (void __user *) regs->cp0_epc;
575 force_sig_info(SIGFPE, &info, current);
579 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
581 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
583 die_if_kernel("FP exception in kernel code", regs);
585 if (fcr31 & FPU_CSR_UNI_X) {
590 #ifdef CONFIG_PREEMPT
591 if (!is_fpu_owner()) {
592 /* We might lose fpu before disabling preempt... */
594 BUG_ON(!used_math());
599 * Unimplemented operation exception. If we've got the full
600 * software emulator on-board, let's use it...
602 * Force FPU to dump state into task/thread context. We're
603 * moving a lot of data here for what is probably a single
604 * instruction, but the alternative is to pre-decode the FP
605 * register operands before invoking the emulator, which seems
606 * a bit extreme for what should be an infrequent event.
609 /* Ensure 'resume' not overwrite saved fp context again. */
614 /* Run the emulator */
615 sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu);
619 own_fpu(); /* Using the FPU again. */
621 * We can't allow the emulated instruction to leave any of
622 * the cause bit set in $fcr31.
624 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
626 /* Restore the hardware register state */
631 /* If something went wrong, signal */
633 force_sig(sig, current);
638 force_sig(SIGFPE, current);
641 asmlinkage void do_bp(struct pt_regs *regs)
643 unsigned int opcode, bcode;
646 die_if_kernel("Break instruction in kernel code", regs);
648 if (get_insn_opcode(regs, &opcode))
652 * There is the ancient bug in the MIPS assemblers that the break
653 * code starts left to bit 16 instead to bit 6 in the opcode.
654 * Gas is bug-compatible, but not always, grrr...
655 * We handle both cases with a simple heuristics. --macro
657 bcode = ((opcode >> 6) & ((1 << 20) - 1));
658 if (bcode < (1 << 10))
662 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
663 * insns, even for break codes that indicate arithmetic failures.
665 * But should we continue the brokenness??? --macro
668 case BRK_OVERFLOW << 10:
669 case BRK_DIVZERO << 10:
670 if (bcode == (BRK_DIVZERO << 10))
671 info.si_code = FPE_INTDIV;
673 info.si_code = FPE_INTOVF;
674 info.si_signo = SIGFPE;
676 info.si_addr = (void __user *) regs->cp0_epc;
677 force_sig_info(SIGFPE, &info, current);
680 force_sig(SIGTRAP, current);
684 asmlinkage void do_tr(struct pt_regs *regs)
686 unsigned int opcode, tcode = 0;
689 die_if_kernel("Trap instruction in kernel code", regs);
691 if (get_insn_opcode(regs, &opcode))
694 /* Immediate versions don't provide a code. */
695 if (!(opcode & OPCODE))
696 tcode = ((opcode >> 6) & ((1 << 10) - 1));
699 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
700 * insns, even for trap codes that indicate arithmetic failures.
702 * But should we continue the brokenness??? --macro
707 if (tcode == BRK_DIVZERO)
708 info.si_code = FPE_INTDIV;
710 info.si_code = FPE_INTOVF;
711 info.si_signo = SIGFPE;
713 info.si_addr = (void __user *) regs->cp0_epc;
714 force_sig_info(SIGFPE, &info, current);
717 force_sig(SIGTRAP, current);
721 asmlinkage void do_ri(struct pt_regs *regs)
723 die_if_kernel("Reserved instruction in kernel code", regs);
726 if (!simulate_llsc(regs))
729 if (!simulate_rdhwr(regs))
732 force_sig(SIGILL, current);
735 asmlinkage void do_cpu(struct pt_regs *regs)
739 die_if_kernel("do_cpu invoked from kernel context!", regs);
741 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
746 if (!simulate_llsc(regs))
749 if (!simulate_rdhwr(regs))
758 if (used_math()) { /* Using the FPU again. */
760 } else { /* First time FPU user. */
768 int sig = fpu_emulator_cop1Handler(regs,
769 ¤t->thread.fpu);
771 force_sig(sig, current);
772 #ifdef CONFIG_MIPS_MT_FPAFF
775 * MIPS MT processors may have fewer FPU contexts
776 * than CPU threads. If we've emulated more than
777 * some threshold number of instructions, force
778 * migration to a "CPU" that has FP support.
780 if(mt_fpemul_threshold > 0
781 && ((current->thread.emulated_fp++
782 > mt_fpemul_threshold))) {
784 * If there's no FPU present, or if the
785 * application has already restricted
786 * the allowed set to exclude any CPUs
787 * with FPUs, we'll skip the procedure.
789 if (cpus_intersects(current->cpus_allowed,
794 current->thread.user_cpus_allowed,
796 set_cpus_allowed(current, tmask);
797 current->thread.mflags |= MF_FPUBOUND;
801 #endif /* CONFIG_MIPS_MT_FPAFF */
808 die_if_kernel("do_cpu invoked from kernel context!", regs);
812 force_sig(SIGILL, current);
815 asmlinkage void do_mdmx(struct pt_regs *regs)
817 force_sig(SIGILL, current);
820 asmlinkage void do_watch(struct pt_regs *regs)
823 * We use the watch exception where available to detect stack
828 panic("Caught WATCH exception - probably caused by stack overflow.");
831 asmlinkage void do_mcheck(struct pt_regs *regs)
833 const int field = 2 * sizeof(unsigned long);
834 int multi_match = regs->cp0_status & ST0_TS;
839 printk("Index : %0x\n", read_c0_index());
840 printk("Pagemask: %0x\n", read_c0_pagemask());
841 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
842 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
843 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
848 show_code((unsigned int *) regs->cp0_epc);
851 * Some chips may have other causes of machine check (e.g. SB1
854 panic("Caught Machine Check exception - %scaused by multiple "
855 "matching entries in the TLB.",
856 (multi_match) ? "" : "not ");
859 asmlinkage void do_mt(struct pt_regs *regs)
863 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
864 >> VPECONTROL_EXCPT_SHIFT;
867 printk(KERN_DEBUG "Thread Underflow\n");
870 printk(KERN_DEBUG "Thread Overflow\n");
873 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
876 printk(KERN_DEBUG "Gating Storage Exception\n");
879 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
882 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
885 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
889 die_if_kernel("MIPS MT Thread exception in kernel", regs);
891 force_sig(SIGILL, current);
895 asmlinkage void do_dsp(struct pt_regs *regs)
898 panic("Unexpected DSP exception\n");
900 force_sig(SIGILL, current);
903 asmlinkage void do_reserved(struct pt_regs *regs)
906 * Game over - no way to handle this if it ever occurs. Most probably
907 * caused by a new unknown cpu type or after another deadly
908 * hard/software error.
911 panic("Caught reserved exception %ld - should not happen.",
912 (regs->cp0_cause & 0x7f) >> 2);
915 asmlinkage void do_default_vi(struct pt_regs *regs)
918 panic("Caught unexpected vectored interrupt.");
922 * Some MIPS CPUs can enable/disable for cache parity detection, but do
925 static inline void parity_protection_init(void)
927 switch (current_cpu_data.cputype) {
931 write_c0_ecc(0x80000000);
932 back_to_back_c0_hazard();
933 /* Set the PE bit (bit 31) in the c0_errctl register. */
934 printk(KERN_INFO "Cache parity protection %sabled\n",
935 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
939 /* Clear the DE bit (bit 16) in the c0_status register. */
940 printk(KERN_INFO "Enable cache parity protection for "
941 "MIPS 20KC/25KF CPUs.\n");
942 clear_c0_status(ST0_DE);
949 asmlinkage void cache_parity_error(void)
951 const int field = 2 * sizeof(unsigned long);
952 unsigned int reg_val;
954 /* For the moment, report the problem and hang. */
955 printk("Cache error exception:\n");
956 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
957 reg_val = read_c0_cacheerr();
958 printk("c0_cacheerr == %08x\n", reg_val);
960 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
961 reg_val & (1<<30) ? "secondary" : "primary",
962 reg_val & (1<<31) ? "data" : "insn");
963 printk("Error bits: %s%s%s%s%s%s%s\n",
964 reg_val & (1<<29) ? "ED " : "",
965 reg_val & (1<<28) ? "ET " : "",
966 reg_val & (1<<26) ? "EE " : "",
967 reg_val & (1<<25) ? "EB " : "",
968 reg_val & (1<<24) ? "EI " : "",
969 reg_val & (1<<23) ? "E1 " : "",
970 reg_val & (1<<22) ? "E0 " : "");
971 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
973 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
974 if (reg_val & (1<<22))
975 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
977 if (reg_val & (1<<23))
978 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
981 panic("Can't handle the cache error!");
985 * SDBBP EJTAG debug exception handler.
986 * We skip the instruction and return to the next instruction.
988 void ejtag_exception_handler(struct pt_regs *regs)
990 const int field = 2 * sizeof(unsigned long);
991 unsigned long depc, old_epc;
994 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
995 depc = read_c0_depc();
996 debug = read_c0_debug();
997 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
998 if (debug & 0x80000000) {
1000 * In branch delay slot.
1001 * We cheat a little bit here and use EPC to calculate the
1002 * debug return address (DEPC). EPC is restored after the
1005 old_epc = regs->cp0_epc;
1006 regs->cp0_epc = depc;
1007 __compute_return_epc(regs);
1008 depc = regs->cp0_epc;
1009 regs->cp0_epc = old_epc;
1012 write_c0_depc(depc);
1015 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1016 write_c0_debug(debug | 0x100);
1021 * NMI exception handler.
1023 void nmi_exception_handler(struct pt_regs *regs)
1025 #ifdef CONFIG_MIPS_MT_SMTC
1026 unsigned long dvpret = dvpe();
1028 printk("NMI taken!!!!\n");
1029 mips_mt_regdump(dvpret);
1032 printk("NMI taken!!!!\n");
1033 #endif /* CONFIG_MIPS_MT_SMTC */
1038 #define VECTORSPACING 0x100 /* for EI/VI mode */
1040 unsigned long ebase;
1041 unsigned long exception_handlers[32];
1042 unsigned long vi_handlers[64];
1045 * As a side effect of the way this is implemented we're limited
1046 * to interrupt handlers in the address range from
1047 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
1049 void *set_except_vector(int n, void *addr)
1051 unsigned long handler = (unsigned long) addr;
1052 unsigned long old_handler = exception_handlers[n];
1054 exception_handlers[n] = handler;
1055 if (n == 0 && cpu_has_divec) {
1056 *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
1057 (0x03ffffff & (handler >> 2));
1058 flush_icache_range(ebase + 0x200, ebase + 0x204);
1060 return (void *)old_handler;
1063 #ifdef CONFIG_CPU_MIPSR2_SRS
1065 * MIPSR2 shadow register set allocation
1069 static struct shadow_registers {
1071 * Number of shadow register sets supported
1073 unsigned long sr_supported;
1075 * Bitmap of allocated shadow registers
1077 unsigned long sr_allocated;
1080 static void mips_srs_init(void)
1082 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1083 printk(KERN_INFO "%d MIPSR2 register sets available\n",
1084 shadow_registers.sr_supported);
1085 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
1088 int mips_srs_max(void)
1090 return shadow_registers.sr_supported;
1093 int mips_srs_alloc(void)
1095 struct shadow_registers *sr = &shadow_registers;
1099 set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
1100 if (set >= sr->sr_supported)
1103 if (test_and_set_bit(set, &sr->sr_allocated))
1109 void mips_srs_free(int set)
1111 struct shadow_registers *sr = &shadow_registers;
1113 clear_bit(set, &sr->sr_allocated);
1116 static void *set_vi_srs_handler(int n, void *addr, int srs)
1118 unsigned long handler;
1119 unsigned long old_handler = vi_handlers[n];
1123 if (!cpu_has_veic && !cpu_has_vint)
1127 handler = (unsigned long) do_default_vi;
1130 handler = (unsigned long) addr;
1131 vi_handlers[n] = (unsigned long) addr;
1133 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1135 if (srs >= mips_srs_max())
1136 panic("Shadow register set %d not supported", srs);
1139 if (board_bind_eic_interrupt)
1140 board_bind_eic_interrupt (n, srs);
1141 } else if (cpu_has_vint) {
1142 /* SRSMap is only defined if shadow sets are implemented */
1143 if (mips_srs_max() > 1)
1144 change_c0_srsmap (0xf << n*4, srs << n*4);
1149 * If no shadow set is selected then use the default handler
1150 * that does normal register saving and a standard interrupt exit
1153 extern char except_vec_vi, except_vec_vi_lui;
1154 extern char except_vec_vi_ori, except_vec_vi_end;
1155 #ifdef CONFIG_MIPS_MT_SMTC
1157 * We need to provide the SMTC vectored interrupt handler
1158 * not only with the address of the handler, but with the
1159 * Status.IM bit to be masked before going there.
1161 extern char except_vec_vi_mori;
1162 const int mori_offset = &except_vec_vi_mori - &except_vec_vi;
1163 #endif /* CONFIG_MIPS_MT_SMTC */
1164 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1165 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1166 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1168 if (handler_len > VECTORSPACING) {
1170 * Sigh... panicing won't help as the console
1171 * is probably not configured :(
1173 panic ("VECTORSPACING too small");
1176 memcpy (b, &except_vec_vi, handler_len);
1177 #ifdef CONFIG_MIPS_MT_SMTC
1179 printk("Vector index %d exceeds SMTC maximum\n", n);
1180 w = (u32 *)(b + mori_offset);
1181 *w = (*w & 0xffff0000) | (0x100 << n);
1182 #endif /* CONFIG_MIPS_MT_SMTC */
1183 w = (u32 *)(b + lui_offset);
1184 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1185 w = (u32 *)(b + ori_offset);
1186 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1187 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1191 * In other cases jump directly to the interrupt handler
1193 * It is the handlers responsibility to save registers if required
1194 * (eg hi/lo) and return from the exception using "eret"
1197 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1199 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1202 return (void *)old_handler;
1205 void *set_vi_handler(int n, void *addr)
1207 return set_vi_srs_handler(n, addr, 0);
1212 static inline void mips_srs_init(void)
1216 #endif /* CONFIG_CPU_MIPSR2_SRS */
1219 * This is used by native signal handling
1221 asmlinkage int (*save_fp_context)(struct sigcontext *sc);
1222 asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
1224 extern asmlinkage int _save_fp_context(struct sigcontext *sc);
1225 extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
1227 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
1228 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
1231 static int smp_save_fp_context(struct sigcontext *sc)
1234 ? _save_fp_context(sc)
1235 : fpu_emulator_save_context(sc);
1238 static int smp_restore_fp_context(struct sigcontext *sc)
1241 ? _restore_fp_context(sc)
1242 : fpu_emulator_restore_context(sc);
1246 static inline void signal_init(void)
1249 /* For now just do the cpu_has_fpu check when the functions are invoked */
1250 save_fp_context = smp_save_fp_context;
1251 restore_fp_context = smp_restore_fp_context;
1254 save_fp_context = _save_fp_context;
1255 restore_fp_context = _restore_fp_context;
1257 save_fp_context = fpu_emulator_save_context;
1258 restore_fp_context = fpu_emulator_restore_context;
1263 #ifdef CONFIG_MIPS32_COMPAT
1266 * This is used by 32-bit signal stuff on the 64-bit kernel
1268 asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
1269 asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
1271 extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
1272 extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
1274 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
1275 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
1277 static inline void signal32_init(void)
1280 save_fp_context32 = _save_fp_context32;
1281 restore_fp_context32 = _restore_fp_context32;
1283 save_fp_context32 = fpu_emulator_save_context32;
1284 restore_fp_context32 = fpu_emulator_restore_context32;
1289 extern void cpu_cache_init(void);
1290 extern void tlb_init(void);
1291 extern void flush_tlb_handlers(void);
1293 void __init per_cpu_trap_init(void)
1295 unsigned int cpu = smp_processor_id();
1296 unsigned int status_set = ST0_CU0;
1297 #ifdef CONFIG_MIPS_MT_SMTC
1298 int secondaryTC = 0;
1299 int bootTC = (cpu == 0);
1302 * Only do per_cpu_trap_init() for first TC of Each VPE.
1303 * Note that this hack assumes that the SMTC init code
1304 * assigns TCs consecutively and in ascending order.
1307 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1308 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1310 #endif /* CONFIG_MIPS_MT_SMTC */
1313 * Disable coprocessors and select 32-bit or 64-bit addressing
1314 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1315 * flag that some firmware may have left set and the TS bit (for
1316 * IP27). Set XX for ISA IV code to work.
1319 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1321 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1322 status_set |= ST0_XX;
1323 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1327 set_c0_status(ST0_MX);
1329 #ifdef CONFIG_CPU_MIPSR2
1330 write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
1333 #ifdef CONFIG_MIPS_MT_SMTC
1335 #endif /* CONFIG_MIPS_MT_SMTC */
1338 * Interrupt handling.
1340 if (cpu_has_veic || cpu_has_vint) {
1341 write_c0_ebase (ebase);
1342 /* Setting vector spacing enables EI/VI mode */
1343 change_c0_intctl (0x3e0, VECTORSPACING);
1345 if (cpu_has_divec) {
1346 if (cpu_has_mipsmt) {
1347 unsigned int vpflags = dvpe();
1348 set_c0_cause(CAUSEF_IV);
1351 set_c0_cause(CAUSEF_IV);
1353 #ifdef CONFIG_MIPS_MT_SMTC
1355 #endif /* CONFIG_MIPS_MT_SMTC */
1357 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1358 TLBMISS_HANDLER_SETUP();
1360 atomic_inc(&init_mm.mm_count);
1361 current->active_mm = &init_mm;
1362 BUG_ON(current->mm);
1363 enter_lazy_tlb(&init_mm, current);
1365 #ifdef CONFIG_MIPS_MT_SMTC
1367 #endif /* CONFIG_MIPS_MT_SMTC */
1370 #ifdef CONFIG_MIPS_MT_SMTC
1372 #endif /* CONFIG_MIPS_MT_SMTC */
1375 /* Install CPU exception handler */
1376 void __init set_handler (unsigned long offset, void *addr, unsigned long size)
1378 memcpy((void *)(ebase + offset), addr, size);
1379 flush_icache_range(ebase + offset, ebase + offset + size);
1382 /* Install uncached CPU exception handler */
1383 void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
1386 unsigned long uncached_ebase = KSEG1ADDR(ebase);
1389 unsigned long uncached_ebase = TO_UNCAC(ebase);
1392 memcpy((void *)(uncached_ebase + offset), addr, size);
1395 void __init trap_init(void)
1397 extern char except_vec3_generic, except_vec3_r4000;
1398 extern char except_vec4;
1401 if (cpu_has_veic || cpu_has_vint)
1402 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
1408 per_cpu_trap_init();
1411 * Copy the generic exception handlers to their final destination.
1412 * This will be overriden later as suitable for a particular
1415 set_handler(0x180, &except_vec3_generic, 0x80);
1418 * Setup default vectors
1420 for (i = 0; i <= 31; i++)
1421 set_except_vector(i, handle_reserved);
1424 * Copy the EJTAG debug exception vector handler code to it's final
1427 if (cpu_has_ejtag && board_ejtag_handler_setup)
1428 board_ejtag_handler_setup ();
1431 * Only some CPUs have the watch exceptions.
1434 set_except_vector(23, handle_watch);
1437 * Initialise interrupt handlers
1439 if (cpu_has_veic || cpu_has_vint) {
1440 int nvec = cpu_has_veic ? 64 : 8;
1441 for (i = 0; i < nvec; i++)
1442 set_vi_handler(i, NULL);
1444 else if (cpu_has_divec)
1445 set_handler(0x200, &except_vec4, 0x8);
1448 * Some CPUs can enable/disable for cache parity detection, but does
1449 * it different ways.
1451 parity_protection_init();
1454 * The Data Bus Errors / Instruction Bus Errors are signaled
1455 * by external hardware. Therefore these two exceptions
1456 * may have board specific handlers.
1461 set_except_vector(0, handle_int);
1462 set_except_vector(1, handle_tlbm);
1463 set_except_vector(2, handle_tlbl);
1464 set_except_vector(3, handle_tlbs);
1466 set_except_vector(4, handle_adel);
1467 set_except_vector(5, handle_ades);
1469 set_except_vector(6, handle_ibe);
1470 set_except_vector(7, handle_dbe);
1472 set_except_vector(8, handle_sys);
1473 set_except_vector(9, handle_bp);
1474 set_except_vector(10, handle_ri);
1475 set_except_vector(11, handle_cpu);
1476 set_except_vector(12, handle_ov);
1477 set_except_vector(13, handle_tr);
1479 if (current_cpu_data.cputype == CPU_R6000 ||
1480 current_cpu_data.cputype == CPU_R6000A) {
1482 * The R6000 is the only R-series CPU that features a machine
1483 * check exception (similar to the R4000 cache error) and
1484 * unaligned ldc1/sdc1 exception. The handlers have not been
1485 * written yet. Well, anyway there is no R6000 machine on the
1486 * current list of targets for Linux/MIPS.
1487 * (Duh, crap, there is someone with a triple R6k machine)
1489 //set_except_vector(14, handle_mc);
1490 //set_except_vector(15, handle_ndc);
1494 if (board_nmi_handler_setup)
1495 board_nmi_handler_setup();
1497 if (cpu_has_fpu && !cpu_has_nofpuex)
1498 set_except_vector(15, handle_fpe);
1500 set_except_vector(22, handle_mdmx);
1503 set_except_vector(24, handle_mcheck);
1506 set_except_vector(25, handle_mt);
1509 set_except_vector(26, handle_dsp);
1512 /* Special exception: R4[04]00 uses also the divec space. */
1513 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1514 else if (cpu_has_4kex)
1515 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1517 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1520 #ifdef CONFIG_MIPS32_COMPAT
1524 flush_icache_range(ebase, ebase + 0x400);
1525 flush_tlb_handlers();