2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 * Copyright (c) 2003, 2004 Maciej W. Rozycki
6 * Common time service routines for MIPS machines. See
7 * Documentation/mips/time.README.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 #include <linux/clockchips.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/sched.h>
19 #include <linux/param.h>
20 #include <linux/profile.h>
21 #include <linux/time.h>
22 #include <linux/timex.h>
23 #include <linux/smp.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/spinlock.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
29 #include <asm/bootinfo.h>
30 #include <asm/cache.h>
31 #include <asm/compiler.h>
33 #include <asm/cpu-features.h>
34 #include <asm/div64.h>
35 #include <asm/sections.h>
41 * The integer part of the number of usecs per jiffy is taken from tick,
42 * but the fractional part is not recorded, so we calculate it using the
43 * initial value of HZ. This aids systems where tick isn't really an
44 * integer (e.g. for HZ = 128).
46 #define USECS_PER_JIFFY TICK_SIZE
47 #define USECS_PER_JIFFY_FRAC ((unsigned long)(u32)((1000000ULL << 32) / HZ))
49 #define TICK_SIZE (tick_nsec / 1000)
54 DEFINE_SPINLOCK(rtc_lock);
55 EXPORT_SYMBOL(rtc_lock);
57 int __weak rtc_mips_set_time(unsigned long sec)
61 EXPORT_SYMBOL(rtc_mips_set_time);
63 int __weak rtc_mips_set_mmss(unsigned long nowtime)
65 return rtc_mips_set_time(nowtime);
68 int update_persistent_clock(struct timespec now)
70 return rtc_mips_set_mmss(now.tv_sec);
73 /* how many counter cycles in a jiffy */
74 static unsigned long cycles_per_jiffy __read_mostly;
77 * Null timer ack for systems not needing one (e.g. i8254).
79 static void null_timer_ack(void) { /* nothing */ }
82 * Null high precision timer functions for systems lacking one.
84 static cycle_t null_hpt_read(void)
90 * Timer ack for an R4k-compatible timer of a known frequency.
92 static void c0_timer_ack(void)
94 write_c0_compare(read_c0_compare());
98 * High precision timer functions for a R4k-compatible timer.
100 static cycle_t c0_hpt_read(void)
102 return read_c0_count();
105 int (*mips_timer_state)(void);
106 void (*mips_timer_ack)(void);
109 * local_timer_interrupt() does profiling and process accounting
110 * on a per-CPU basis.
112 * In UP mode, it is invoked from the (global) timer_interrupt.
114 * In SMP mode, it might invoked by per-CPU timer interrupt, or
115 * a broadcasted inter-processor interrupt which itself is triggered
116 * by the global timer interrupt.
118 void local_timer_interrupt(int irq, void *dev_id)
120 profile_tick(CPU_PROFILING);
121 update_process_times(user_mode(get_irq_regs()));
124 int null_perf_irq(void)
129 EXPORT_SYMBOL(null_perf_irq);
131 int (*perf_irq)(void) = null_perf_irq;
133 EXPORT_SYMBOL(perf_irq);
141 * Performance counter IRQ or -1 if shared with timer
143 int cp0_perfcount_irq;
144 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
147 * Possibly handle a performance counter interrupt.
148 * Return true if the timer interrupt should not be checked
150 static inline int handle_perf_irq (int r2)
153 * The performance counter overflow interrupt may be shared with the
154 * timer interrupt (cp0_perfcount_irq < 0). If it is and a
155 * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
156 * and we can't reliably determine if a counter interrupt has also
157 * happened (!r2) then don't check for a timer interrupt.
159 return (cp0_perfcount_irq < 0) &&
160 perf_irq() == IRQ_HANDLED &&
165 * time_init() - it does the following things.
167 * 1) plat_time_init() -
168 * a) (optional) set up RTC routines,
169 * b) (optional) calibrate and set the mips_hpt_frequency
170 * (only needed if you intended to use cpu counter as timer interrupt
172 * 2) calculate a couple of cached variables for later usage
173 * 3) plat_timer_setup() -
174 * a) (optional) over-write any choices made above by time_init().
175 * b) machine specific code should setup the timer irqaction.
176 * c) enable the timer interrupt
179 unsigned int mips_hpt_frequency;
181 static unsigned int __init calibrate_hpt(void)
183 cycle_t frequency, hpt_start, hpt_end, hpt_count, hz;
185 const int loops = HZ / 10;
190 * We want to calibrate for 0.1s, but to avoid a 64-bit
191 * division we round the number of loops up to the nearest
194 while (loops > 1 << log_2_loops)
196 i = 1 << log_2_loops;
199 * Wait for a rising edge of the timer interrupt.
201 while (mips_timer_state());
202 while (!mips_timer_state());
205 * Now see how many high precision timer ticks happen
206 * during the calculated number of periods between timer
209 hpt_start = clocksource_mips.read();
211 while (mips_timer_state());
212 while (!mips_timer_state());
214 hpt_end = clocksource_mips.read();
216 hpt_count = (hpt_end - hpt_start) & clocksource_mips.mask;
218 frequency = hpt_count * hz;
220 return frequency >> log_2_loops;
223 struct clocksource clocksource_mips = {
225 .mask = CLOCKSOURCE_MASK(32),
226 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
229 static int mips_next_event(unsigned long delta,
230 struct clock_event_device *evt)
234 cnt = read_c0_count();
236 write_c0_compare(cnt);
238 return ((long)(read_c0_count() - cnt ) > 0) ? -ETIME : 0;
241 static void mips_set_mode(enum clock_event_mode mode,
242 struct clock_event_device *evt)
244 /* Nothing to do ... */
247 struct clock_event_device mips_clockevent;
249 static struct clock_event_device *global_cd[NR_CPUS];
250 static int cp0_timer_irq_installed;
252 static irqreturn_t timer_interrupt(int irq, void *dev_id)
254 const int r2 = cpu_has_mips_r2;
255 struct clock_event_device *cd;
256 int cpu = smp_processor_id();
260 * Before R2 of the architecture there was no way to see if a
261 * performance counter interrupt was pending, so we have to run
262 * the performance counter interrupt handler anyway.
264 if (handle_perf_irq(r2))
268 * The same applies to performance counter interrupts. But with the
269 * above we now know that the reason we got here must be a timer
270 * interrupt. Being the paranoiacs we are we check anyway.
272 if (!r2 || (read_c0_cause() & (1 << 30))) {
275 cd->event_handler(cd);
282 static struct irqaction timer_irqaction = {
283 .handler = timer_interrupt,
284 .flags = IRQF_DISABLED | IRQF_PERCPU,
288 static void __init init_mips_clocksource(void)
293 if (!mips_hpt_frequency || clocksource_mips.read == null_hpt_read)
296 /* Calclate a somewhat reasonable rating value */
297 clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
298 /* Find a shift value */
299 for (shift = 32; shift > 0; shift--) {
300 temp = (u64) NSEC_PER_SEC << shift;
301 do_div(temp, mips_hpt_frequency);
302 if ((temp >> 32) == 0)
305 clocksource_mips.shift = shift;
306 clocksource_mips.mult = (u32)temp;
308 clocksource_register(&clocksource_mips);
311 void __init __weak plat_time_init(void)
315 void __init __weak plat_timer_setup(struct irqaction *irq)
319 void __cpuinit mips_clockevent_init(void)
321 uint64_t mips_freq = mips_hpt_frequency;
322 unsigned int cpu = smp_processor_id();
323 struct clock_event_device *cd;
324 unsigned int irq = MIPS_CPU_IRQ_BASE + 7;
326 if (!cpu_has_counter)
330 cd = &mips_clockevent;
332 cd = kzalloc(sizeof(*cd), GFP_ATOMIC);
334 return; /* We're probably roadkill ... */
337 cd->features = CLOCK_EVT_FEAT_ONESHOT;
339 /* Calculate the min / max delta */
340 cd->mult = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
342 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
343 cd->min_delta_ns = clockevent_delta2ns(0x30, cd);
347 cd->cpumask = cpumask_of_cpu(cpu);
348 cd->set_next_event = mips_next_event;
349 cd->set_mode = mips_set_mode;
352 clockevents_register_device(cd);
354 if (!cp0_timer_irq_installed) {
355 #ifdef CONFIG_MIPS_MT_SMTC
356 #define CPUCTR_IMASKBIT (0x100 << cp0_compare_irq)
357 setup_irq_smtc(irq, &timer_irqaction, CPUCTR_IMASKBIT);
359 setup_irq(irq, &timer_irqaction);
360 #endif /* CONFIG_MIPS_MT_SMTC */
361 cp0_timer_irq_installed = 1;
365 void __init time_init(void)
369 /* Choose appropriate high precision timer routines. */
370 if (!cpu_has_counter && !clocksource_mips.read)
371 /* No high precision timer -- sorry. */
372 clocksource_mips.read = null_hpt_read;
373 else if (!mips_hpt_frequency && !mips_timer_state) {
374 /* A high precision timer of unknown frequency. */
375 if (!clocksource_mips.read)
376 /* No external high precision timer -- use R4k. */
377 clocksource_mips.read = c0_hpt_read;
379 /* We know counter frequency. Or we can get it. */
380 if (!clocksource_mips.read) {
381 /* No external high precision timer -- use R4k. */
382 clocksource_mips.read = c0_hpt_read;
384 if (!mips_timer_state) {
385 /* No external timer interrupt -- use R4k. */
386 mips_timer_ack = c0_timer_ack;
387 /* Calculate cache parameters. */
389 (mips_hpt_frequency + HZ / 2) / HZ;
392 if (!mips_hpt_frequency)
393 mips_hpt_frequency = calibrate_hpt();
395 /* Report the high precision timer rate for a reference. */
396 printk("Using %u.%03u MHz high precision timer.\n",
397 ((mips_hpt_frequency + 500) / 1000) / 1000,
398 ((mips_hpt_frequency + 500) / 1000) % 1000);
400 #ifdef CONFIG_IRQ_CPU
401 setup_irq(MIPS_CPU_IRQ_BASE + 7, &timer_irqaction);
406 /* No timer interrupt ack (e.g. i8254). */
407 mips_timer_ack = null_timer_ack;
410 * Call board specific timer interrupt setup.
412 * this pointer must be setup in machine setup routine.
414 * Even if a machine chooses to use a low-level timer interrupt,
415 * it still needs to setup the timer_irqaction.
416 * In that case, it might be better to set timer_irqaction.handler
417 * to be NULL function so that we are sure the high-level code
418 * is not invoked accidentally.
420 plat_timer_setup(&timer_irqaction);
422 init_mips_clocksource();
423 mips_clockevent_init();