1 /* Copyright (C) 2004 Mips Technologies, Inc */
3 #include <linux/kernel.h>
4 #include <linux/sched.h>
5 #include <linux/cpumask.h>
6 #include <linux/interrupt.h>
7 #include <linux/kernel_stat.h>
8 #include <linux/module.h>
11 #include <asm/processor.h>
12 #include <asm/atomic.h>
13 #include <asm/system.h>
14 #include <asm/hardirq.h>
15 #include <asm/hazards.h>
16 #include <asm/mmu_context.h>
18 #include <asm/mips-boards/maltaint.h>
19 #include <asm/mipsregs.h>
20 #include <asm/cacheflush.h>
22 #include <asm/addrspace.h>
24 #include <asm/smtc_ipi.h>
25 #include <asm/smtc_proc.h>
28 * This file should be built into the kernel only if CONFIG_MIPS_MT_SMTC is set.
31 #define MIPS_CPU_IPI_IRQ 1
33 #define LOCK_MT_PRA() \
34 local_irq_save(flags); \
37 #define UNLOCK_MT_PRA() \
39 local_irq_restore(flags)
41 #define LOCK_CORE_PRA() \
42 local_irq_save(flags); \
45 #define UNLOCK_CORE_PRA() \
47 local_irq_restore(flags)
50 * Data structures purely associated with SMTC parallelism
55 * Table for tracking ASIDs whose lifetime is prolonged.
58 asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
61 * Clock interrupt "latch" buffers, per "CPU"
64 unsigned int ipi_timer_latch[NR_CPUS];
67 * Number of InterProcessor Interupt (IPI) message buffers to allocate
70 #define IPIBUF_PER_CPU 4
72 static struct smtc_ipi_q IPIQ[NR_CPUS];
73 static struct smtc_ipi_q freeIPIq;
76 /* Forward declarations */
78 void ipi_decode(struct smtc_ipi *);
79 static void post_direct_ipi(int cpu, struct smtc_ipi *pipi);
80 static void setup_cross_vpe_interrupts(void);
81 void init_smtc_stats(void);
83 /* Global SMTC Status */
85 unsigned int smtc_status = 0;
87 /* Boot command line configuration overrides */
89 static int vpelimit = 0;
90 static int tclimit = 0;
91 static int ipibuffers = 0;
92 static int nostlb = 0;
93 static int asidmask = 0;
94 unsigned long smtc_asid_mask = 0xff;
96 static int __init maxvpes(char *str)
98 get_option(&str, &vpelimit);
102 static int __init maxtcs(char *str)
104 get_option(&str, &tclimit);
108 static int __init ipibufs(char *str)
110 get_option(&str, &ipibuffers);
114 static int __init stlb_disable(char *s)
120 static int __init asidmask_set(char *str)
122 get_option(&str, &asidmask);
132 smtc_asid_mask = (unsigned long)asidmask;
135 printk("ILLEGAL ASID mask 0x%x from command line\n", asidmask);
140 __setup("maxvpes=", maxvpes);
141 __setup("maxtcs=", maxtcs);
142 __setup("ipibufs=", ipibufs);
143 __setup("nostlb", stlb_disable);
144 __setup("asidmask=", asidmask_set);
146 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
148 static int hang_trig = 0;
150 static int __init hangtrig_enable(char *s)
157 __setup("hangtrig", hangtrig_enable);
159 #define DEFAULT_BLOCKED_IPI_LIMIT 32
161 static int timerq_limit = DEFAULT_BLOCKED_IPI_LIMIT;
163 static int __init tintq(char *str)
165 get_option(&str, &timerq_limit);
169 __setup("tintq=", tintq);
171 int imstuckcount[2][8];
172 /* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */
173 int vpemask[2][8] = {{0,1,1,0,0,0,0,1},{0,1,0,0,0,0,0,1}};
174 int tcnoprog[NR_CPUS];
175 static atomic_t idle_hook_initialized = {0};
176 static int clock_hang_reported[NR_CPUS];
178 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
180 /* Initialize shared TLB - the should probably migrate to smtc_setup_cpus() */
182 void __init sanitize_tlb_entries(void)
184 printk("Deprecated sanitize_tlb_entries() invoked\n");
189 * Configure shared TLB - VPC configuration bit must be set by caller
192 static void smtc_configure_tlb(void)
195 unsigned long mvpconf0;
196 unsigned long config1val;
198 /* Set up ASID preservation table */
199 for (vpes=0; vpes<MAX_SMTC_TLBS; vpes++) {
200 for(i = 0; i < MAX_SMTC_ASIDS; i++) {
201 smtc_live_asid[vpes][i] = 0;
204 mvpconf0 = read_c0_mvpconf0();
206 if ((vpes = ((mvpconf0 & MVPCONF0_PVPE)
207 >> MVPCONF0_PVPE_SHIFT) + 1) > 1) {
208 /* If we have multiple VPEs, try to share the TLB */
209 if ((mvpconf0 & MVPCONF0_TLBS) && !nostlb) {
211 * If TLB sizing is programmable, shared TLB
212 * size is the total available complement.
213 * Otherwise, we have to take the sum of all
214 * static VPE TLB entries.
216 if ((tlbsiz = ((mvpconf0 & MVPCONF0_PTLBE)
217 >> MVPCONF0_PTLBE_SHIFT)) == 0) {
219 * If there's more than one VPE, there had better
220 * be more than one TC, because we need one to bind
221 * to each VPE in turn to be able to read
222 * its configuration state!
225 /* Stop the TC from doing anything foolish */
226 write_tc_c0_tchalt(TCHALT_H);
228 /* No need to un-Halt - that happens later anyway */
229 for (i=0; i < vpes; i++) {
230 write_tc_c0_tcbind(i);
232 * To be 100% sure we're really getting the right
233 * information, we exit the configuration state
234 * and do an IHB after each rebinding.
237 read_c0_mvpcontrol() & ~ MVPCONTROL_VPC );
240 * Only count if the MMU Type indicated is TLB
242 if (((read_vpe_c0_config() & MIPS_CONF_MT) >> 7) == 1) {
243 config1val = read_vpe_c0_config1();
244 tlbsiz += ((config1val >> 25) & 0x3f) + 1;
247 /* Put core back in configuration state */
249 read_c0_mvpcontrol() | MVPCONTROL_VPC );
253 write_c0_mvpcontrol(read_c0_mvpcontrol() | MVPCONTROL_STLB);
257 * Setup kernel data structures to use software total,
258 * rather than read the per-VPE Config1 value. The values
259 * for "CPU 0" gets copied to all the other CPUs as part
260 * of their initialization in smtc_cpu_setup().
263 /* MIPS32 limits TLB indices to 64 */
266 cpu_data[0].tlbsize = current_cpu_data.tlbsize = tlbsiz;
267 smtc_status |= SMTC_TLB_SHARED;
268 local_flush_tlb_all();
270 printk("TLB of %d entry pairs shared by %d VPEs\n",
273 printk("WARNING: TLB Not Sharable on SMTC Boot!\n");
280 * Incrementally build the CPU map out of constituent MIPS MT cores,
281 * using the specified available VPEs and TCs. Plaform code needs
282 * to ensure that each MIPS MT core invokes this routine on reset,
285 * This version of the build_cpu_map and prepare_cpus routines assumes
286 * that *all* TCs of a MIPS MT core will be used for Linux, and that
287 * they will be spread across *all* available VPEs (to minimise the
288 * loss of efficiency due to exception service serialization).
289 * An improved version would pick up configuration information and
290 * possibly leave some TCs/VPEs as "slave" processors.
292 * Use c0_MVPConf0 to find out how many TCs are available, setting up
293 * phys_cpu_present_map and the logical/physical mappings.
296 int __init mipsmt_build_cpu_map(int start_cpu_slot)
301 * The CPU map isn't actually used for anything at this point,
302 * so it's not clear what else we should do apart from set
303 * everything up so that "logical" = "physical".
305 ntcs = ((read_c0_mvpconf0() & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
306 for (i=start_cpu_slot; i<NR_CPUS && i<ntcs; i++) {
307 cpu_set(i, phys_cpu_present_map);
308 __cpu_number_map[i] = i;
309 __cpu_logical_map[i] = i;
311 /* Initialize map of CPUs with FPUs */
312 cpus_clear(mt_fpu_cpumask);
314 /* One of those TC's is the one booting, and not a secondary... */
315 printk("%i available secondary CPU TC(s)\n", i - 1);
321 * Common setup before any secondaries are started
322 * Make sure all CPU's are in a sensible state before we boot any of the
325 * For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly
326 * as possible across the available VPEs.
329 static void smtc_tc_setup(int vpe, int tc, int cpu)
332 write_tc_c0_tchalt(TCHALT_H);
334 write_tc_c0_tcstatus((read_tc_c0_tcstatus()
335 & ~(TCSTATUS_TKSU | TCSTATUS_DA | TCSTATUS_IXMT))
337 write_tc_c0_tccontext(0);
339 write_tc_c0_tcbind(vpe);
340 /* In general, all TCs should have the same cpu_data indications */
341 memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips));
342 /* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */
343 if (cpu_data[0].cputype == CPU_34K)
344 cpu_data[cpu].options &= ~MIPS_CPU_FPU;
345 cpu_data[cpu].vpe_id = vpe;
346 cpu_data[cpu].tc_id = tc;
350 void mipsmt_prepare_cpus(void)
352 int i, vpe, tc, ntc, nvpe, tcpervpe, slop, cpu;
356 struct smtc_ipi *pipi;
358 /* disable interrupts so we can disable MT */
359 local_irq_save(flags);
360 /* disable MT so we can configure */
364 spin_lock_init(&freeIPIq.lock);
367 * We probably don't have as many VPEs as we do SMP "CPUs",
368 * but it's possible - and in any case we'll never use more!
370 for (i=0; i<NR_CPUS; i++) {
371 IPIQ[i].head = IPIQ[i].tail = NULL;
372 spin_lock_init(&IPIQ[i].lock);
374 ipi_timer_latch[i] = 0;
377 /* cpu_data index starts at zero */
379 cpu_data[cpu].vpe_id = 0;
380 cpu_data[cpu].tc_id = 0;
383 /* Report on boot-time options */
384 mips_mt_set_cpuoptions ();
386 printk("Limit of %d VPEs set\n", vpelimit);
388 printk("Limit of %d TCs set\n", tclimit);
390 printk("Shared TLB Use Inhibited - UNSAFE for Multi-VPE Operation\n");
393 printk("ASID mask value override to 0x%x\n", asidmask);
396 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
398 printk("Logic Analyser Trigger on suspected TC hang\n");
399 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
401 /* Put MVPE's into 'configuration state' */
402 write_c0_mvpcontrol( read_c0_mvpcontrol() | MVPCONTROL_VPC );
404 val = read_c0_mvpconf0();
405 nvpe = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
406 if (vpelimit > 0 && nvpe > vpelimit)
408 ntc = ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
411 if (tclimit > 0 && ntc > tclimit)
413 tcpervpe = ntc / nvpe;
414 slop = ntc % nvpe; /* Residual TCs, < NVPE */
416 /* Set up shared TLB */
417 smtc_configure_tlb();
419 for (tc = 0, vpe = 0 ; (vpe < nvpe) && (tc < ntc) ; vpe++) {
424 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_MVP);
427 printk("VPE %d: TC", vpe);
428 for (i = 0; i < tcpervpe; i++) {
430 * TC 0 is bound to VPE 0 at reset,
431 * and is presumably executing this
432 * code. Leave it alone!
435 smtc_tc_setup(vpe,tc, cpu);
443 smtc_tc_setup(vpe,tc, cpu);
452 * Clear any stale software interrupts from VPE's Cause
454 write_vpe_c0_cause(0);
457 * Clear ERL/EXL of VPEs other than 0
458 * and set restricted interrupt enable/mask.
460 write_vpe_c0_status((read_vpe_c0_status()
461 & ~(ST0_BEV | ST0_ERL | ST0_EXL | ST0_IM))
462 | (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7
465 * set config to be the same as vpe0,
466 * particularly kseg0 coherency alg
468 write_vpe_c0_config(read_c0_config());
469 /* Clear any pending timer interrupt */
470 write_vpe_c0_compare(0);
471 /* Propagate Config7 */
472 write_vpe_c0_config7(read_c0_config7());
473 write_vpe_c0_count(read_c0_count());
475 /* enable multi-threading within VPE */
476 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() | VPECONTROL_TE);
478 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
482 * Pull any physically present but unused TCs out of circulation.
484 while (tc < (((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1)) {
485 cpu_clear(tc, phys_cpu_present_map);
486 cpu_clear(tc, cpu_present_map);
490 /* release config state */
491 write_c0_mvpcontrol( read_c0_mvpcontrol() & ~ MVPCONTROL_VPC );
495 /* Set up coprocessor affinity CPU mask(s) */
497 for (tc = 0; tc < ntc; tc++) {
498 if (cpu_data[tc].options & MIPS_CPU_FPU)
499 cpu_set(tc, mt_fpu_cpumask);
502 /* set up ipi interrupts... */
504 /* If we have multiple VPEs running, set up the cross-VPE interrupt */
507 setup_cross_vpe_interrupts();
509 /* Set up queue of free IPI "messages". */
510 nipi = NR_CPUS * IPIBUF_PER_CPU;
514 pipi = kmalloc(nipi *sizeof(struct smtc_ipi), GFP_KERNEL);
516 panic("kmalloc of IPI message buffers failed\n");
518 printk("IPI buffer pool of %d buffers\n", nipi);
519 for (i = 0; i < nipi; i++) {
520 smtc_ipi_nq(&freeIPIq, pipi);
524 /* Arm multithreading and enable other VPEs - but all TCs are Halted */
527 local_irq_restore(flags);
528 /* Initialize SMTC /proc statistics/diagnostics */
534 * Setup the PC, SP, and GP of a secondary processor and start it
536 * smp_bootstrap is the place to resume from
537 * __KSTK_TOS(idle) is apparently the stack pointer
538 * (unsigned long)idle->thread_info the gp
541 void smtc_boot_secondary(int cpu, struct task_struct *idle)
543 extern u32 kernelsp[NR_CPUS];
548 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
551 settc(cpu_data[cpu].tc_id);
554 write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
557 kernelsp[cpu] = __KSTK_TOS(idle);
558 write_tc_gpr_sp(__KSTK_TOS(idle));
561 write_tc_gpr_gp((unsigned long)idle->thread_info);
563 smtc_status |= SMTC_MTC_ACTIVE;
564 write_tc_c0_tchalt(0);
565 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
571 void smtc_init_secondary(void)
574 * Start timer on secondary VPEs if necessary.
575 * plat_timer_setup has already have been invoked by init/main
576 * on "boot" TC. Like per_cpu_trap_init() hack, this assumes that
577 * SMTC init code assigns TCs consdecutively and in ascending order
578 * to across available VPEs.
580 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
581 ((read_c0_tcbind() & TCBIND_CURVPE)
582 != cpu_data[smp_processor_id() - 1].vpe_id)){
583 write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ);
589 void smtc_smp_finish(void)
591 printk("TC %d going on-line as CPU %d\n",
592 cpu_data[smp_processor_id()].tc_id, smp_processor_id());
595 void smtc_cpus_done(void)
600 * Support for SMTC-optimized driver IRQ registration
604 * SMTC Kernel needs to manipulate low-level CPU interrupt mask
605 * in do_IRQ. These are passed in setup_irq_smtc() and stored
609 int setup_irq_smtc(unsigned int irq, struct irqaction * new,
610 unsigned long hwmask)
612 irq_hwmask[irq] = hwmask;
614 return setup_irq(irq, new);
618 * IPI model for SMTC is tricky, because interrupts aren't TC-specific.
619 * Within a VPE one TC can interrupt another by different approaches.
620 * The easiest to get right would probably be to make all TCs except
621 * the target IXMT and set a software interrupt, but an IXMT-based
622 * scheme requires that a handler must run before a new IPI could
623 * be sent, which would break the "broadcast" loops in MIPS MT.
624 * A more gonzo approach within a VPE is to halt the TC, extract
625 * its Restart, Status, and a couple of GPRs, and program the Restart
626 * address to emulate an interrupt.
628 * Within a VPE, one can be confident that the target TC isn't in
629 * a critical EXL state when halted, since the write to the Halt
630 * register could not have issued on the writing thread if the
631 * halting thread had EXL set. So k0 and k1 of the target TC
632 * can be used by the injection code. Across VPEs, one can't
633 * be certain that the target TC isn't in a critical exception
634 * state. So we try a two-step process of sending a software
635 * interrupt to the target VPE, which either handles the event
636 * itself (if it was the target) or injects the event within
640 static void smtc_ipi_qdump(void)
644 for (i = 0; i < NR_CPUS ;i++) {
645 printk("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n",
646 i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail,
652 * The standard atomic.h primitives don't quite do what we want
653 * here: We need an atomic add-and-return-previous-value (which
654 * could be done with atomic_add_return and a decrement) and an
655 * atomic set/zero-and-return-previous-value (which can't really
656 * be done with the atomic.h primitives). And since this is
657 * MIPS MT, we can assume that we have LL/SC.
659 static __inline__ int atomic_postincrement(unsigned int *pv)
661 unsigned long result;
665 __asm__ __volatile__(
671 : "=&r" (result), "=&r" (temp), "=m" (*pv)
678 void smtc_send_ipi(int cpu, int type, unsigned int action)
681 struct smtc_ipi *pipi;
685 if (cpu == smp_processor_id()) {
686 printk("Cannot Send IPI to self!\n");
689 /* Set up a descriptor, to be delivered either promptly or queued */
690 pipi = smtc_ipi_dq(&freeIPIq);
693 mips_mt_regdump(dvpe());
694 panic("IPI Msg. Buffers Depleted\n");
697 pipi->arg = (void *)action;
699 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
700 /* If not on same VPE, enqueue and send cross-VPE interupt */
701 smtc_ipi_nq(&IPIQ[cpu], pipi);
703 settc(cpu_data[cpu].tc_id);
704 write_vpe_c0_cause(read_vpe_c0_cause() | C_SW1);
708 * Not sufficient to do a LOCK_MT_PRA (dmt) here,
709 * since ASID shootdown on the other VPE may
710 * collide with this operation.
713 settc(cpu_data[cpu].tc_id);
714 /* Halt the targeted TC */
715 write_tc_c0_tchalt(TCHALT_H);
719 * Inspect TCStatus - if IXMT is set, we have to queue
720 * a message. Otherwise, we set up the "interrupt"
723 tcstatus = read_tc_c0_tcstatus();
725 if ((tcstatus & TCSTATUS_IXMT) != 0) {
727 * Spin-waiting here can deadlock,
728 * so we queue the message for the target TC.
730 write_tc_c0_tchalt(0);
732 /* Try to reduce redundant timer interrupt messages */
733 if (type == SMTC_CLOCK_TICK) {
734 if (atomic_postincrement(&ipi_timer_latch[cpu])!=0){
735 smtc_ipi_nq(&freeIPIq, pipi);
739 smtc_ipi_nq(&IPIQ[cpu], pipi);
741 post_direct_ipi(cpu, pipi);
742 write_tc_c0_tchalt(0);
749 * Send IPI message to Halted TC, TargTC/TargVPE already having been set
751 static void post_direct_ipi(int cpu, struct smtc_ipi *pipi)
753 struct pt_regs *kstack;
754 unsigned long tcstatus;
755 unsigned long tcrestart;
756 extern u32 kernelsp[NR_CPUS];
757 extern void __smtc_ipi_vector(void);
759 /* Extract Status, EPC from halted TC */
760 tcstatus = read_tc_c0_tcstatus();
761 tcrestart = read_tc_c0_tcrestart();
762 /* If TCRestart indicates a WAIT instruction, advance the PC */
763 if ((tcrestart & 0x80000000)
764 && ((*(unsigned int *)tcrestart & 0xfe00003f) == 0x42000020)) {
768 * Save on TC's future kernel stack
770 * CU bit of Status is indicator that TC was
771 * already running on a kernel stack...
773 if (tcstatus & ST0_CU0) {
774 /* Note that this "- 1" is pointer arithmetic */
775 kstack = ((struct pt_regs *)read_tc_gpr_sp()) - 1;
777 kstack = ((struct pt_regs *)kernelsp[cpu]) - 1;
780 kstack->cp0_epc = (long)tcrestart;
782 kstack->cp0_tcstatus = tcstatus;
783 /* Pass token of operation to be performed kernel stack pad area */
784 kstack->pad0[4] = (unsigned long)pipi;
785 /* Pass address of function to be called likewise */
786 kstack->pad0[5] = (unsigned long)&ipi_decode;
787 /* Set interrupt exempt and kernel mode */
788 tcstatus |= TCSTATUS_IXMT;
789 tcstatus &= ~TCSTATUS_TKSU;
790 write_tc_c0_tcstatus(tcstatus);
792 /* Set TC Restart address to be SMTC IPI vector */
793 write_tc_c0_tcrestart(__smtc_ipi_vector);
796 static void ipi_resched_interrupt(void)
798 /* Return from interrupt should be enough to cause scheduler check */
802 static void ipi_call_interrupt(void)
804 /* Invoke generic function invocation code in smp.c */
805 smp_call_function_interrupt();
808 void ipi_decode(struct smtc_ipi *pipi)
810 void *arg_copy = pipi->arg;
811 int type_copy = pipi->type;
812 int dest_copy = pipi->dest;
814 smtc_ipi_nq(&freeIPIq, pipi);
816 case SMTC_CLOCK_TICK:
818 kstat_this_cpu.irqs[MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR]++;
819 /* Invoke Clock "Interrupt" */
820 ipi_timer_latch[dest_copy] = 0;
821 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
822 clock_hang_reported[dest_copy] = 0;
823 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
824 local_timer_interrupt(0, NULL);
828 switch ((int)arg_copy) {
829 case SMP_RESCHEDULE_YOURSELF:
830 ipi_resched_interrupt();
832 case SMP_CALL_FUNCTION:
833 ipi_call_interrupt();
836 printk("Impossible SMTC IPI Argument 0x%x\n",
842 printk("Impossible SMTC IPI Type 0x%x\n", type_copy);
847 void deferred_smtc_ipi(void)
849 struct smtc_ipi *pipi;
852 int q = smp_processor_id();
855 * Test is not atomic, but much faster than a dequeue,
856 * and the vast majority of invocations will have a null queue.
858 if (IPIQ[q].head != NULL) {
859 while((pipi = smtc_ipi_dq(&IPIQ[q])) != NULL) {
860 /* ipi_decode() should be called with interrupts off */
861 local_irq_save(flags);
863 local_irq_restore(flags);
869 * Send clock tick to all TCs except the one executing the funtion
872 void smtc_timer_broadcast(int vpe)
875 int myTC = cpu_data[smp_processor_id()].tc_id;
876 int myVPE = cpu_data[smp_processor_id()].vpe_id;
878 smtc_cpu_stats[smp_processor_id()].timerints++;
880 for_each_online_cpu(cpu) {
881 if (cpu_data[cpu].vpe_id == myVPE &&
882 cpu_data[cpu].tc_id != myTC)
883 smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
888 * Cross-VPE interrupts in the SMTC prototype use "software interrupts"
889 * set via cross-VPE MTTR manipulation of the Cause register. It would be
890 * in some regards preferable to have external logic for "doorbell" hardware
894 static int cpu_ipi_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_IRQ;
896 static irqreturn_t ipi_interrupt(int irq, void *dev_idm)
898 int my_vpe = cpu_data[smp_processor_id()].vpe_id;
899 int my_tc = cpu_data[smp_processor_id()].tc_id;
901 struct smtc_ipi *pipi;
902 unsigned long tcstatus;
905 unsigned int mtflags;
906 unsigned int vpflags;
909 * So long as cross-VPE interrupts are done via
910 * MFTR/MTTR read-modify-writes of Cause, we need
911 * to stop other VPEs whenever the local VPE does
914 local_irq_save(flags);
916 clear_c0_cause(0x100 << MIPS_CPU_IPI_IRQ);
917 set_c0_status(0x100 << MIPS_CPU_IPI_IRQ);
920 local_irq_restore(flags);
923 * Cross-VPE Interrupt handler: Try to directly deliver IPIs
924 * queued for TCs on this VPE other than the current one.
925 * Return-from-interrupt should cause us to drain the queue
926 * for the current TC, so we ought not to have to do it explicitly here.
929 for_each_online_cpu(cpu) {
930 if (cpu_data[cpu].vpe_id != my_vpe)
933 pipi = smtc_ipi_dq(&IPIQ[cpu]);
935 if (cpu_data[cpu].tc_id != my_tc) {
938 settc(cpu_data[cpu].tc_id);
939 write_tc_c0_tchalt(TCHALT_H);
941 tcstatus = read_tc_c0_tcstatus();
942 if ((tcstatus & TCSTATUS_IXMT) == 0) {
943 post_direct_ipi(cpu, pipi);
946 write_tc_c0_tchalt(0);
949 smtc_ipi_req(&IPIQ[cpu], pipi);
953 * ipi_decode() should be called
954 * with interrupts off
956 local_irq_save(flags);
958 local_irq_restore(flags);
966 static void ipi_irq_dispatch(void)
971 static struct irqaction irq_ipi;
973 static void setup_cross_vpe_interrupts(void)
976 panic("SMTC Kernel requires Vectored Interupt support");
978 set_vi_handler(MIPS_CPU_IPI_IRQ, ipi_irq_dispatch);
980 irq_ipi.handler = ipi_interrupt;
981 irq_ipi.flags = IRQF_DISABLED;
982 irq_ipi.name = "SMTC_IPI";
984 setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ));
986 irq_desc[cpu_ipi_irq].status |= IRQ_PER_CPU;
987 set_irq_handler(cpu_ipi_irq, handle_percpu_irq);
991 * SMTC-specific hacks invoked from elsewhere in the kernel.
994 void smtc_ipi_replay(void)
997 * To the extent that we've ever turned interrupts off,
998 * we may have accumulated deferred IPIs. This is subtle.
999 * If we use the smtc_ipi_qdepth() macro, we'll get an
1000 * exact number - but we'll also disable interrupts
1001 * and create a window of failure where a new IPI gets
1002 * queued after we test the depth but before we re-enable
1003 * interrupts. So long as IXMT never gets set, however,
1004 * we should be OK: If we pick up something and dispatch
1005 * it here, that's great. If we see nothing, but concurrent
1006 * with this operation, another TC sends us an IPI, IXMT
1007 * is clear, and we'll handle it as a real pseudo-interrupt
1008 * and not a pseudo-pseudo interrupt.
1010 if (IPIQ[smp_processor_id()].depth > 0) {
1011 struct smtc_ipi *pipi;
1012 extern void self_ipi(struct smtc_ipi *);
1014 while ((pipi = smtc_ipi_dq(&IPIQ[smp_processor_id()]))) {
1016 smtc_cpu_stats[smp_processor_id()].selfipis++;
1021 EXPORT_SYMBOL(smtc_ipi_replay);
1023 void smtc_idle_loop_hook(void)
1025 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
1034 * printk within DMT-protected regions can deadlock,
1035 * so buffer diagnostic messages for later output.
1038 char id_ho_db_msg[768]; /* worst-case use should be less than 700 */
1040 if (atomic_read(&idle_hook_initialized) == 0) { /* fast test */
1041 if (atomic_add_return(1, &idle_hook_initialized) == 1) {
1043 /* Tedious stuff to just do once */
1044 mvpconf0 = read_c0_mvpconf0();
1045 hook_ntcs = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
1046 if (hook_ntcs > NR_CPUS)
1047 hook_ntcs = NR_CPUS;
1048 for (tc = 0; tc < hook_ntcs; tc++) {
1050 clock_hang_reported[tc] = 0;
1052 for (vpe = 0; vpe < 2; vpe++)
1053 for (im = 0; im < 8; im++)
1054 imstuckcount[vpe][im] = 0;
1055 printk("Idle loop test hook initialized for %d TCs\n", hook_ntcs);
1056 atomic_set(&idle_hook_initialized, 1000);
1058 /* Someone else is initializing in parallel - let 'em finish */
1059 while (atomic_read(&idle_hook_initialized) < 1000)
1064 /* Have we stupidly left IXMT set somewhere? */
1065 if (read_c0_tcstatus() & 0x400) {
1066 write_c0_tcstatus(read_c0_tcstatus() & ~0x400);
1068 printk("Dangling IXMT in cpu_idle()\n");
1071 /* Have we stupidly left an IM bit turned off? */
1072 #define IM_LIMIT 2000
1073 local_irq_save(flags);
1075 pdb_msg = &id_ho_db_msg[0];
1076 im = read_c0_status();
1077 vpe = cpu_data[smp_processor_id()].vpe_id;
1078 for (bit = 0; bit < 8; bit++) {
1080 * In current prototype, I/O interrupts
1081 * are masked for VPE > 0
1083 if (vpemask[vpe][bit]) {
1084 if (!(im & (0x100 << bit)))
1085 imstuckcount[vpe][bit]++;
1087 imstuckcount[vpe][bit] = 0;
1088 if (imstuckcount[vpe][bit] > IM_LIMIT) {
1089 set_c0_status(0x100 << bit);
1091 imstuckcount[vpe][bit] = 0;
1092 pdb_msg += sprintf(pdb_msg,
1093 "Dangling IM %d fixed for VPE %d\n", bit,
1100 * Now that we limit outstanding timer IPIs, check for hung TC
1102 for (tc = 0; tc < NR_CPUS; tc++) {
1103 /* Don't check ourself - we'll dequeue IPIs just below */
1104 if ((tc != smp_processor_id()) &&
1105 ipi_timer_latch[tc] > timerq_limit) {
1106 if (clock_hang_reported[tc] == 0) {
1107 pdb_msg += sprintf(pdb_msg,
1108 "TC %d looks hung with timer latch at %d\n",
1109 tc, ipi_timer_latch[tc]);
1110 clock_hang_reported[tc]++;
1115 local_irq_restore(flags);
1116 if (pdb_msg != &id_ho_db_msg[0])
1117 printk("CPU%d: %s", smp_processor_id(), id_ho_db_msg);
1118 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
1121 * Replay any accumulated deferred IPIs. If "Instant Replay"
1122 * is in use, there should never be any.
1124 #ifndef CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY
1126 #endif /* CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY */
1129 void smtc_soft_dump(void)
1133 printk("Counter Interrupts taken per CPU (TC)\n");
1134 for (i=0; i < NR_CPUS; i++) {
1135 printk("%d: %ld\n", i, smtc_cpu_stats[i].timerints);
1137 printk("Self-IPI invocations:\n");
1138 for (i=0; i < NR_CPUS; i++) {
1139 printk("%d: %ld\n", i, smtc_cpu_stats[i].selfipis);
1142 printk("Timer IPI Backlogs:\n");
1143 for (i=0; i < NR_CPUS; i++) {
1144 printk("%d: %d\n", i, ipi_timer_latch[i]);
1146 printk("%d Recoveries of \"stolen\" FPU\n",
1147 atomic_read(&smtc_fpu_recoveries));
1152 * TLB management routines special to SMTC
1155 void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
1157 unsigned long flags, mtflags, tcstat, prevhalt, asid;
1161 * It would be nice to be able to use a spinlock here,
1162 * but this is invoked from within TLB flush routines
1163 * that protect themselves with DVPE, so if a lock is
1164 * held by another TC, it'll never be freed.
1166 * DVPE/DMT must not be done with interrupts enabled,
1167 * so even so most callers will already have disabled
1168 * them, let's be really careful...
1171 local_irq_save(flags);
1172 if (smtc_status & SMTC_TLB_SHARED) {
1177 tlb = cpu_data[cpu].vpe_id;
1179 asid = asid_cache(cpu);
1182 if (!((asid += ASID_INC) & ASID_MASK) ) {
1183 if (cpu_has_vtag_icache)
1185 /* Traverse all online CPUs (hack requires contigous range) */
1186 for (i = 0; i < num_online_cpus(); i++) {
1188 * We don't need to worry about our own CPU, nor those of
1189 * CPUs who don't share our TLB.
1191 if ((i != smp_processor_id()) &&
1192 ((smtc_status & SMTC_TLB_SHARED) ||
1193 (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))) {
1194 settc(cpu_data[i].tc_id);
1195 prevhalt = read_tc_c0_tchalt() & TCHALT_H;
1197 write_tc_c0_tchalt(TCHALT_H);
1200 tcstat = read_tc_c0_tcstatus();
1201 smtc_live_asid[tlb][(tcstat & ASID_MASK)] |= (asiduse)(0x1 << i);
1203 write_tc_c0_tchalt(0);
1206 if (!asid) /* fix version if needed */
1207 asid = ASID_FIRST_VERSION;
1208 local_flush_tlb_all(); /* start new asid cycle */
1210 } while (smtc_live_asid[tlb][(asid & ASID_MASK)]);
1213 * SMTC shares the TLB within VPEs and possibly across all VPEs.
1215 for (i = 0; i < num_online_cpus(); i++) {
1216 if ((smtc_status & SMTC_TLB_SHARED) ||
1217 (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
1218 cpu_context(i, mm) = asid_cache(i) = asid;
1221 if (smtc_status & SMTC_TLB_SHARED)
1225 local_irq_restore(flags);
1229 * Invoked from macros defined in mmu_context.h
1230 * which must already have disabled interrupts
1231 * and done a DVPE or DMT as appropriate.
1234 void smtc_flush_tlb_asid(unsigned long asid)
1239 entry = read_c0_wired();
1241 /* Traverse all non-wired entries */
1242 while (entry < current_cpu_data.tlbsize) {
1243 write_c0_index(entry);
1247 ehi = read_c0_entryhi();
1248 if ((ehi & ASID_MASK) == asid) {
1250 * Invalidate only entries with specified ASID,
1251 * makiing sure all entries differ.
1253 write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1)));
1254 write_c0_entrylo0(0);
1255 write_c0_entrylo1(0);
1257 tlb_write_indexed();
1261 write_c0_index(PARKED_INDEX);
1266 * Support for single-threading cache flush operations.
1269 static int halt_state_save[NR_CPUS];
1272 * To really, really be sure that nothing is being done
1273 * by other TCs, halt them all. This code assumes that
1274 * a DVPE has already been done, so while their Halted
1275 * state is theoretically architecturally unstable, in
1276 * practice, it's not going to change while we're looking
1280 void smtc_cflush_lockdown(void)
1284 for_each_online_cpu(cpu) {
1285 if (cpu != smp_processor_id()) {
1286 settc(cpu_data[cpu].tc_id);
1287 halt_state_save[cpu] = read_tc_c0_tchalt();
1288 write_tc_c0_tchalt(TCHALT_H);
1294 /* It would be cheating to change the cpu_online states during a flush! */
1296 void smtc_cflush_release(void)
1301 * Start with a hazard barrier to ensure
1302 * that all CACHE ops have played through.
1306 for_each_online_cpu(cpu) {
1307 if (cpu != smp_processor_id()) {
1308 settc(cpu_data[cpu].tc_id);
1309 write_tc_c0_tchalt(halt_state_save[cpu]);