2 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
4 * Elizabeth Clarke (beth@mips.com)
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 #include <linux/kernel.h>
21 #include <linux/sched.h>
22 #include <linux/cpumask.h>
23 #include <linux/interrupt.h>
24 #include <linux/compiler.h>
26 #include <asm/atomic.h>
28 #include <asm/processor.h>
29 #include <asm/system.h>
30 #include <asm/hardirq.h>
31 #include <asm/mmu_context.h>
34 #include <asm/mipsregs.h>
35 #include <asm/mipsmtregs.h>
36 #include <asm/cacheflush.h>
37 #include <asm/mips-boards/maltaint.h>
39 #define MIPS_CPU_IPI_RESCHED_IRQ 0
40 #define MIPS_CPU_IPI_CALL_IRQ 1
42 static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
45 static void dump_mtregisters(int vpe, int tc)
47 printk("vpe %d tc %d\n", vpe, tc);
51 printk(" c0 status 0x%lx\n", read_vpe_c0_status());
52 printk(" vpecontrol 0x%lx\n", read_vpe_c0_vpecontrol());
53 printk(" vpeconf0 0x%lx\n", read_vpe_c0_vpeconf0());
54 printk(" tcstatus 0x%lx\n", read_tc_c0_tcstatus());
55 printk(" tcrestart 0x%lx\n", read_tc_c0_tcrestart());
56 printk(" tcbind 0x%lx\n", read_tc_c0_tcbind());
57 printk(" tchalt 0x%lx\n", read_tc_c0_tchalt());
61 void __init sanitize_tlb_entries(void)
64 unsigned long mvpconf0, ncpu;
69 set_c0_mvpcontrol(MVPCONTROL_VPC);
71 /* Disable TLB sharing */
72 clear_c0_mvpcontrol(MVPCONTROL_STLB);
74 mvpconf0 = read_c0_mvpconf0();
76 printk(KERN_INFO "MVPConf0 0x%lx TLBS %lx PTLBE %ld\n", mvpconf0,
77 (mvpconf0 & MVPCONF0_TLBS) >> MVPCONF0_TLBS_SHIFT,
78 (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT);
80 tlbsiz = (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT;
81 ncpu = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
83 printk(" tlbsiz %d ncpu %ld\n", tlbsiz, ncpu);
86 /* share them out across the vpe's */
89 printk(KERN_INFO "setting Config1.MMU_size to %d\n", tlbsiz);
91 for (i = 0; i < ncpu; i++) {
95 write_c0_config1((read_c0_config1() & ~(0x3f << 25)) | (tlbsiz << 25));
97 write_vpe_c0_config1((read_vpe_c0_config1() & ~(0x3f << 25)) |
102 clear_c0_mvpcontrol(MVPCONTROL_VPC);
105 static void ipi_resched_dispatch (struct pt_regs *regs)
107 do_IRQ(MIPS_CPU_IPI_RESCHED_IRQ, regs);
110 static void ipi_call_dispatch (struct pt_regs *regs)
112 do_IRQ(MIPS_CPU_IPI_CALL_IRQ, regs);
115 irqreturn_t ipi_resched_interrupt(int irq, void *dev_id, struct pt_regs *regs)
120 irqreturn_t ipi_call_interrupt(int irq, void *dev_id, struct pt_regs *regs)
122 smp_call_function_interrupt();
127 static struct irqaction irq_resched = {
128 .handler = ipi_resched_interrupt,
129 .flags = SA_INTERRUPT,
130 .name = "IPI_resched"
133 static struct irqaction irq_call = {
134 .handler = ipi_call_interrupt,
135 .flags = SA_INTERRUPT,
140 * Common setup before any secondaries are started
141 * Make sure all CPU's are in a sensible state before we boot any of the
144 void prom_prepare_cpus(unsigned int max_cpus)
152 /* disable MT so we can configure */
156 /* Put MVPE's into 'configuration state' */
157 set_c0_mvpcontrol(MVPCONTROL_VPC);
159 val = read_c0_mvpconf0();
161 /* we'll always have more TC's than VPE's, so loop setting everything
162 to a sensible state */
163 for (i = 0, num = 0; i <= ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT); i++) {
167 if (i <= ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)) {
169 /* deactivate all but vpe0 */
171 unsigned long tmp = read_vpe_c0_vpeconf0();
173 tmp &= ~VPECONF0_VPA;
177 write_vpe_c0_vpeconf0(tmp);
179 /* Record this as available CPU */
181 cpu_set(i, phys_cpu_present_map);
182 __cpu_number_map[i] = ++num;
183 __cpu_logical_map[num] = i;
187 /* disable multi-threading with TC's */
188 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
191 write_vpe_c0_status((read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0);
192 write_vpe_c0_cause(read_vpe_c0_cause() & ~CAUSEF_IP);
194 /* set config to be the same as vpe0, particularly kseg0 coherency alg */
195 write_vpe_c0_config( read_c0_config());
205 /* bind a TC to each VPE, May as well put all excess TC's
207 if ( i >= (((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1) )
208 write_tc_c0_tcbind(read_tc_c0_tcbind() | ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) );
210 write_tc_c0_tcbind( read_tc_c0_tcbind() | i);
213 write_vpe_c0_vpeconf0( read_vpe_c0_vpeconf0() | (i << VPECONF0_XTC_SHIFT));
216 tmp = read_tc_c0_tcstatus();
218 /* mark not allocated and not dynamically allocatable */
219 tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
220 tmp |= TCSTATUS_IXMT; /* interrupt exempt */
221 write_tc_c0_tcstatus(tmp);
223 write_tc_c0_tchalt(TCHALT_H);
227 /* Release config state */
228 clear_c0_mvpcontrol(MVPCONTROL_VPC);
230 /* We'll wait until starting the secondaries before starting MVPE */
232 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
234 /* set up ipi interrupts */
236 set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
237 set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
240 cpu_ipi_resched_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
241 cpu_ipi_call_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ;
243 setup_irq(cpu_ipi_resched_irq, &irq_resched);
244 setup_irq(cpu_ipi_call_irq, &irq_call);
246 /* need to mark IPI's as IRQ_PER_CPU */
247 irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU;
248 irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU;
252 * Setup the PC, SP, and GP of a secondary processor and start it
254 * smp_bootstrap is the place to resume from
255 * __KSTK_TOS(idle) is apparently the stack pointer
256 * (unsigned long)idle->thread_info the gp
257 * assumes a 1:1 mapping of TC => VPE
259 void prom_boot_secondary(int cpu, struct task_struct *idle)
261 struct thread_info *gp = task_thread_info(idle);
263 set_c0_mvpcontrol(MVPCONTROL_VPC);
268 write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
270 /* enable the tc this vpe/cpu will be running */
271 write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A);
273 write_tc_c0_tchalt(0);
276 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
279 write_tc_gpr_sp( __KSTK_TOS(idle));
282 write_tc_gpr_gp((unsigned long)gp);
284 flush_icache_range((unsigned long)gp, (unsigned long)(gp + 1));
286 /* finally out of configuration and into chaos */
287 clear_c0_mvpcontrol(MVPCONTROL_VPC);
292 void prom_init_secondary(void)
294 write_c0_status((read_c0_status() & ~ST0_IM ) |
295 (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7));
298 void prom_smp_finish(void)
300 write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
305 void prom_cpus_done(void)
309 void core_send_ipi(int cpu, unsigned int action)
315 local_irq_save (flags);
317 vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */
320 case SMP_CALL_FUNCTION:
324 case SMP_RESCHEDULE_YOURSELF:
330 /* 1:1 mapping of vpe and tc... */
332 write_vpe_c0_cause(read_vpe_c0_cause() | i);
335 local_irq_restore(flags);