2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Copyright (C) 2001 MIPS Technologies, Inc.
9 * Copyright (C) 2002 Maciej W. Rozycki
11 #include <linux/config.h>
12 #include <linux/init.h>
15 #include <asm/cacheops.h>
16 #include <asm/regdef.h>
17 #include <asm/fpregdef.h>
18 #include <asm/mipsregs.h>
19 #include <asm/stackframe.h>
22 #define PANIC_PIC(msg) \
35 NESTED(except_vec0_generic, 0, sp)
36 PANIC_PIC("Exception vector 0 called")
37 END(except_vec0_generic)
39 NESTED(except_vec1_generic, 0, sp)
40 PANIC_PIC("Exception vector 1 called")
41 END(except_vec1_generic)
44 * General exception vector for all other CPUs.
46 * Be careful when changing this, it has to be at most 128 bytes
47 * to fit into space reserved for the exception handler.
49 NESTED(except_vec3_generic, 0, sp)
52 #if R5432_CP0_INTERRUPT_WAR
60 PTR_L k0, exception_handlers(k1)
63 END(except_vec3_generic)
66 * General exception handler for CPUs with virtual coherency exception.
68 * Be careful when changing this, it has to be at most 256 (as a special
69 * exception) bytes to fit into space reserved for the exception handler.
71 NESTED(except_vec3_r4000, 0, sp)
81 beq k1, k0, handle_vced
83 beq k1, k0, handle_vcei
88 PTR_L k0, exception_handlers(k1)
92 * Big shit, we now may have two dirty primary cache lines for the same
93 * physical address. We can safely invalidate the line pointed to by
94 * c0_badvaddr because after return from this exception handler the
95 * load / store will be re-executed.
99 li k1, -4 # Is this ...
100 and k0, k1 # ... really needed?
102 cache Index_Store_Tag_D, (k0)
103 cache Hit_Writeback_Inv_SD, (k0)
104 #ifdef CONFIG_PROC_FS
105 PTR_LA k0, vced_count
113 MFC0 k0, CP0_BADVADDR
114 cache Hit_Writeback_Inv_SD, (k0) # also cleans pi
115 #ifdef CONFIG_PROC_FS
116 PTR_LA k0, vcei_count
123 END(except_vec3_r4000)
128 NESTED(handle_int, PT_SIZE, sp)
132 PTR_LA ra, ret_from_irq
140 * Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
141 * This is a dedicated interrupt exception vector which reduces the
142 * interrupt processing overhead. The jump instruction will be replaced
143 * at the initialization time.
145 * Be careful when changing this, it has to be at most 128 bytes
146 * to fit into space reserved for the exception handler.
148 NESTED(except_vec4, 0, sp)
149 1: j 1b /* Dummy, will be replaced */
153 * EJTAG debug exception handler.
154 * The EJTAG debug exception entry point is 0xbfc00480, which
155 * normally is in the boot PROM, so the boot PROM must do a
156 * unconditional jump to this vector.
158 NESTED(except_vec_ejtag_debug, 0, sp)
159 j ejtag_debug_handler
160 END(except_vec_ejtag_debug)
165 * Vectored interrupt handler.
166 * This prototype is copied to ebase + n*IntCtl.VS and patched
167 * to invoke the handler
169 NESTED(except_vec_vi, 0, sp)
174 EXPORT(except_vec_vi_lui)
175 lui v0, 0 /* Patched */
176 j except_vec_vi_handler
177 EXPORT(except_vec_vi_ori)
178 ori v0, 0 /* Patched */
181 EXPORT(except_vec_vi_end)
184 * Common Vectored Interrupt code
185 * Complete the register saves and invoke the handler which is passed in $v0
187 NESTED(except_vec_vi_handler, 0, sp)
194 END(except_vec_vi_handler)
197 * EJTAG debug exception handler.
199 NESTED(ejtag_debug_handler, PT_SIZE, sp)
205 sll k0, k0, 30 # Check for SDBBP.
206 bgez k0, ejtag_return
208 PTR_LA k0, ejtag_debug_buffer
212 jal ejtag_exception_handler
214 PTR_LA k0, ejtag_debug_buffer
222 END(ejtag_debug_handler)
225 * This buffer is reserved for the use of the EJTAG debug
229 EXPORT(ejtag_debug_buffer)
236 * NMI debug exception handler for MIPS reference boards.
237 * The NMI debug exception entry point is 0xbfc00000, which
238 * normally is in the boot PROM, so the boot PROM must do a
239 * unconditional jump to this vector.
241 NESTED(except_vec_nmi, 0, sp)
247 NESTED(nmi_handler, PT_SIZE, sp)
252 jal nmi_exception_handler
259 .macro __build_clear_none
262 .macro __build_clear_sti
266 .macro __build_clear_cli
270 .macro __build_clear_fpe
278 .macro __build_clear_ade
279 MFC0 t0, CP0_BADVADDR
280 PTR_S t0, PT_BVADDR(sp)
284 .macro __BUILD_silent exception
287 /* Gas tries to parse the PRINT argument as a string containing
288 string escapes and emits bogus warnings if it believes to
289 recognize an unknown escape code. So make the arguments
290 start with an n and gas will believe \n is ok ... */
291 .macro __BUILD_verbose nexception
292 LONG_L a1, PT_EPC(sp)
294 PRINT("Got \nexception at %08lx\012")
297 PRINT("Got \nexception at %016lx\012")
301 .macro __BUILD_count exception
302 LONG_L t0,exception_count_\exception
304 LONG_S t0,exception_count_\exception
305 .comm exception_count\exception, 8, 8
308 .macro __BUILD_HANDLER exception handler clear verbose ext
310 NESTED(handle_\exception, PT_SIZE, sp)
313 FEXPORT(handle_\exception\ext)
316 __BUILD_\verbose \exception
320 END(handle_\exception)
323 .macro BUILD_HANDLER exception handler clear verbose
324 __BUILD_HANDLER \exception \handler \clear \verbose _int
327 BUILD_HANDLER adel ade ade silent /* #4 */
328 BUILD_HANDLER ades ade ade silent /* #5 */
329 BUILD_HANDLER ibe be cli silent /* #6 */
330 BUILD_HANDLER dbe be cli silent /* #7 */
331 BUILD_HANDLER bp bp sti silent /* #9 */
332 BUILD_HANDLER ri ri sti silent /* #10 */
333 BUILD_HANDLER cpu cpu sti silent /* #11 */
334 BUILD_HANDLER ov ov sti silent /* #12 */
335 BUILD_HANDLER tr tr sti silent /* #13 */
336 BUILD_HANDLER fpe fpe fpe silent /* #15 */
337 BUILD_HANDLER mdmx mdmx sti silent /* #22 */
338 BUILD_HANDLER watch watch sti verbose /* #23 */
339 BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
340 BUILD_HANDLER mt mt sti verbose /* #25 */
341 BUILD_HANDLER dsp dsp sti silent /* #26 */
342 BUILD_HANDLER reserved reserved sti verbose /* others */
345 /* A temporary overflow handler used by check_daddi(). */
349 BUILD_HANDLER daddi_ov daddi_ov none silent /* #12 */