SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   6  * Copyright (C) 1994 - 2003 Ralf Baechle
   7  * Copyright (C) 2001, 2004  MIPS Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/config.h>
  15 #include <linux/init.h>
  16 #include <linux/kernel.h>
  17 #include <linux/ptrace.h>
  18 #include <linux/stddef.h>
  19
  20 #include <asm/cpu.h>
  21 #include <asm/fpu.h>
  22 #include <asm/mipsregs.h>
  23 #include <asm/system.h>
  24
  25 /*
  26  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  27  * the implementation of the "wait" feature differs between CPU families. This
  28  * points to the function that implements CPU specific wait.
  29  * The wait instruction stops the pipeline and reduces the power consumption of
  30  * the CPU very much.
  31  */
  32 void (*cpu_wait)(void) = NULL;
  33
  34 static void r3081_wait(void)
  35 {
  36         unsigned long cfg = read_c0_conf();
  37         write_c0_conf(cfg | R30XX_CONF_HALT);
  38 }
  39
  40 static void r39xx_wait(void)
  41 {
  42         unsigned long cfg = read_c0_conf();
  43         write_c0_conf(cfg | TX39_CONF_HALT);
  44 }
  45
  46 static void r4k_wait(void)
  47 {
  48         __asm__(".set\tmips3\n\t"
  49                 "wait\n\t"
  50                 ".set\tmips0");
  51 }
  52
  53 /* The Au1xxx wait is available only if using 32khz counter or
  54  * external timer source, but specifically not CP0 Counter. */
  55 int allow_au1k_wait;
  56
  57 static void au1k_wait(void)
  58 {
  59         /* using the wait instruction makes CP0 counter unusable */
  60         __asm__(".set mips3\n\t"
  61                 "cache 0x14, 0(%0)\n\t"
  62                 "cache 0x14, 32(%0)\n\t"
  63                 "sync\n\t"
  64                 "nop\n\t"
  65                 "wait\n\t"
  66                 "nop\n\t"
  67                 "nop\n\t"
  68                 "nop\n\t"
  69                 "nop\n\t"
  70                 ".set mips0\n\t"
  71                 : : "r" (au1k_wait));
  72 }
  73
  74 static int __initdata nowait = 0;
  75
  76 int __init wait_disable(char *s)
  77 {
  78         nowait = 1;
  79
  80         return 1;
  81 }
  82
  83 __setup("nowait", wait_disable);
  84
  85 static inline void check_wait(void)
  86 {
  87         struct cpuinfo_mips *c = &current_cpu_data;
  88
  89         printk("Checking for 'wait' instruction... ");
  90         if (nowait) {
  91                 printk (" disabled.\n");
  92                 return;
  93         }
  94
  95         switch (c->cputype) {
  96         case CPU_R3081:
  97         case CPU_R3081E:
  98                 cpu_wait = r3081_wait;
  99                 printk(" available.\n");
 100                 break;
 101         case CPU_TX3927:
 102                 cpu_wait = r39xx_wait;
 103                 printk(" available.\n");
 104                 break;
 105         case CPU_R4200:
 106 /*      case CPU_R4300: */
 107         case CPU_R4600:
 108         case CPU_R4640:
 109         case CPU_R4650:
 110         case CPU_R4700:
 111         case CPU_R5000:
 112         case CPU_NEVADA:
 113         case CPU_RM7000:
 114         case CPU_RM9000:
 115         case CPU_TX49XX:
 116         case CPU_4KC:
 117         case CPU_4KEC:
 118         case CPU_4KSC:
 119         case CPU_5KC:
 120 /*      case CPU_20KC:*/
 121         case CPU_24K:
 122         case CPU_25KF:
 123         case CPU_34K:
 124                 cpu_wait = r4k_wait;
 125                 printk(" available.\n");
 126                 break;
 127         case CPU_AU1000:
 128         case CPU_AU1100:
 129         case CPU_AU1500:
 130         case CPU_AU1550:
 131         case CPU_AU1200:
 132                 if (allow_au1k_wait) {
 133                         cpu_wait = au1k_wait;
 134                         printk(" available.\n");
 135                 } else
 136                         printk(" unavailable.\n");
 137                 break;
 138         default:
 139                 printk(" unavailable.\n");
 140                 break;
 141         }
 142 }
 143
 144 void __init check_bugs32(void)
 145 {
 146         check_wait();
 147 }
 148
 149 /*
 150  * Probe whether cpu has config register by trying to play with
 151  * alternate cache bit and see whether it matters.
 152  * It's used by cpu_probe to distinguish between R3000A and R3081.
 153  */
 154 static inline int cpu_has_confreg(void)
 155 {
 156 #ifdef CONFIG_CPU_R3000
 157         extern unsigned long r3k_cache_size(unsigned long);
 158         unsigned long size1, size2;
 159         unsigned long cfg = read_c0_conf();
 160
 161         size1 = r3k_cache_size(ST0_ISC);
 162         write_c0_conf(cfg ^ R30XX_CONF_AC);
 163         size2 = r3k_cache_size(ST0_ISC);
 164         write_c0_conf(cfg);
 165         return size1 != size2;
 166 #else
 167         return 0;
 168 #endif
 169 }
 170
 171 /*
 172  * Get the FPU Implementation/Revision.
 173  */
 174 static inline unsigned long cpu_get_fpu_id(void)
 175 {
 176         unsigned long tmp, fpu_id;
 177
 178         tmp = read_c0_status();
 179         __enable_fpu();
 180         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 181         write_c0_status(tmp);
 182         return fpu_id;
 183 }
 184
 185 /*
 186  * Check the CPU has an FPU the official way.
 187  */
 188 static inline int __cpu_has_fpu(void)
 189 {
 190         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 191 }
 192
 193 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
 194                 | MIPS_CPU_COUNTER)
 195
 196 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
 197 {
 198         switch (c->processor_id & 0xff00) {
 199         case PRID_IMP_R2000:
 200                 c->cputype = CPU_R2000;
 201                 c->isa_level = MIPS_CPU_ISA_I;
 202                 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
 203                 if (__cpu_has_fpu())
 204                         c->options |= MIPS_CPU_FPU;
 205                 c->tlbsize = 64;
 206                 break;
 207         case PRID_IMP_R3000:
 208                 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
 209                         if (cpu_has_confreg())
 210                                 c->cputype = CPU_R3081E;
 211                         else
 212                                 c->cputype = CPU_R3000A;
 213                 else
 214                         c->cputype = CPU_R3000;
 215                 c->isa_level = MIPS_CPU_ISA_I;
 216                 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
 217                 if (__cpu_has_fpu())
 218                         c->options |= MIPS_CPU_FPU;
 219                 c->tlbsize = 64;
 220                 break;
 221         case PRID_IMP_R4000:
 222                 if (read_c0_config() & CONF_SC) {
 223                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 224                                 c->cputype = CPU_R4400PC;
 225                         else
 226                                 c->cputype = CPU_R4000PC;
 227                 } else {
 228                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 229                                 c->cputype = CPU_R4400SC;
 230                         else
 231                                 c->cputype = CPU_R4000SC;
 232                 }
 233
 234                 c->isa_level = MIPS_CPU_ISA_III;
 235                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 236                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 237                              MIPS_CPU_LLSC;
 238                 c->tlbsize = 48;
 239                 break;
 240         case PRID_IMP_VR41XX:
 241                 switch (c->processor_id & 0xf0) {
 242                 case PRID_REV_VR4111:
 243                         c->cputype = CPU_VR4111;
 244                         break;
 245                 case PRID_REV_VR4121:
 246                         c->cputype = CPU_VR4121;
 247                         break;
 248                 case PRID_REV_VR4122:
 249                         if ((c->processor_id & 0xf) < 0x3)
 250                                 c->cputype = CPU_VR4122;
 251                         else
 252                                 c->cputype = CPU_VR4181A;
 253                         break;
 254                 case PRID_REV_VR4130:
 255                         if ((c->processor_id & 0xf) < 0x4)
 256                                 c->cputype = CPU_VR4131;
 257                         else
 258                                 c->cputype = CPU_VR4133;
 259                         break;
 260                 default:
 261                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 262                         c->cputype = CPU_VR41XX;
 263                         break;
 264                 }
 265                 c->isa_level = MIPS_CPU_ISA_III;
 266                 c->options = R4K_OPTS;
 267                 c->tlbsize = 32;
 268                 break;
 269         case PRID_IMP_R4300:
 270                 c->cputype = CPU_R4300;
 271                 c->isa_level = MIPS_CPU_ISA_III;
 272                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 273                              MIPS_CPU_LLSC;
 274                 c->tlbsize = 32;
 275                 break;
 276         case PRID_IMP_R4600:
 277                 c->cputype = CPU_R4600;
 278                 c->isa_level = MIPS_CPU_ISA_III;
 279                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 280                 c->tlbsize = 48;
 281                 break;
 282         #if 0
 283         case PRID_IMP_R4650:
 284                 /*
 285                  * This processor doesn't have an MMU, so it's not
 286                  * "real easy" to run Linux on it. It is left purely
 287                  * for documentation.  Commented out because it shares
 288                  * it's c0_prid id number with the TX3900.
 289                  */
 290                 c->cputype = CPU_R4650;
 291                 c->isa_level = MIPS_CPU_ISA_III;
 292                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 293                 c->tlbsize = 48;
 294                 break;
 295         #endif
 296         case PRID_IMP_TX39:
 297                 c->isa_level = MIPS_CPU_ISA_I;
 298                 c->options = MIPS_CPU_TLB;
 299
 300                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 301                         c->cputype = CPU_TX3927;
 302                         c->tlbsize = 64;
 303                 } else {
 304                         switch (c->processor_id & 0xff) {
 305                         case PRID_REV_TX3912:
 306                                 c->cputype = CPU_TX3912;
 307                                 c->tlbsize = 32;
 308                                 break;
 309                         case PRID_REV_TX3922:
 310                                 c->cputype = CPU_TX3922;
 311                                 c->tlbsize = 64;
 312                                 break;
 313                         default:
 314                                 c->cputype = CPU_UNKNOWN;
 315                                 break;
 316                         }
 317                 }
 318                 break;
 319         case PRID_IMP_R4700:
 320                 c->cputype = CPU_R4700;
 321                 c->isa_level = MIPS_CPU_ISA_III;
 322                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 323                              MIPS_CPU_LLSC;
 324                 c->tlbsize = 48;
 325                 break;
 326         case PRID_IMP_TX49:
 327                 c->cputype = CPU_TX49XX;
 328                 c->isa_level = MIPS_CPU_ISA_III;
 329                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 330                 if (!(c->processor_id & 0x08))
 331                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 332                 c->tlbsize = 48;
 333                 break;
 334         case PRID_IMP_R5000:
 335                 c->cputype = CPU_R5000;
 336                 c->isa_level = MIPS_CPU_ISA_IV;
 337                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 338                              MIPS_CPU_LLSC;
 339                 c->tlbsize = 48;
 340                 break;
 341         case PRID_IMP_R5432:
 342                 c->cputype = CPU_R5432;
 343                 c->isa_level = MIPS_CPU_ISA_IV;
 344                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 345                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 346                 c->tlbsize = 48;
 347                 break;
 348         case PRID_IMP_R5500:
 349                 c->cputype = CPU_R5500;
 350                 c->isa_level = MIPS_CPU_ISA_IV;
 351                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 352                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 353                 c->tlbsize = 48;
 354                 break;
 355         case PRID_IMP_NEVADA:
 356                 c->cputype = CPU_NEVADA;
 357                 c->isa_level = MIPS_CPU_ISA_IV;
 358                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 359                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 360                 c->tlbsize = 48;
 361                 break;
 362         case PRID_IMP_R6000:
 363                 c->cputype = CPU_R6000;
 364                 c->isa_level = MIPS_CPU_ISA_II;
 365                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 366                              MIPS_CPU_LLSC;
 367                 c->tlbsize = 32;
 368                 break;
 369         case PRID_IMP_R6000A:
 370                 c->cputype = CPU_R6000A;
 371                 c->isa_level = MIPS_CPU_ISA_II;
 372                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 373                              MIPS_CPU_LLSC;
 374                 c->tlbsize = 32;
 375                 break;
 376         case PRID_IMP_RM7000:
 377                 c->cputype = CPU_RM7000;
 378                 c->isa_level = MIPS_CPU_ISA_IV;
 379                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 380                              MIPS_CPU_LLSC;
 381                 /*
 382                  * Undocumented RM7000:  Bit 29 in the info register of
 383                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 384                  * entries.
 385                  *
 386                  * 29      1 =>    64 entry JTLB
 387                  *         0 =>    48 entry JTLB
 388                  */
 389                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 390                 break;
 391         case PRID_IMP_RM9000:
 392                 c->cputype = CPU_RM9000;
 393                 c->isa_level = MIPS_CPU_ISA_IV;
 394                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 395                              MIPS_CPU_LLSC;
 396                 /*
 397                  * Bit 29 in the info register of the RM9000
 398                  * indicates if the TLB has 48 or 64 entries.
 399                  *
 400                  * 29      1 =>    64 entry JTLB
 401                  *         0 =>    48 entry JTLB
 402                  */
 403                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 404                 break;
 405         case PRID_IMP_R8000:
 406                 c->cputype = CPU_R8000;
 407                 c->isa_level = MIPS_CPU_ISA_IV;
 408                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 409                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 410                              MIPS_CPU_LLSC;
 411                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 412                 break;
 413         case PRID_IMP_R10000:
 414                 c->cputype = CPU_R10000;
 415                 c->isa_level = MIPS_CPU_ISA_IV;
 416                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 417                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 418                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 419                              MIPS_CPU_LLSC;
 420                 c->tlbsize = 64;
 421                 break;
 422         case PRID_IMP_R12000:
 423                 c->cputype = CPU_R12000;
 424                 c->isa_level = MIPS_CPU_ISA_IV;
 425                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 426                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 427                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 428                              MIPS_CPU_LLSC;
 429                 c->tlbsize = 64;
 430                 break;
 431         }
 432 }
 433
 434 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 435 {
 436         unsigned int config0;
 437         int isa;
 438
 439         config0 = read_c0_config();
 440
 441         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
 442                 c->options |= MIPS_CPU_TLB | MIPS_CPU_4KTLB;
 443         isa = (config0 & MIPS_CONF_AT) >> 13;
 444         switch (isa) {
 445         case 0:
 446                 c->isa_level = MIPS_CPU_ISA_M32;
 447                 break;
 448         case 2:
 449                 c->isa_level = MIPS_CPU_ISA_M64;
 450                 break;
 451         default:
 452                 panic("Unsupported ISA type, cp0.config0.at: %d.", isa);
 453         }
 454
 455         return config0 & MIPS_CONF_M;
 456 }
 457
 458 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 459 {
 460         unsigned int config1;
 461
 462         config1 = read_c0_config1();
 463
 464         if (config1 & MIPS_CONF1_MD)
 465                 c->ases |= MIPS_ASE_MDMX;
 466         if (config1 & MIPS_CONF1_WR)
 467                 c->options |= MIPS_CPU_WATCH;
 468         if (config1 & MIPS_CONF1_CA)
 469                 c->ases |= MIPS_ASE_MIPS16;
 470         if (config1 & MIPS_CONF1_EP)
 471                 c->options |= MIPS_CPU_EJTAG;
 472         if (config1 & MIPS_CONF1_FP) {
 473                 c->options |= MIPS_CPU_FPU;
 474                 c->options |= MIPS_CPU_32FPR;
 475         }
 476         if (cpu_has_tlb)
 477                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 478
 479         return config1 & MIPS_CONF_M;
 480 }
 481
 482 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 483 {
 484         unsigned int config2;
 485
 486         config2 = read_c0_config2();
 487
 488         if (config2 & MIPS_CONF2_SL)
 489                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 490
 491         return config2 & MIPS_CONF_M;
 492 }
 493
 494 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 495 {
 496         unsigned int config3;
 497
 498         config3 = read_c0_config3();
 499
 500         if (config3 & MIPS_CONF3_SM)
 501                 c->ases |= MIPS_ASE_SMARTMIPS;
 502         if (config3 & MIPS_CONF3_DSP)
 503                 c->ases |= MIPS_ASE_DSP;
 504
 505         return config3 & MIPS_CONF_M;
 506 }
 507
 508 static inline void decode_configs(struct cpuinfo_mips *c)
 509 {
 510         /* MIPS32 or MIPS64 compliant CPU.  */
 511         c->options = MIPS_CPU_4KEX | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
 512                      MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 513
 514         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 515
 516         /* Read Config registers.  */
 517         if (!decode_config0(c))
 518                 return;                 /* actually worth a panic() */
 519         if (!decode_config1(c))
 520                 return;
 521         if (!decode_config2(c))
 522                 return;
 523         if (!decode_config3(c))
 524                 return;
 525 }
 526
 527 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
 528 {
 529         decode_configs(c);
 530         switch (c->processor_id & 0xff00) {
 531         case PRID_IMP_4KC:
 532                 c->cputype = CPU_4KC;
 533                 break;
 534         case PRID_IMP_4KEC:
 535                 c->cputype = CPU_4KEC;
 536                 break;
 537         case PRID_IMP_4KECR2:
 538                 c->cputype = CPU_4KEC;
 539                 break;
 540         case PRID_IMP_4KSC:
 541                 c->cputype = CPU_4KSC;
 542                 break;
 543         case PRID_IMP_5KC:
 544                 c->cputype = CPU_5KC;
 545                 break;
 546         case PRID_IMP_20KC:
 547                 c->cputype = CPU_20KC;
 548                 break;
 549         case PRID_IMP_24K:
 550         case PRID_IMP_24KE:
 551                 c->cputype = CPU_24K;
 552                 break;
 553         case PRID_IMP_25KF:
 554                 c->cputype = CPU_25KF;
 555                 /* Probe for L2 cache */
 556                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 557                 break;
 558         case PRID_IMP_34K:
 559                 c->cputype = CPU_34K;
 560                 c->isa_level = MIPS_CPU_ISA_M32;
 561                 break;
 562         }
 563 }
 564
 565 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
 566 {
 567         decode_configs(c);
 568         switch (c->processor_id & 0xff00) {
 569         case PRID_IMP_AU1_REV1:
 570         case PRID_IMP_AU1_REV2:
 571                 switch ((c->processor_id >> 24) & 0xff) {
 572                 case 0:
 573                         c->cputype = CPU_AU1000;
 574                         break;
 575                 case 1:
 576                         c->cputype = CPU_AU1500;
 577                         break;
 578                 case 2:
 579                         c->cputype = CPU_AU1100;
 580                         break;
 581                 case 3:
 582                         c->cputype = CPU_AU1550;
 583                         break;
 584                 case 4:
 585                         c->cputype = CPU_AU1200;
 586                         break;
 587                 default:
 588                         panic("Unknown Au Core!");
 589                         break;
 590                 }
 591                 break;
 592         }
 593 }
 594
 595 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
 596 {
 597         decode_configs(c);
 598         switch (c->processor_id & 0xff00) {
 599         case PRID_IMP_SB1:
 600                 c->cputype = CPU_SB1;
 601 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
 602                 /* FPU in pass1 is known to have issues. */
 603                 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 604 #endif
 605                 break;
 606         }
 607 }
 608
 609 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
 610 {
 611         decode_configs(c);
 612         switch (c->processor_id & 0xff00) {
 613         case PRID_IMP_SR71000:
 614                 c->cputype = CPU_SR71000;
 615                 c->scache.ways = 8;
 616                 c->tlbsize = 64;
 617                 break;
 618         }
 619 }
 620
 621 __init void cpu_probe(void)
 622 {
 623         struct cpuinfo_mips *c = &current_cpu_data;
 624
 625         c->processor_id = PRID_IMP_UNKNOWN;
 626         c->fpu_id       = FPIR_IMP_NONE;
 627         c->cputype      = CPU_UNKNOWN;
 628
 629         c->processor_id = read_c0_prid();
 630         switch (c->processor_id & 0xff0000) {
 631         case PRID_COMP_LEGACY:
 632                 cpu_probe_legacy(c);
 633                 break;
 634         case PRID_COMP_MIPS:
 635                 cpu_probe_mips(c);
 636                 break;
 637         case PRID_COMP_ALCHEMY:
 638                 cpu_probe_alchemy(c);
 639                 break;
 640         case PRID_COMP_SIBYTE:
 641                 cpu_probe_sibyte(c);
 642                 break;
 643         case PRID_COMP_SANDCRAFT:
 644                 cpu_probe_sandcraft(c);
 645                 break;
 646         default:
 647                 c->cputype = CPU_UNKNOWN;
 648         }
 649         if (c->options & MIPS_CPU_FPU) {
 650                 c->fpu_id = cpu_get_fpu_id();
 651
 652                 if (c->isa_level == MIPS_CPU_ISA_M32 ||
 653                     c->isa_level == MIPS_CPU_ISA_M64) {
 654                         if (c->fpu_id & MIPS_FPIR_3D)
 655                                 c->ases |= MIPS_ASE_MIPS3D;
 656                 }
 657         }
 658 }
 659
 660 __init void cpu_report(void)
 661 {
 662         struct cpuinfo_mips *c = &current_cpu_data;
 663
 664         printk("CPU revision is: %08x\n", c->processor_id);
 665         if (c->options & MIPS_CPU_FPU)
 666                 printk("FPU revision is: %08x\n", c->fpu_id);
 667 }