SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004  MIPS Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/stddef.h>
  18
  19 #include <asm/bugs.h>
  20 #include <asm/cpu.h>
  21 #include <asm/fpu.h>
  22 #include <asm/mipsregs.h>
  23 #include <asm/system.h>
  24
  25 /*
  26  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  27  * the implementation of the "wait" feature differs between CPU families. This
  28  * points to the function that implements CPU specific wait.
  29  * The wait instruction stops the pipeline and reduces the power consumption of
  30  * the CPU very much.
  31  */
  32 void (*cpu_wait)(void) = NULL;
  33
  34 static void r3081_wait(void)
  35 {
  36         unsigned long cfg = read_c0_conf();
  37         write_c0_conf(cfg | R30XX_CONF_HALT);
  38 }
  39
  40 static void r39xx_wait(void)
  41 {
  42         local_irq_disable();
  43         if (!need_resched())
  44                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
  45         local_irq_enable();
  46 }
  47
  48 /*
  49  * There is a race when WAIT instruction executed with interrupt
  50  * enabled.
  51  * But it is implementation-dependent wheter the pipelie restarts when
  52  * a non-enabled interrupt is requested.
  53  */
  54 static void r4k_wait(void)
  55 {
  56         __asm__("       .set    mips3                   \n"
  57                 "       wait                            \n"
  58                 "       .set    mips0                   \n");
  59 }
  60
  61 /*
  62  * This variant is preferable as it allows testing need_resched and going to
  63  * sleep depending on the outcome atomically.  Unfortunately the "It is
  64  * implementation-dependent whether the pipeline restarts when a non-enabled
  65  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
  66  * using this version a gamble.
  67  */
  68 static void r4k_wait_irqoff(void)
  69 {
  70         local_irq_disable();
  71         if (!need_resched())
  72                 __asm__("       .set    mips3           \n"
  73                         "       wait                    \n"
  74                         "       .set    mips0           \n");
  75         local_irq_enable();
  76 }
  77
  78 /*
  79  * The RM7000 variant has to handle erratum 38.  The workaround is to not
  80  * have any pending stores when the WAIT instruction is executed.
  81  */
  82 static void rm7k_wait_irqoff(void)
  83 {
  84         local_irq_disable();
  85         if (!need_resched())
  86                 __asm__(
  87                 "       .set    push                                    \n"
  88                 "       .set    mips3                                   \n"
  89                 "       .set    noat                                    \n"
  90                 "       mfc0    $1, $12                                 \n"
  91                 "       sync                                            \n"
  92                 "       mtc0    $1, $12         # stalls until W stage  \n"
  93                 "       wait                                            \n"
  94                 "       mtc0    $1, $12         # stalls until W stage  \n"
  95                 "       .set    pop                                     \n");
  96         local_irq_enable();
  97 }
  98
  99 /* The Au1xxx wait is available only if using 32khz counter or
 100  * external timer source, but specifically not CP0 Counter. */
 101 int allow_au1k_wait;
 102
 103 static void au1k_wait(void)
 104 {
 105         /* using the wait instruction makes CP0 counter unusable */
 106         __asm__("       .set    mips3                   \n"
 107                 "       cache   0x14, 0(%0)             \n"
 108                 "       cache   0x14, 32(%0)            \n"
 109                 "       sync                            \n"
 110                 "       nop                             \n"
 111                 "       wait                            \n"
 112                 "       nop                             \n"
 113                 "       nop                             \n"
 114                 "       nop                             \n"
 115                 "       nop                             \n"
 116                 "       .set    mips0                   \n"
 117                 : : "r" (au1k_wait));
 118 }
 119
 120 static int __initdata nowait = 0;
 121
 122 static int __init wait_disable(char *s)
 123 {
 124         nowait = 1;
 125
 126         return 1;
 127 }
 128
 129 __setup("nowait", wait_disable);
 130
 131 static inline void check_wait(void)
 132 {
 133         struct cpuinfo_mips *c = &current_cpu_data;
 134
 135         if (nowait) {
 136                 printk("Wait instruction disabled.\n");
 137                 return;
 138         }
 139
 140         switch (c->cputype) {
 141         case CPU_R3081:
 142         case CPU_R3081E:
 143                 cpu_wait = r3081_wait;
 144                 break;
 145         case CPU_TX3927:
 146                 cpu_wait = r39xx_wait;
 147                 break;
 148         case CPU_R4200:
 149 /*      case CPU_R4300: */
 150         case CPU_R4600:
 151         case CPU_R4640:
 152         case CPU_R4650:
 153         case CPU_R4700:
 154         case CPU_R5000:
 155         case CPU_NEVADA:
 156         case CPU_4KC:
 157         case CPU_4KEC:
 158         case CPU_4KSC:
 159         case CPU_5KC:
 160         case CPU_25KF:
 161         case CPU_PR4450:
 162                 cpu_wait = r4k_wait;
 163                 break;
 164
 165         case CPU_RM7000:
 166                 cpu_wait = rm7k_wait_irqoff;
 167                 break;
 168
 169         case CPU_24K:
 170         case CPU_34K:
 171                 cpu_wait = r4k_wait;
 172                 if (read_c0_config7() & MIPS_CONF7_WII)
 173                         cpu_wait = r4k_wait_irqoff;
 174                 break;
 175
 176         case CPU_74K:
 177                 cpu_wait = r4k_wait;
 178                 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
 179                         cpu_wait = r4k_wait_irqoff;
 180                 break;
 181
 182         case CPU_TX49XX:
 183                 cpu_wait = r4k_wait_irqoff;
 184                 break;
 185         case CPU_AU1000:
 186         case CPU_AU1100:
 187         case CPU_AU1500:
 188         case CPU_AU1550:
 189         case CPU_AU1200:
 190                 if (allow_au1k_wait)
 191                         cpu_wait = au1k_wait;
 192                 break;
 193         case CPU_20KC:
 194                 /*
 195                  * WAIT on Rev1.0 has E1, E2, E3 and E16.
 196                  * WAIT on Rev2.0 and Rev3.0 has E16.
 197                  * Rev3.1 WAIT is nop, why bother
 198                  */
 199                 if ((c->processor_id & 0xff) <= 0x64)
 200                         break;
 201
 202                 /*
 203                  * Another rev is incremeting c0_count at a reduced clock
 204                  * rate while in WAIT mode.  So we basically have the choice
 205                  * between using the cp0 timer as clocksource or avoiding
 206                  * the WAIT instruction.  Until more details are known,
 207                  * disable the use of WAIT for 20Kc entirely.
 208                    cpu_wait = r4k_wait;
 209                  */
 210                 break;
 211         case CPU_RM9000:
 212                 if ((c->processor_id & 0x00ff) >= 0x40)
 213                         cpu_wait = r4k_wait;
 214                 break;
 215         default:
 216                 break;
 217         }
 218 }
 219
 220 static inline void check_errata(void)
 221 {
 222         struct cpuinfo_mips *c = &current_cpu_data;
 223
 224         switch (c->cputype) {
 225         case CPU_34K:
 226                 /*
 227                  * Erratum "RPS May Cause Incorrect Instruction Execution"
 228                  * This code only handles VPE0, any SMP/SMTC/RTOS code
 229                  * making use of VPE1 will be responsable for that VPE.
 230                  */
 231                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
 232                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
 233                 break;
 234         default:
 235                 break;
 236         }
 237 }
 238
 239 void __init check_bugs32(void)
 240 {
 241         check_wait();
 242         check_errata();
 243 }
 244
 245 /*
 246  * Probe whether cpu has config register by trying to play with
 247  * alternate cache bit and see whether it matters.
 248  * It's used by cpu_probe to distinguish between R3000A and R3081.
 249  */
 250 static inline int cpu_has_confreg(void)
 251 {
 252 #ifdef CONFIG_CPU_R3000
 253         extern unsigned long r3k_cache_size(unsigned long);
 254         unsigned long size1, size2;
 255         unsigned long cfg = read_c0_conf();
 256
 257         size1 = r3k_cache_size(ST0_ISC);
 258         write_c0_conf(cfg ^ R30XX_CONF_AC);
 259         size2 = r3k_cache_size(ST0_ISC);
 260         write_c0_conf(cfg);
 261         return size1 != size2;
 262 #else
 263         return 0;
 264 #endif
 265 }
 266
 267 /*
 268  * Get the FPU Implementation/Revision.
 269  */
 270 static inline unsigned long cpu_get_fpu_id(void)
 271 {
 272         unsigned long tmp, fpu_id;
 273
 274         tmp = read_c0_status();
 275         __enable_fpu();
 276         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 277         write_c0_status(tmp);
 278         return fpu_id;
 279 }
 280
 281 /*
 282  * Check the CPU has an FPU the official way.
 283  */
 284 static inline int __cpu_has_fpu(void)
 285 {
 286         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 287 }
 288
 289 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 290                 | MIPS_CPU_COUNTER)
 291
 292 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
 293 {
 294         switch (c->processor_id & 0xff00) {
 295         case PRID_IMP_R2000:
 296                 c->cputype = CPU_R2000;
 297                 c->isa_level = MIPS_CPU_ISA_I;
 298                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 299                              MIPS_CPU_NOFPUEX;
 300                 if (__cpu_has_fpu())
 301                         c->options |= MIPS_CPU_FPU;
 302                 c->tlbsize = 64;
 303                 break;
 304         case PRID_IMP_R3000:
 305                 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
 306                         if (cpu_has_confreg())
 307                                 c->cputype = CPU_R3081E;
 308                         else
 309                                 c->cputype = CPU_R3000A;
 310                 else
 311                         c->cputype = CPU_R3000;
 312                 c->isa_level = MIPS_CPU_ISA_I;
 313                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 314                              MIPS_CPU_NOFPUEX;
 315                 if (__cpu_has_fpu())
 316                         c->options |= MIPS_CPU_FPU;
 317                 c->tlbsize = 64;
 318                 break;
 319         case PRID_IMP_R4000:
 320                 if (read_c0_config() & CONF_SC) {
 321                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 322                                 c->cputype = CPU_R4400PC;
 323                         else
 324                                 c->cputype = CPU_R4000PC;
 325                 } else {
 326                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 327                                 c->cputype = CPU_R4400SC;
 328                         else
 329                                 c->cputype = CPU_R4000SC;
 330                 }
 331
 332                 c->isa_level = MIPS_CPU_ISA_III;
 333                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 334                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 335                              MIPS_CPU_LLSC;
 336                 c->tlbsize = 48;
 337                 break;
 338         case PRID_IMP_VR41XX:
 339                 switch (c->processor_id & 0xf0) {
 340                 case PRID_REV_VR4111:
 341                         c->cputype = CPU_VR4111;
 342                         break;
 343                 case PRID_REV_VR4121:
 344                         c->cputype = CPU_VR4121;
 345                         break;
 346                 case PRID_REV_VR4122:
 347                         if ((c->processor_id & 0xf) < 0x3)
 348                                 c->cputype = CPU_VR4122;
 349                         else
 350                                 c->cputype = CPU_VR4181A;
 351                         break;
 352                 case PRID_REV_VR4130:
 353                         if ((c->processor_id & 0xf) < 0x4)
 354                                 c->cputype = CPU_VR4131;
 355                         else
 356                                 c->cputype = CPU_VR4133;
 357                         break;
 358                 default:
 359                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 360                         c->cputype = CPU_VR41XX;
 361                         break;
 362                 }
 363                 c->isa_level = MIPS_CPU_ISA_III;
 364                 c->options = R4K_OPTS;
 365                 c->tlbsize = 32;
 366                 break;
 367         case PRID_IMP_R4300:
 368                 c->cputype = CPU_R4300;
 369                 c->isa_level = MIPS_CPU_ISA_III;
 370                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 371                              MIPS_CPU_LLSC;
 372                 c->tlbsize = 32;
 373                 break;
 374         case PRID_IMP_R4600:
 375                 c->cputype = CPU_R4600;
 376                 c->isa_level = MIPS_CPU_ISA_III;
 377                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 378                              MIPS_CPU_LLSC;
 379                 c->tlbsize = 48;
 380                 break;
 381         #if 0
 382         case PRID_IMP_R4650:
 383                 /*
 384                  * This processor doesn't have an MMU, so it's not
 385                  * "real easy" to run Linux on it. It is left purely
 386                  * for documentation.  Commented out because it shares
 387                  * it's c0_prid id number with the TX3900.
 388                  */
 389                 c->cputype = CPU_R4650;
 390                 c->isa_level = MIPS_CPU_ISA_III;
 391                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 392                 c->tlbsize = 48;
 393                 break;
 394         #endif
 395         case PRID_IMP_TX39:
 396                 c->isa_level = MIPS_CPU_ISA_I;
 397                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 398
 399                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 400                         c->cputype = CPU_TX3927;
 401                         c->tlbsize = 64;
 402                 } else {
 403                         switch (c->processor_id & 0xff) {
 404                         case PRID_REV_TX3912:
 405                                 c->cputype = CPU_TX3912;
 406                                 c->tlbsize = 32;
 407                                 break;
 408                         case PRID_REV_TX3922:
 409                                 c->cputype = CPU_TX3922;
 410                                 c->tlbsize = 64;
 411                                 break;
 412                         default:
 413                                 c->cputype = CPU_UNKNOWN;
 414                                 break;
 415                         }
 416                 }
 417                 break;
 418         case PRID_IMP_R4700:
 419                 c->cputype = CPU_R4700;
 420                 c->isa_level = MIPS_CPU_ISA_III;
 421                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 422                              MIPS_CPU_LLSC;
 423                 c->tlbsize = 48;
 424                 break;
 425         case PRID_IMP_TX49:
 426                 c->cputype = CPU_TX49XX;
 427                 c->isa_level = MIPS_CPU_ISA_III;
 428                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 429                 if (!(c->processor_id & 0x08))
 430                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 431                 c->tlbsize = 48;
 432                 break;
 433         case PRID_IMP_R5000:
 434                 c->cputype = CPU_R5000;
 435                 c->isa_level = MIPS_CPU_ISA_IV;
 436                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 437                              MIPS_CPU_LLSC;
 438                 c->tlbsize = 48;
 439                 break;
 440         case PRID_IMP_R5432:
 441                 c->cputype = CPU_R5432;
 442                 c->isa_level = MIPS_CPU_ISA_IV;
 443                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 444                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 445                 c->tlbsize = 48;
 446                 break;
 447         case PRID_IMP_R5500:
 448                 c->cputype = CPU_R5500;
 449                 c->isa_level = MIPS_CPU_ISA_IV;
 450                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 451                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 452                 c->tlbsize = 48;
 453                 break;
 454         case PRID_IMP_NEVADA:
 455                 c->cputype = CPU_NEVADA;
 456                 c->isa_level = MIPS_CPU_ISA_IV;
 457                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 458                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 459                 c->tlbsize = 48;
 460                 break;
 461         case PRID_IMP_R6000:
 462                 c->cputype = CPU_R6000;
 463                 c->isa_level = MIPS_CPU_ISA_II;
 464                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 465                              MIPS_CPU_LLSC;
 466                 c->tlbsize = 32;
 467                 break;
 468         case PRID_IMP_R6000A:
 469                 c->cputype = CPU_R6000A;
 470                 c->isa_level = MIPS_CPU_ISA_II;
 471                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 472                              MIPS_CPU_LLSC;
 473                 c->tlbsize = 32;
 474                 break;
 475         case PRID_IMP_RM7000:
 476                 c->cputype = CPU_RM7000;
 477                 c->isa_level = MIPS_CPU_ISA_IV;
 478                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 479                              MIPS_CPU_LLSC;
 480                 /*
 481                  * Undocumented RM7000:  Bit 29 in the info register of
 482                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 483                  * entries.
 484                  *
 485                  * 29      1 =>    64 entry JTLB
 486                  *         0 =>    48 entry JTLB
 487                  */
 488                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 489                 break;
 490         case PRID_IMP_RM9000:
 491                 c->cputype = CPU_RM9000;
 492                 c->isa_level = MIPS_CPU_ISA_IV;
 493                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 494                              MIPS_CPU_LLSC;
 495                 /*
 496                  * Bit 29 in the info register of the RM9000
 497                  * indicates if the TLB has 48 or 64 entries.
 498                  *
 499                  * 29      1 =>    64 entry JTLB
 500                  *         0 =>    48 entry JTLB
 501                  */
 502                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 503                 break;
 504         case PRID_IMP_R8000:
 505                 c->cputype = CPU_R8000;
 506                 c->isa_level = MIPS_CPU_ISA_IV;
 507                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 508                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 509                              MIPS_CPU_LLSC;
 510                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 511                 break;
 512         case PRID_IMP_R10000:
 513                 c->cputype = CPU_R10000;
 514                 c->isa_level = MIPS_CPU_ISA_IV;
 515                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 516                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 517                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 518                              MIPS_CPU_LLSC;
 519                 c->tlbsize = 64;
 520                 break;
 521         case PRID_IMP_R12000:
 522                 c->cputype = CPU_R12000;
 523                 c->isa_level = MIPS_CPU_ISA_IV;
 524                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 525                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 526                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 527                              MIPS_CPU_LLSC;
 528                 c->tlbsize = 64;
 529                 break;
 530         case PRID_IMP_R14000:
 531                 c->cputype = CPU_R14000;
 532                 c->isa_level = MIPS_CPU_ISA_IV;
 533                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 534                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 535                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 536                              MIPS_CPU_LLSC;
 537                 c->tlbsize = 64;
 538                 break;
 539         case PRID_IMP_LOONGSON2:
 540                 c->cputype = CPU_LOONGSON2;
 541                 c->isa_level = MIPS_CPU_ISA_III;
 542                 c->options = R4K_OPTS |
 543                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
 544                              MIPS_CPU_32FPR;
 545                 c->tlbsize = 64;
 546                 break;
 547         }
 548 }
 549
 550 static char unknown_isa[] __initdata = KERN_ERR \
 551         "Unsupported ISA type, c0.config0: %d.";
 552
 553 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 554 {
 555         unsigned int config0;
 556         int isa;
 557
 558         config0 = read_c0_config();
 559
 560         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
 561                 c->options |= MIPS_CPU_TLB;
 562         isa = (config0 & MIPS_CONF_AT) >> 13;
 563         switch (isa) {
 564         case 0:
 565                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 566                 case 0:
 567                         c->isa_level = MIPS_CPU_ISA_M32R1;
 568                         break;
 569                 case 1:
 570                         c->isa_level = MIPS_CPU_ISA_M32R2;
 571                         break;
 572                 default:
 573                         goto unknown;
 574                 }
 575                 break;
 576         case 2:
 577                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 578                 case 0:
 579                         c->isa_level = MIPS_CPU_ISA_M64R1;
 580                         break;
 581                 case 1:
 582                         c->isa_level = MIPS_CPU_ISA_M64R2;
 583                         break;
 584                 default:
 585                         goto unknown;
 586                 }
 587                 break;
 588         default:
 589                 goto unknown;
 590         }
 591
 592         return config0 & MIPS_CONF_M;
 593
 594 unknown:
 595         panic(unknown_isa, config0);
 596 }
 597
 598 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 599 {
 600         unsigned int config1;
 601
 602         config1 = read_c0_config1();
 603
 604         if (config1 & MIPS_CONF1_MD)
 605                 c->ases |= MIPS_ASE_MDMX;
 606         if (config1 & MIPS_CONF1_WR)
 607                 c->options |= MIPS_CPU_WATCH;
 608         if (config1 & MIPS_CONF1_CA)
 609                 c->ases |= MIPS_ASE_MIPS16;
 610         if (config1 & MIPS_CONF1_EP)
 611                 c->options |= MIPS_CPU_EJTAG;
 612         if (config1 & MIPS_CONF1_FP) {
 613                 c->options |= MIPS_CPU_FPU;
 614                 c->options |= MIPS_CPU_32FPR;
 615         }
 616         if (cpu_has_tlb)
 617                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 618
 619         return config1 & MIPS_CONF_M;
 620 }
 621
 622 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 623 {
 624         unsigned int config2;
 625
 626         config2 = read_c0_config2();
 627
 628         if (config2 & MIPS_CONF2_SL)
 629                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 630
 631         return config2 & MIPS_CONF_M;
 632 }
 633
 634 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 635 {
 636         unsigned int config3;
 637
 638         config3 = read_c0_config3();
 639
 640         if (config3 & MIPS_CONF3_SM)
 641                 c->ases |= MIPS_ASE_SMARTMIPS;
 642         if (config3 & MIPS_CONF3_DSP)
 643                 c->ases |= MIPS_ASE_DSP;
 644         if (config3 & MIPS_CONF3_VINT)
 645                 c->options |= MIPS_CPU_VINT;
 646         if (config3 & MIPS_CONF3_VEIC)
 647                 c->options |= MIPS_CPU_VEIC;
 648         if (config3 & MIPS_CONF3_MT)
 649                 c->ases |= MIPS_ASE_MIPSMT;
 650         if (config3 & MIPS_CONF3_ULRI)
 651                 c->options |= MIPS_CPU_ULRI;
 652
 653         return config3 & MIPS_CONF_M;
 654 }
 655
 656 static void __init decode_configs(struct cpuinfo_mips *c)
 657 {
 658         /* MIPS32 or MIPS64 compliant CPU.  */
 659         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 660                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 661
 662         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 663
 664         /* Read Config registers.  */
 665         if (!decode_config0(c))
 666                 return;                 /* actually worth a panic() */
 667         if (!decode_config1(c))
 668                 return;
 669         if (!decode_config2(c))
 670                 return;
 671         if (!decode_config3(c))
 672                 return;
 673 }
 674
 675 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
 676 {
 677         decode_configs(c);
 678         switch (c->processor_id & 0xff00) {
 679         case PRID_IMP_4KC:
 680                 c->cputype = CPU_4KC;
 681                 break;
 682         case PRID_IMP_4KEC:
 683                 c->cputype = CPU_4KEC;
 684                 break;
 685         case PRID_IMP_4KECR2:
 686                 c->cputype = CPU_4KEC;
 687                 break;
 688         case PRID_IMP_4KSC:
 689         case PRID_IMP_4KSD:
 690                 c->cputype = CPU_4KSC;
 691                 break;
 692         case PRID_IMP_5KC:
 693                 c->cputype = CPU_5KC;
 694                 break;
 695         case PRID_IMP_20KC:
 696                 c->cputype = CPU_20KC;
 697                 break;
 698         case PRID_IMP_24K:
 699         case PRID_IMP_24KE:
 700                 c->cputype = CPU_24K;
 701                 break;
 702         case PRID_IMP_25KF:
 703                 c->cputype = CPU_25KF;
 704                 break;
 705         case PRID_IMP_34K:
 706                 c->cputype = CPU_34K;
 707                 break;
 708         case PRID_IMP_74K:
 709                 c->cputype = CPU_74K;
 710                 break;
 711         }
 712 }
 713
 714 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
 715 {
 716         decode_configs(c);
 717         switch (c->processor_id & 0xff00) {
 718         case PRID_IMP_AU1_REV1:
 719         case PRID_IMP_AU1_REV2:
 720                 switch ((c->processor_id >> 24) & 0xff) {
 721                 case 0:
 722                         c->cputype = CPU_AU1000;
 723                         break;
 724                 case 1:
 725                         c->cputype = CPU_AU1500;
 726                         break;
 727                 case 2:
 728                         c->cputype = CPU_AU1100;
 729                         break;
 730                 case 3:
 731                         c->cputype = CPU_AU1550;
 732                         break;
 733                 case 4:
 734                         c->cputype = CPU_AU1200;
 735                         break;
 736                 default:
 737                         panic("Unknown Au Core!");
 738                         break;
 739                 }
 740                 break;
 741         }
 742 }
 743
 744 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
 745 {
 746         decode_configs(c);
 747
 748         /*
 749          * For historical reasons the SB1 comes with it's own variant of
 750          * cache code which eventually will be folded into c-r4k.c.  Until
 751          * then we pretend it's got it's own cache architecture.
 752          */
 753         c->options &= ~MIPS_CPU_4K_CACHE;
 754         c->options |= MIPS_CPU_SB1_CACHE;
 755
 756         switch (c->processor_id & 0xff00) {
 757         case PRID_IMP_SB1:
 758                 c->cputype = CPU_SB1;
 759                 /* FPU in pass1 is known to have issues. */
 760                 if ((c->processor_id & 0xff) < 0x02)
 761                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 762                 break;
 763         case PRID_IMP_SB1A:
 764                 c->cputype = CPU_SB1A;
 765                 break;
 766         }
 767 }
 768
 769 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
 770 {
 771         decode_configs(c);
 772         switch (c->processor_id & 0xff00) {
 773         case PRID_IMP_SR71000:
 774                 c->cputype = CPU_SR71000;
 775                 c->scache.ways = 8;
 776                 c->tlbsize = 64;
 777                 break;
 778         }
 779 }
 780
 781 static inline void cpu_probe_philips(struct cpuinfo_mips *c)
 782 {
 783         decode_configs(c);
 784         switch (c->processor_id & 0xff00) {
 785         case PRID_IMP_PR4450:
 786                 c->cputype = CPU_PR4450;
 787                 c->isa_level = MIPS_CPU_ISA_M32R1;
 788                 break;
 789         default:
 790                 panic("Unknown Philips Core!"); /* REVISIT: die? */
 791                 break;
 792         }
 793 }
 794
 795
 796 __init void cpu_probe(void)
 797 {
 798         struct cpuinfo_mips *c = &current_cpu_data;
 799
 800         c->processor_id = PRID_IMP_UNKNOWN;
 801         c->fpu_id       = FPIR_IMP_NONE;
 802         c->cputype      = CPU_UNKNOWN;
 803
 804         c->processor_id = read_c0_prid();
 805         switch (c->processor_id & 0xff0000) {
 806         case PRID_COMP_LEGACY:
 807                 cpu_probe_legacy(c);
 808                 break;
 809         case PRID_COMP_MIPS:
 810                 cpu_probe_mips(c);
 811                 break;
 812         case PRID_COMP_ALCHEMY:
 813                 cpu_probe_alchemy(c);
 814                 break;
 815         case PRID_COMP_SIBYTE:
 816                 cpu_probe_sibyte(c);
 817                 break;
 818         case PRID_COMP_SANDCRAFT:
 819                 cpu_probe_sandcraft(c);
 820                 break;
 821         case PRID_COMP_PHILIPS:
 822                 cpu_probe_philips(c);
 823                 break;
 824         default:
 825                 c->cputype = CPU_UNKNOWN;
 826         }
 827         if (c->options & MIPS_CPU_FPU) {
 828                 c->fpu_id = cpu_get_fpu_id();
 829
 830                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
 831                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
 832                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
 833                     c->isa_level == MIPS_CPU_ISA_M64R2) {
 834                         if (c->fpu_id & MIPS_FPIR_3D)
 835                                 c->ases |= MIPS_ASE_MIPS3D;
 836                 }
 837         }
 838 }
 839
 840 __init void cpu_report(void)
 841 {
 842         struct cpuinfo_mips *c = &current_cpu_data;
 843
 844         printk("CPU revision is: %08x\n", c->processor_id);
 845         if (c->options & MIPS_CPU_FPU)
 846                 printk("FPU revision is: %08x\n", c->fpu_id);
 847 }