2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 2003, 2004 Maciej W. Rozycki
6 * Copyright (C) 1994 - 2003 Ralf Baechle
7 * Copyright (C) 2001, 2004 MIPS Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/config.h>
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/ptrace.h>
18 #include <linux/stddef.h>
22 #include <asm/mipsregs.h>
23 #include <asm/system.h>
26 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
27 * the implementation of the "wait" feature differs between CPU families. This
28 * points to the function that implements CPU specific wait.
29 * The wait instruction stops the pipeline and reduces the power consumption of
32 void (*cpu_wait)(void) = NULL;
34 static void r3081_wait(void)
36 unsigned long cfg = read_c0_conf();
37 write_c0_conf(cfg | R30XX_CONF_HALT);
40 static void r39xx_wait(void)
42 unsigned long cfg = read_c0_conf();
43 write_c0_conf(cfg | TX39_CONF_HALT);
46 static void r4k_wait(void)
48 __asm__(".set\tmips3\n\t"
53 /* The Au1xxx wait is available only if using 32khz counter or
54 * external timer source, but specifically not CP0 Counter. */
57 static void au1k_wait(void)
59 /* using the wait instruction makes CP0 counter unusable */
60 __asm__(".set mips3\n\t"
61 "cache 0x14, 0(%0)\n\t"
62 "cache 0x14, 32(%0)\n\t"
74 static inline void check_wait(void)
76 struct cpuinfo_mips *c = ¤t_cpu_data;
78 printk("Checking for 'wait' instruction... ");
82 cpu_wait = r3081_wait;
83 printk(" available.\n");
86 cpu_wait = r39xx_wait;
87 printk(" available.\n");
108 printk(" available.\n");
115 if (allow_au1k_wait) {
116 cpu_wait = au1k_wait;
117 printk(" available.\n");
119 printk(" unavailable.\n");
122 printk(" unavailable.\n");
127 void __init check_bugs32(void)
133 * Probe whether cpu has config register by trying to play with
134 * alternate cache bit and see whether it matters.
135 * It's used by cpu_probe to distinguish between R3000A and R3081.
137 static inline int cpu_has_confreg(void)
139 #ifdef CONFIG_CPU_R3000
140 extern unsigned long r3k_cache_size(unsigned long);
141 unsigned long size1, size2;
142 unsigned long cfg = read_c0_conf();
144 size1 = r3k_cache_size(ST0_ISC);
145 write_c0_conf(cfg ^ R30XX_CONF_AC);
146 size2 = r3k_cache_size(ST0_ISC);
148 return size1 != size2;
155 * Get the FPU Implementation/Revision.
157 static inline unsigned long cpu_get_fpu_id(void)
159 unsigned long tmp, fpu_id;
161 tmp = read_c0_status();
163 fpu_id = read_32bit_cp1_register(CP1_REVISION);
164 write_c0_status(tmp);
169 * Check the CPU has an FPU the official way.
171 static inline int __cpu_has_fpu(void)
173 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
176 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
179 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
181 switch (c->processor_id & 0xff00) {
183 c->cputype = CPU_R2000;
184 c->isa_level = MIPS_CPU_ISA_I;
185 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
187 c->options |= MIPS_CPU_FPU;
191 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
192 if (cpu_has_confreg())
193 c->cputype = CPU_R3081E;
195 c->cputype = CPU_R3000A;
197 c->cputype = CPU_R3000;
198 c->isa_level = MIPS_CPU_ISA_I;
199 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
201 c->options |= MIPS_CPU_FPU;
205 if (read_c0_config() & CONF_SC) {
206 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
207 c->cputype = CPU_R4400PC;
209 c->cputype = CPU_R4000PC;
211 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
212 c->cputype = CPU_R4400SC;
214 c->cputype = CPU_R4000SC;
217 c->isa_level = MIPS_CPU_ISA_III;
218 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
219 MIPS_CPU_WATCH | MIPS_CPU_VCE |
223 case PRID_IMP_VR41XX:
224 switch (c->processor_id & 0xf0) {
225 case PRID_REV_VR4111:
226 c->cputype = CPU_VR4111;
228 case PRID_REV_VR4121:
229 c->cputype = CPU_VR4121;
231 case PRID_REV_VR4122:
232 if ((c->processor_id & 0xf) < 0x3)
233 c->cputype = CPU_VR4122;
235 c->cputype = CPU_VR4181A;
237 case PRID_REV_VR4130:
238 if ((c->processor_id & 0xf) < 0x4)
239 c->cputype = CPU_VR4131;
241 c->cputype = CPU_VR4133;
244 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
245 c->cputype = CPU_VR41XX;
248 c->isa_level = MIPS_CPU_ISA_III;
249 c->options = R4K_OPTS;
253 c->cputype = CPU_R4300;
254 c->isa_level = MIPS_CPU_ISA_III;
255 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
260 c->cputype = CPU_R4600;
261 c->isa_level = MIPS_CPU_ISA_III;
262 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
268 * This processor doesn't have an MMU, so it's not
269 * "real easy" to run Linux on it. It is left purely
270 * for documentation. Commented out because it shares
271 * it's c0_prid id number with the TX3900.
273 c->cputype = CPU_R4650;
274 c->isa_level = MIPS_CPU_ISA_III;
275 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
280 c->isa_level = MIPS_CPU_ISA_I;
281 c->options = MIPS_CPU_TLB;
283 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
284 c->cputype = CPU_TX3927;
287 switch (c->processor_id & 0xff) {
288 case PRID_REV_TX3912:
289 c->cputype = CPU_TX3912;
292 case PRID_REV_TX3922:
293 c->cputype = CPU_TX3922;
297 c->cputype = CPU_UNKNOWN;
303 c->cputype = CPU_R4700;
304 c->isa_level = MIPS_CPU_ISA_III;
305 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
310 c->cputype = CPU_TX49XX;
311 c->isa_level = MIPS_CPU_ISA_III;
312 c->options = R4K_OPTS | MIPS_CPU_LLSC;
313 if (!(c->processor_id & 0x08))
314 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
318 c->cputype = CPU_R5000;
319 c->isa_level = MIPS_CPU_ISA_IV;
320 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
325 c->cputype = CPU_R5432;
326 c->isa_level = MIPS_CPU_ISA_IV;
327 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
328 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
332 c->cputype = CPU_R5500;
333 c->isa_level = MIPS_CPU_ISA_IV;
334 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
335 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
338 case PRID_IMP_NEVADA:
339 c->cputype = CPU_NEVADA;
340 c->isa_level = MIPS_CPU_ISA_IV;
341 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
342 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
346 c->cputype = CPU_R6000;
347 c->isa_level = MIPS_CPU_ISA_II;
348 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
352 case PRID_IMP_R6000A:
353 c->cputype = CPU_R6000A;
354 c->isa_level = MIPS_CPU_ISA_II;
355 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
359 case PRID_IMP_RM7000:
360 c->cputype = CPU_RM7000;
361 c->isa_level = MIPS_CPU_ISA_IV;
362 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
365 * Undocumented RM7000: Bit 29 in the info register of
366 * the RM7000 v2.0 indicates if the TLB has 48 or 64
369 * 29 1 => 64 entry JTLB
372 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
374 case PRID_IMP_RM9000:
375 c->cputype = CPU_RM9000;
376 c->isa_level = MIPS_CPU_ISA_IV;
377 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
380 * Bit 29 in the info register of the RM9000
381 * indicates if the TLB has 48 or 64 entries.
383 * 29 1 => 64 entry JTLB
386 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
389 c->cputype = CPU_R8000;
390 c->isa_level = MIPS_CPU_ISA_IV;
391 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
392 MIPS_CPU_FPU | MIPS_CPU_32FPR |
394 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
396 case PRID_IMP_R10000:
397 c->cputype = CPU_R10000;
398 c->isa_level = MIPS_CPU_ISA_IV;
399 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
400 MIPS_CPU_FPU | MIPS_CPU_32FPR |
401 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
405 case PRID_IMP_R12000:
406 c->cputype = CPU_R12000;
407 c->isa_level = MIPS_CPU_ISA_IV;
408 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
409 MIPS_CPU_FPU | MIPS_CPU_32FPR |
410 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
417 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
419 unsigned int config0;
422 config0 = read_c0_config();
424 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
425 c->options |= MIPS_CPU_TLB | MIPS_CPU_4KTLB;
426 isa = (config0 & MIPS_CONF_AT) >> 13;
429 c->isa_level = MIPS_CPU_ISA_M32;
432 c->isa_level = MIPS_CPU_ISA_M64;
435 panic("Unsupported ISA type, cp0.config0.at: %d.", isa);
438 return config0 & MIPS_CONF_M;
441 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
443 unsigned int config1;
445 config1 = read_c0_config1();
447 if (config1 & MIPS_CONF1_MD)
448 c->ases |= MIPS_ASE_MDMX;
449 if (config1 & MIPS_CONF1_WR)
450 c->options |= MIPS_CPU_WATCH;
451 if (config1 & MIPS_CONF1_CA)
452 c->ases |= MIPS_ASE_MIPS16;
453 if (config1 & MIPS_CONF1_EP)
454 c->options |= MIPS_CPU_EJTAG;
455 if (config1 & MIPS_CONF1_FP) {
456 c->options |= MIPS_CPU_FPU;
457 c->options |= MIPS_CPU_32FPR;
460 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
462 return config1 & MIPS_CONF_M;
465 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
467 unsigned int config2;
469 config2 = read_c0_config2();
471 if (config2 & MIPS_CONF2_SL)
472 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
474 return config2 & MIPS_CONF_M;
477 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
479 unsigned int config3;
481 config3 = read_c0_config3();
483 if (config3 & MIPS_CONF3_SM)
484 c->ases |= MIPS_ASE_SMARTMIPS;
485 if (config3 & MIPS_CONF3_DSP)
486 c->ases |= MIPS_ASE_DSP;
488 return config3 & MIPS_CONF_M;
491 static inline void decode_configs(struct cpuinfo_mips *c)
493 /* MIPS32 or MIPS64 compliant CPU. */
494 c->options = MIPS_CPU_4KEX | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
495 MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
497 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
499 /* Read Config registers. */
500 if (!decode_config0(c))
501 return; /* actually worth a panic() */
502 if (!decode_config1(c))
504 if (!decode_config2(c))
506 if (!decode_config3(c))
510 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
513 switch (c->processor_id & 0xff00) {
515 c->cputype = CPU_4KC;
518 c->cputype = CPU_4KEC;
520 case PRID_IMP_4KECR2:
521 c->cputype = CPU_4KEC;
524 c->cputype = CPU_4KSC;
527 c->cputype = CPU_5KC;
530 c->cputype = CPU_20KC;
534 c->cputype = CPU_24K;
537 c->cputype = CPU_25KF;
538 /* Probe for L2 cache */
539 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
544 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
547 switch (c->processor_id & 0xff00) {
548 case PRID_IMP_AU1_REV1:
549 case PRID_IMP_AU1_REV2:
550 switch ((c->processor_id >> 24) & 0xff) {
552 c->cputype = CPU_AU1000;
555 c->cputype = CPU_AU1500;
558 c->cputype = CPU_AU1100;
561 c->cputype = CPU_AU1550;
564 c->cputype = CPU_AU1200;
567 panic("Unknown Au Core!");
574 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
577 switch (c->processor_id & 0xff00) {
579 c->cputype = CPU_SB1;
580 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
581 /* FPU in pass1 is known to have issues. */
582 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
588 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
591 switch (c->processor_id & 0xff00) {
592 case PRID_IMP_SR71000:
593 c->cputype = CPU_SR71000;
600 __init void cpu_probe(void)
602 struct cpuinfo_mips *c = ¤t_cpu_data;
604 c->processor_id = PRID_IMP_UNKNOWN;
605 c->fpu_id = FPIR_IMP_NONE;
606 c->cputype = CPU_UNKNOWN;
608 c->processor_id = read_c0_prid();
609 switch (c->processor_id & 0xff0000) {
610 case PRID_COMP_LEGACY:
616 case PRID_COMP_ALCHEMY:
617 cpu_probe_alchemy(c);
619 case PRID_COMP_SIBYTE:
622 case PRID_COMP_SANDCRAFT:
623 cpu_probe_sandcraft(c);
626 c->cputype = CPU_UNKNOWN;
628 if (c->options & MIPS_CPU_FPU) {
629 c->fpu_id = cpu_get_fpu_id();
631 if (c->isa_level == MIPS_CPU_ISA_M32 ||
632 c->isa_level == MIPS_CPU_ISA_M64) {
633 if (c->fpu_id & MIPS_FPIR_3D)
634 c->ases |= MIPS_ASE_MIPS3D;
639 __init void cpu_report(void)
641 struct cpuinfo_mips *c = ¤t_cpu_data;
643 printk("CPU revision is: %08x\n", c->processor_id);
644 if (c->options & MIPS_CPU_FPU)
645 printk("FPU revision is: %08x\n", c->fpu_id);