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   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
   7  * Copyright (C) 1996 by Paul M. Antoine
   8  * Copyright (C) 1999 Silicon Graphics
   9  * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000 MIPS Technologies, Inc.
  11  */
  12 #ifndef _ASM_SYSTEM_H
  13 #define _ASM_SYSTEM_H
  14
  15 #include <linux/types.h>
  16 #include <linux/irqflags.h>
  17
  18 #include <asm/addrspace.h>
  19 #include <asm/barrier.h>
  20 #include <asm/cmpxchg.h>
  21 #include <asm/cpu-features.h>
  22 #include <asm/dsp.h>
  23 #include <asm/watch.h>
  24 #include <asm/war.h>
  25
  26
  27 /*
  28  * switch_to(n) should switch tasks to task nr n, first
  29  * checking that n isn't the current task, in which case it does nothing.
  30  */
  31 extern asmlinkage void *resume(void *last, void *next, void *next_ti);
  32
  33 struct task_struct;
  34
  35 #ifdef CONFIG_MIPS_MT_FPAFF
  36
  37 /*
  38  * Handle the scheduler resume end of FPU affinity management.  We do this
  39  * inline to try to keep the overhead down. If we have been forced to run on
  40  * a "CPU" with an FPU because of a previous high level of FP computation,
  41  * but did not actually use the FPU during the most recent time-slice (CU1
  42  * isn't set), we undo the restriction on cpus_allowed.
  43  *
  44  * We're not calling set_cpus_allowed() here, because we have no need to
  45  * force prompt migration - we're already switching the current CPU to a
  46  * different thread.
  47  */
  48
  49 #define __mips_mt_fpaff_switch_to(prev)                                 \
  50 do {                                                                    \
  51         struct thread_info *__prev_ti = task_thread_info(prev);         \
  52                                                                         \
  53         if (cpu_has_fpu &&                                              \
  54             test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) &&             \
  55             (!(KSTK_STATUS(prev) & ST0_CU1))) {                         \
  56                 clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND);          \
  57                 prev->cpus_allowed = prev->thread.user_cpus_allowed;    \
  58         }                                                               \
  59         next->thread.emulated_fp = 0;                                   \
  60 } while(0)
  61
  62 #else
  63 #define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
  64 #endif
  65
  66 #ifdef CONFIG_CPU_HAS_LLSC
  67 #define __clear_software_ll_bit() do { } while (0)
  68 #else
  69 extern unsigned long ll_bit;
  70
  71 #define __clear_software_ll_bit()                                       \
  72 do {                                                                    \
  73         ll_bit = 0;                                                     \
  74 } while (0)
  75 #endif
  76
  77 #define switch_to(prev, next, last)                                     \
  78 do {                                                                    \
  79         __mips_mt_fpaff_switch_to(prev);                                \
  80         if (cpu_has_dsp)                                                \
  81                 __save_dsp(prev);                                       \
  82         __clear_software_ll_bit();                                      \
  83         (last) = resume(prev, next, task_thread_info(next));            \
  84 } while (0)
  85
  86 #define finish_arch_switch(prev)                                        \
  87 do {                                                                    \
  88         if (cpu_has_dsp)                                                \
  89                 __restore_dsp(current);                                 \
  90         if (cpu_has_userlocal)                                          \
  91                 write_c0_userlocal(current_thread_info()->tp_value);    \
  92         __restore_watch();                                              \
  93 } while (0)
  94
  95 static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
  96 {
  97         __u32 retval;
  98
  99         if (cpu_has_llsc && R10000_LLSC_WAR) {
 100                 unsigned long dummy;
 101
 102                 __asm__ __volatile__(
 103                 "       .set    mips3                                   \n"
 104                 "1:     ll      %0, %3                  # xchg_u32      \n"
 105                 "       .set    mips0                                   \n"
 106                 "       move    %2, %z4                                 \n"
 107                 "       .set    mips3                                   \n"
 108                 "       sc      %2, %1                                  \n"
 109                 "       beqzl   %2, 1b                                  \n"
 110                 "       .set    mips0                                   \n"
 111                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 112                 : "R" (*m), "Jr" (val)
 113                 : "memory");
 114         } else if (cpu_has_llsc) {
 115                 unsigned long dummy;
 116
 117                 __asm__ __volatile__(
 118                 "       .set    mips3                                   \n"
 119                 "1:     ll      %0, %3                  # xchg_u32      \n"
 120                 "       .set    mips0                                   \n"
 121                 "       move    %2, %z4                                 \n"
 122                 "       .set    mips3                                   \n"
 123                 "       sc      %2, %1                                  \n"
 124                 "       beqz    %2, 2f                                  \n"
 125                 "       .subsection 2                                   \n"
 126                 "2:     b       1b                                      \n"
 127                 "       .previous                                       \n"
 128                 "       .set    mips0                                   \n"
 129                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 130                 : "R" (*m), "Jr" (val)
 131                 : "memory");
 132         } else {
 133                 unsigned long flags;
 134
 135                 raw_local_irq_save(flags);
 136                 retval = *m;
 137                 *m = val;
 138                 raw_local_irq_restore(flags);   /* implies memory barrier  */
 139         }
 140
 141         smp_llsc_mb();
 142
 143         return retval;
 144 }
 145
 146 #ifdef CONFIG_64BIT
 147 static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
 148 {
 149         __u64 retval;
 150
 151         if (cpu_has_llsc && R10000_LLSC_WAR) {
 152                 unsigned long dummy;
 153
 154                 __asm__ __volatile__(
 155                 "       .set    mips3                                   \n"
 156                 "1:     lld     %0, %3                  # xchg_u64      \n"
 157                 "       move    %2, %z4                                 \n"
 158                 "       scd     %2, %1                                  \n"
 159                 "       beqzl   %2, 1b                                  \n"
 160                 "       .set    mips0                                   \n"
 161                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 162                 : "R" (*m), "Jr" (val)
 163                 : "memory");
 164         } else if (cpu_has_llsc) {
 165                 unsigned long dummy;
 166
 167                 __asm__ __volatile__(
 168                 "       .set    mips3                                   \n"
 169                 "1:     lld     %0, %3                  # xchg_u64      \n"
 170                 "       move    %2, %z4                                 \n"
 171                 "       scd     %2, %1                                  \n"
 172                 "       beqz    %2, 2f                                  \n"
 173                 "       .subsection 2                                   \n"
 174                 "2:     b       1b                                      \n"
 175                 "       .previous                                       \n"
 176                 "       .set    mips0                                   \n"
 177                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 178                 : "R" (*m), "Jr" (val)
 179                 : "memory");
 180         } else {
 181                 unsigned long flags;
 182
 183                 raw_local_irq_save(flags);
 184                 retval = *m;
 185                 *m = val;
 186                 raw_local_irq_restore(flags);   /* implies memory barrier  */
 187         }
 188
 189         smp_llsc_mb();
 190
 191         return retval;
 192 }
 193 #else
 194 extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
 195 #define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
 196 #endif
 197
 198 /* This function doesn't exist, so you'll get a linker error
 199    if something tries to do an invalid xchg().  */
 200 extern void __xchg_called_with_bad_pointer(void);
 201
 202 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 203 {
 204         switch (size) {
 205         case 4:
 206                 return __xchg_u32(ptr, x);
 207         case 8:
 208                 return __xchg_u64(ptr, x);
 209         }
 210         __xchg_called_with_bad_pointer();
 211         return x;
 212 }
 213
 214 #define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
 215
 216 extern void set_handler(unsigned long offset, void *addr, unsigned long len);
 217 extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
 218
 219 typedef void (*vi_handler_t)(void);
 220 extern void *set_vi_handler(int n, vi_handler_t addr);
 221
 222 extern void *set_except_vector(int n, void *addr);
 223 extern unsigned long ebase;
 224 extern void per_cpu_trap_init(void);
 225
 226 /*
 227  * See include/asm-ia64/system.h; prevents deadlock on SMP
 228  * systems.
 229  */
 230 #define __ARCH_WANT_UNLOCKED_CTXSW
 231
 232 extern unsigned long arch_align_stack(unsigned long sp);
 233
 234 #endif /* _ASM_SYSTEM_H */