2 * Copyright (C) 2009 Lemote, Inc.
3 * Author: Wu Zhangjin <wuzj@lemote.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
12 #ifndef __ASM_MACH_LOONGSON_LOONGSON_H
13 #define __ASM_MACH_LOONGSON_LOONGSON_H
16 #include <linux/init.h>
18 /* loongson internal northbridge initialization */
19 extern void bonito_irq_init(void);
21 /* machine-specific reboot/halt operation */
22 extern void mach_prepare_reboot(void);
23 extern void mach_prepare_shutdown(void);
25 /* environment arguments from bootloader */
26 extern unsigned long bus_clock, cpu_clock_freq;
27 extern unsigned long memsize, highmemsize;
29 /* loongson-specific command line, env and memory initialization */
30 extern void __init prom_init_memory(void);
31 extern void __init prom_init_cmdline(void);
32 extern void __init prom_init_machtype(void);
33 extern void __init prom_init_env(void);
34 #ifdef CONFIG_LOONGSON_UART_BASE
35 extern unsigned long _loongson_uart_base, loongson_uart_base;
36 extern void prom_init_loongson_uart_base(void);
39 static inline void prom_init_uart_base(void)
41 #ifdef CONFIG_LOONGSON_UART_BASE
42 prom_init_loongson_uart_base();
46 /* irq operation functions */
47 extern void bonito_irqdispatch(void);
48 extern void __init bonito_irq_init(void);
49 extern void __init set_irq_trigger_mode(void);
50 extern void __init mach_init_irq(void);
51 extern void mach_irq_dispatch(unsigned int pending);
52 extern int mach_i8259_irq(void);
54 /* We need this in some places... */
57 for (x = 0; x < 100000; x++) \
58 __asm__ __volatile__(""); \
61 #define LOONGSON_REG(x) \
62 (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
64 #define LOONGSON_IRQ_BASE 32
65 #define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
67 #define LOONGSON_FLASH_BASE 0x1c000000
68 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
69 #define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
71 #define LOONGSON_LIO0_BASE 0x1e000000
72 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
73 #define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
75 #define LOONGSON_BOOT_BASE 0x1fc00000
76 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
77 #define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
78 #define LOONGSON_REG_BASE 0x1fe00000
79 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
80 #define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
82 #define LOONGSON_LIO1_BASE 0x1ff00000
83 #define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */
84 #define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
86 #define LOONGSON_PCILO0_BASE 0x10000000
87 #define LOONGSON_PCILO1_BASE 0x14000000
88 #define LOONGSON_PCILO2_BASE 0x18000000
89 #define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE
90 #define LOONGSON_PCILO_SIZE 0x0c000000 /* 64M * 3 */
91 #define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
93 #define LOONGSON_PCICFG_BASE 0x1fe80000
94 #define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */
95 #define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
96 #define LOONGSON_PCIIO_BASE 0x1fd00000
97 #define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */
98 #define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
100 /* Loongson Register Bases */
102 #define LOONGSON_PCICONFIGBASE 0x00
103 #define LOONGSON_REGBASE 0x100
105 /* PCI Configuration Registers */
107 #define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
108 #define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00)
109 #define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04)
110 #define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08)
111 #define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c)
112 #define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10)
113 #define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14)
114 #define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18)
115 #define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c)
116 #define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20)
117 #define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30)
118 #define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c)
120 #define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c)
122 #define LOONGSON_PCICMD_PERR_CLR 0x80000000
123 #define LOONGSON_PCICMD_SERR_CLR 0x40000000
124 #define LOONGSON_PCICMD_MABORT_CLR 0x20000000
125 #define LOONGSON_PCICMD_MTABORT_CLR 0x10000000
126 #define LOONGSON_PCICMD_TABORT_CLR 0x08000000
127 #define LOONGSON_PCICMD_MPERR_CLR 0x01000000
128 #define LOONGSON_PCICMD_PERRRESPEN 0x00000040
129 #define LOONGSON_PCICMD_ASTEPEN 0x00000080
130 #define LOONGSON_PCICMD_SERREN 0x00000100
131 #define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00
132 #define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8
134 /* Loongson h/w Configuration */
136 #define LOONGSON_GENCFG_OFFSET 0x4
137 #define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
139 #define LOONGSON_GENCFG_DEBUGMODE 0x00000001
140 #define LOONGSON_GENCFG_SNOOPEN 0x00000002
141 #define LOONGSON_GENCFG_CPUSELFRESET 0x00000004
143 #define LOONGSON_GENCFG_FORCE_IRQA 0x00000008
144 #define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010
145 #define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020
146 #define LOONGSON_GENCFG_BYTESWAP 0x00000040
148 #define LOONGSON_GENCFG_UNCACHED 0x00000080
149 #define LOONGSON_GENCFG_PREFETCHEN 0x00000100
150 #define LOONGSON_GENCFG_WBEHINDEN 0x00000200
151 #define LOONGSON_GENCFG_CACHEALG 0x00000c00
152 #define LOONGSON_GENCFG_CACHEALG_SHIFT 10
153 #define LOONGSON_GENCFG_PCIQUEUE 0x00001000
154 #define LOONGSON_GENCFG_CACHESTOP 0x00002000
155 #define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000
156 #define LOONGSON_GENCFG_BUSERREN 0x00008000
157 #define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000
158 #define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000
160 /* PCI address map control */
162 #define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10)
163 #define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14)
164 #define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18)
166 /* GPIO Regs - r/w */
168 #define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
169 #define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20)
171 /* ICU Configuration Regs - r/w */
173 #define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24)
174 #define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28)
175 #define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
177 /* ICU Enable Regs - IntEn & IntISR are r/o. */
179 #define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30)
180 #define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34)
181 #define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38)
182 #define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
185 #define LOONGSON_ICU_MBOXES 0x0000000f
186 #define LOONGSON_ICU_MBOXES_SHIFT 0
187 #define LOONGSON_ICU_DMARDY 0x00000010
188 #define LOONGSON_ICU_DMAEMPTY 0x00000020
189 #define LOONGSON_ICU_COPYRDY 0x00000040
190 #define LOONGSON_ICU_COPYEMPTY 0x00000080
191 #define LOONGSON_ICU_COPYERR 0x00000100
192 #define LOONGSON_ICU_PCIIRQ 0x00000200
193 #define LOONGSON_ICU_MASTERERR 0x00000400
194 #define LOONGSON_ICU_SYSTEMERR 0x00000800
195 #define LOONGSON_ICU_DRAMPERR 0x00001000
196 #define LOONGSON_ICU_RETRYERR 0x00002000
197 #define LOONGSON_ICU_GPIOS 0x01ff0000
198 #define LOONGSON_ICU_GPIOS_SHIFT 16
199 #define LOONGSON_ICU_GPINS 0x7e000000
200 #define LOONGSON_ICU_GPINS_SHIFT 25
201 #define LOONGSON_ICU_MBOX(N) (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
202 #define LOONGSON_ICU_GPIO(N) (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
203 #define LOONGSON_ICU_GPIN(N) (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
205 /* PCI prefetch window base & mask */
207 #define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40)
208 #define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44)
209 #define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48)
210 #define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
214 #define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50)
215 #define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54)
216 #define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58)
217 #define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
218 #define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60)
219 #define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64)
221 /* PXArb Config & Status */
223 #define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68)
224 #define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
228 #define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f
229 #define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0
230 #define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0
231 #define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT 6
232 #define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000
233 #define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT 12
234 #define LOONGSON_PCIMAP_PCIMAP_2 0x00040000
235 #define LOONGSON_PCIMAP_WIN(WIN, ADDR) \
236 ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
238 #ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
239 #include <linux/cpufreq.h>
240 extern void loongson2_cpu_wait(void);
241 extern struct cpufreq_frequency_table loongson2_clockmod_table[];
244 #define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80)
248 * address windows configuration module
250 * loongson2e do not have this module
252 #ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
254 /* address window config module base address */
255 #define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul
256 #define LOONGSON_ADDRWINCFG_SIZE 0x180
258 extern unsigned long _loongson_addrwincfg_base;
259 #define LOONGSON_ADDRWINCFG(offset) \
260 (*(volatile u64 *)(_loongson_addrwincfg_base + (offset)))
262 #define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00)
263 #define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08)
264 #define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10)
265 #define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18)
267 #define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20)
268 #define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28)
269 #define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30)
270 #define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38)
272 #define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40)
273 #define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48)
274 #define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50)
275 #define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58)
277 #define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60)
278 #define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68)
279 #define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70)
280 #define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78)
282 #define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80)
283 #define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88)
284 #define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90)
285 #define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98)
287 #define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0)
288 #define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8)
289 #define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0)
290 #define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8)
292 #define ADDRWIN_WIN0 0
293 #define ADDRWIN_WIN1 1
294 #define ADDRWIN_WIN2 2
295 #define ADDRWIN_WIN3 3
297 #define ADDRWIN_MAP_DST_DDR 0
298 #define ADDRWIN_MAP_DST_PCI 1
299 #define ADDRWIN_MAP_DST_LIO 1
306 * dst: map destination
309 #define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
310 s##_WIN##w##_BASE = (src); \
311 s##_WIN##w##_MMAP = (src) | ADDRWIN_MAP_DST_##d; \
312 s##_WIN##w##_MASK = ~(size-1); \
315 #define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
316 LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
317 #define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
318 LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
319 #define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
320 LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
322 #endif /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
324 #endif /* __ASM_MACH_LOONGSON_LOONGSON_H */