2 * arch/m68k/q40/config.c
4 * Copyright (C) 1999 Richard Zidlicky
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file README.legal in the main directory of this archive
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
19 #include <linux/tty.h>
20 #include <linux/console.h>
21 #include <linux/linkage.h>
22 #include <linux/init.h>
23 #include <linux/major.h>
24 #include <linux/serial_reg.h>
25 #include <linux/rtc.h>
26 #include <linux/vt_kern.h>
30 #include <asm/bootinfo.h>
31 #include <asm/system.h>
32 #include <asm/pgtable.h>
33 #include <asm/setup.h>
35 #include <asm/traps.h>
36 #include <asm/machdep.h>
37 #include <asm/q40_master.h>
39 extern void floppy_setup(char *str, int *ints);
41 extern irqreturn_t q40_process_int (int level, struct pt_regs *regs);
42 extern irqreturn_t (*q40_default_handler[]) (int, void *, struct pt_regs *); /* added just for debugging */
43 extern void q40_init_IRQ (void);
44 extern void q40_free_irq (unsigned int, void *);
45 extern int show_q40_interrupts (struct seq_file *, void *);
46 extern void q40_enable_irq (unsigned int);
47 extern void q40_disable_irq (unsigned int);
48 static void q40_get_model(char *model);
49 static int q40_get_hardware_list(char *buffer);
50 extern int q40_request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *), unsigned long flags, const char *devname, void *dev_id);
51 extern void q40_sched_init(irqreturn_t (*handler)(int, void *, struct pt_regs *));
53 extern unsigned long q40_gettimeoffset (void);
54 extern int q40_hwclk (int, struct rtc_time *);
55 extern unsigned int q40_get_ss (void);
56 extern int q40_set_clock_mmss (unsigned long);
57 static int q40_get_rtc_pll(struct rtc_pll_info *pll);
58 static int q40_set_rtc_pll(struct rtc_pll_info *pll);
59 extern void q40_reset (void);
61 extern void q40_waitbut(void);
62 void q40_set_vectors (void);
64 extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/ );
66 extern char m68k_debug_device[];
67 static void q40_mem_console_write(struct console *co, const char *b,
72 static struct console q40_console_driver = {
74 .flags = CON_PRINTBUFFER,
79 /* early debugging function:*/
80 extern char *q40_mem_cptr; /*=(char *)0xff020000;*/
83 static void q40_mem_console_write(struct console *co, const char *s,
96 void printq40(char *str)
101 while (l-- >0 && _cpleft-- >0)
112 #ifdef CONFIG_HEARTBEAT
113 static void q40_heartbeat(int on)
127 printk ("\n\n*******************************************\n"
128 "Called q40_reset : press the RESET button!! \n"
129 "*******************************************\n");
136 printk ("\n\n*******************\n"
138 "*******************\n");
143 static void q40_get_model(char *model)
145 sprintf(model, "Q40");
148 /* No hardware options on Q40? */
150 static int q40_get_hardware_list(char *buffer)
156 static unsigned int serports[]={0x3f8,0x2f8,0x3e8,0x2e8,0};
157 void q40_disable_irqs(void)
162 while((i=serports[j++])) outb(0,i+UART_IER);
163 master_outb(0,EXT_ENABLE_REG);
164 master_outb(0,KEY_IRQ_ENABLE_REG);
167 void __init config_q40(void)
169 mach_sched_init = q40_sched_init;
171 mach_init_IRQ = q40_init_IRQ;
172 mach_gettimeoffset = q40_gettimeoffset;
173 mach_hwclk = q40_hwclk;
174 mach_get_ss = q40_get_ss;
175 mach_get_rtc_pll = q40_get_rtc_pll;
176 mach_set_rtc_pll = q40_set_rtc_pll;
177 mach_set_clock_mmss = q40_set_clock_mmss;
179 mach_reset = q40_reset;
180 mach_free_irq = q40_free_irq;
181 mach_process_int = q40_process_int;
182 mach_get_irq_list = show_q40_interrupts;
183 mach_request_irq = q40_request_irq;
184 enable_irq = q40_enable_irq;
185 disable_irq = q40_disable_irq;
186 mach_default_handler = &q40_default_handler;
187 mach_get_model = q40_get_model;
188 mach_get_hardware_list = q40_get_hardware_list;
190 #if defined(CONFIG_INPUT_M68K_BEEP) || defined(CONFIG_INPUT_M68K_BEEP_MODULE)
191 mach_beep = q40_mksound;
193 #ifdef CONFIG_HEARTBEAT
194 mach_heartbeat = q40_heartbeat;
196 mach_halt = q40_halt;
198 /* disable a few things that SMSQ might have left enabled */
201 /* no DMA at all, but ide-scsi requires it.. make sure
202 * all physical RAM fits into the boundary - otherwise
203 * allocator may play costly and useless tricks */
204 mach_max_dma_address = 1024*1024*1024;
206 /* useful for early debugging stages - writes kernel messages into SRAM */
207 if (!strncmp( m68k_debug_device,"mem",3 ))
209 /*printk("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/
210 _cpleft=2000-((long)q40_mem_cptr-0xff020000)/4;
211 q40_console_driver.write = q40_mem_console_write;
212 register_console(&q40_console_driver);
217 int q40_parse_bootinfo(const struct bi_record *rec)
223 static inline unsigned char bcd2bin (unsigned char b)
225 return ((b>>4)*10 + (b&15));
228 static inline unsigned char bin2bcd (unsigned char b)
230 return (((b/10)*16) + (b%10));
234 unsigned long q40_gettimeoffset (void)
236 return 5000*(ql_ticks!=0);
241 * Looks like op is non-zero for setting the clock, and zero for
244 * struct hwclk_time {
245 * unsigned sec; 0..59
246 * unsigned min; 0..59
247 * unsigned hour; 0..23
248 * unsigned day; 1..31
249 * unsigned mon; 0..11
250 * unsigned year; 00...
251 * int wday; 0..6, 0 is Sunday, -1 means unknown/don't set
255 int q40_hwclk(int op, struct rtc_time *t)
259 Q40_RTC_CTRL |= Q40_RTC_WRITE;
261 Q40_RTC_SECS = bin2bcd(t->tm_sec);
262 Q40_RTC_MINS = bin2bcd(t->tm_min);
263 Q40_RTC_HOUR = bin2bcd(t->tm_hour);
264 Q40_RTC_DATE = bin2bcd(t->tm_mday);
265 Q40_RTC_MNTH = bin2bcd(t->tm_mon + 1);
266 Q40_RTC_YEAR = bin2bcd(t->tm_year%100);
268 Q40_RTC_DOW = bin2bcd(t->tm_wday+1);
270 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
274 Q40_RTC_CTRL |= Q40_RTC_READ;
276 t->tm_year = bcd2bin (Q40_RTC_YEAR);
277 t->tm_mon = bcd2bin (Q40_RTC_MNTH)-1;
278 t->tm_mday = bcd2bin (Q40_RTC_DATE);
279 t->tm_hour = bcd2bin (Q40_RTC_HOUR);
280 t->tm_min = bcd2bin (Q40_RTC_MINS);
281 t->tm_sec = bcd2bin (Q40_RTC_SECS);
283 Q40_RTC_CTRL &= ~(Q40_RTC_READ);
287 t->tm_wday = bcd2bin(Q40_RTC_DOW)-1;
294 unsigned int q40_get_ss(void)
296 return bcd2bin(Q40_RTC_SECS);
300 * Set the minutes and seconds from seconds value 'nowtime'. Fail if
301 * clock is out by > 30 minutes. Logic lifted from atari code.
304 int q40_set_clock_mmss (unsigned long nowtime)
307 short real_seconds = nowtime % 60, real_minutes = (nowtime / 60) % 60;
312 rtc_minutes = bcd2bin (Q40_RTC_MINS);
314 if ((rtc_minutes < real_minutes
315 ? real_minutes - rtc_minutes
316 : rtc_minutes - real_minutes) < 30)
318 Q40_RTC_CTRL |= Q40_RTC_WRITE;
319 Q40_RTC_MINS = bin2bcd(real_minutes);
320 Q40_RTC_SECS = bin2bcd(real_seconds);
321 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);
331 /* get and set PLL calibration of RTC clock */
332 #define Q40_RTC_PLL_MASK ((1<<5)-1)
333 #define Q40_RTC_PLL_SIGN (1<<5)
335 static int q40_get_rtc_pll(struct rtc_pll_info *pll)
337 int tmp=Q40_RTC_CTRL;
338 pll->pll_value = tmp & Q40_RTC_PLL_MASK;
339 if (tmp & Q40_RTC_PLL_SIGN)
340 pll->pll_value = -pll->pll_value;
343 pll->pll_posmult=512;
344 pll->pll_negmult=256;
345 pll->pll_clock=125829120;
349 static int q40_set_rtc_pll(struct rtc_pll_info *pll)
352 /* the docs are a bit unclear so I am doublesetting */
353 /* RTC_WRITE here ... */
354 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) |
356 Q40_RTC_CTRL |= Q40_RTC_WRITE;
358 Q40_RTC_CTRL &= ~(Q40_RTC_WRITE);