2 * File: arch/blackfin/mach-common/ints-priority.c
7 * Description: Set up the interrupt priorities
11 * 1999 D. Jeff Dionne <jeff@uclinux.org>
12 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl>
16 * Copyright 2004-2008 Analog Devices Inc.
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see the file COPYING, or write
32 * to the Free Software Foundation, Inc.,
33 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
36 #include <linux/module.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/seq_file.h>
39 #include <linux/irq.h>
41 #include <linux/kgdb.h>
43 #include <asm/traps.h>
44 #include <asm/blackfin.h>
46 #include <asm/irq_handler.h>
49 # define BF537_GENERIC_ERROR_INT_DEMUX
51 # undef BF537_GENERIC_ERROR_INT_DEMUX
56 * - we have separated the physical Hardware interrupt from the
57 * levels that the LINUX kernel sees (see the description in irq.h)
61 /* Initialize this to an actual value to force it into the .data
62 * section so that we know it is properly initialized at entry into
63 * the kernel but before bss is initialized to zero (which is where
64 * it would live otherwise). The 0x1f magic represents the IRQs we
65 * cannot actually mask out in hardware.
67 unsigned long irq_flags = 0x1f;
68 EXPORT_SYMBOL(irq_flags);
70 /* The number of spurious interrupts */
71 atomic_t num_spurious;
74 unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
79 /* irq number for request_irq, available in mach-bf5xx/irq.h */
81 /* corresponding bit in the SIC_ISR register */
83 } ivg_table[NR_PERI_INTS];
86 /* position of first irq in ivg_table for given ivg */
89 } ivg7_13[IVG13 - IVG7 + 1];
93 * Search SIC_IAR and fill tables with the irqvalues
94 * and their positions in the SIC_ISR register.
96 static void __init search_IAR(void)
98 unsigned ivg, irq_pos = 0;
99 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
102 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
104 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
105 int iar_shift = (irqn & 7) * 4;
107 #if defined(CONFIG_BF52x) || defined(CONFIG_BF538) || defined(CONFIG_BF539)
108 bfin_read32((unsigned long *)SIC_IAR0 +
109 ((irqn % 32) >> 3) + ((irqn / 32) *
110 ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
112 bfin_read32((unsigned long *)SIC_IAR0 +
113 (irqn >> 3)) >> iar_shift)) {
115 ivg_table[irq_pos].irqno = IVG7 + irqn;
116 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
117 ivg7_13[ivg].istop++;
125 * This is for core internal IRQs
128 static void bfin_ack_noop(unsigned int irq)
130 /* Dummy function. */
133 static void bfin_core_mask_irq(unsigned int irq)
135 irq_flags &= ~(1 << irq);
136 if (!irqs_disabled())
140 static void bfin_core_unmask_irq(unsigned int irq)
142 irq_flags |= 1 << irq;
144 * If interrupts are enabled, IMASK must contain the same value
145 * as irq_flags. Make sure that invariant holds. If interrupts
146 * are currently disabled we need not do anything; one of the
147 * callers will take care of setting IMASK to the proper value
148 * when reenabling interrupts.
149 * local_irq_enable just does "STI irq_flags", so it's exactly
152 if (!irqs_disabled())
157 static void bfin_internal_mask_irq(unsigned int irq)
160 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
161 ~(1 << SIC_SYSIRQ(irq)));
163 unsigned mask_bank, mask_bit;
164 mask_bank = SIC_SYSIRQ(irq) / 32;
165 mask_bit = SIC_SYSIRQ(irq) % 32;
166 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
172 static void bfin_internal_unmask_irq(unsigned int irq)
175 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
176 (1 << SIC_SYSIRQ(irq)));
178 unsigned mask_bank, mask_bit;
179 mask_bank = SIC_SYSIRQ(irq) / 32;
180 mask_bit = SIC_SYSIRQ(irq) % 32;
181 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
188 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
190 unsigned bank, bit, wakeup = 0;
192 bank = SIC_SYSIRQ(irq) / 32;
193 bit = SIC_SYSIRQ(irq) % 32;
230 local_irq_save(flags);
233 bfin_sic_iwr[bank] |= (1 << bit);
237 bfin_sic_iwr[bank] &= ~(1 << bit);
238 vr_wakeup &= ~wakeup;
241 local_irq_restore(flags);
247 static struct irq_chip bfin_core_irqchip = {
249 .ack = bfin_ack_noop,
250 .mask = bfin_core_mask_irq,
251 .unmask = bfin_core_unmask_irq,
254 static struct irq_chip bfin_internal_irqchip = {
256 .ack = bfin_ack_noop,
257 .mask = bfin_internal_mask_irq,
258 .unmask = bfin_internal_unmask_irq,
259 .mask_ack = bfin_internal_mask_irq,
260 .disable = bfin_internal_mask_irq,
261 .enable = bfin_internal_unmask_irq,
263 .set_wake = bfin_internal_set_wake,
267 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
268 static int error_int_mask;
270 static void bfin_generic_error_mask_irq(unsigned int irq)
272 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
275 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
278 static void bfin_generic_error_unmask_irq(unsigned int irq)
280 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
281 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
284 static struct irq_chip bfin_generic_error_irqchip = {
286 .ack = bfin_ack_noop,
287 .mask_ack = bfin_generic_error_mask_irq,
288 .mask = bfin_generic_error_mask_irq,
289 .unmask = bfin_generic_error_unmask_irq,
292 static void bfin_demux_error_irq(unsigned int int_err_irq,
293 struct irq_desc *inta_desc)
299 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
300 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
304 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
305 irq = IRQ_SPORT0_ERROR;
306 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
307 irq = IRQ_SPORT1_ERROR;
308 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
310 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
312 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
314 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
315 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
316 irq = IRQ_UART0_ERROR;
317 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
318 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
319 irq = IRQ_UART1_ERROR;
322 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
323 struct irq_desc *desc = irq_desc + irq;
324 desc->handle_irq(irq, desc);
329 bfin_write_PPI_STATUS(PPI_ERR_MASK);
331 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
333 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
336 case IRQ_SPORT0_ERROR:
337 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
340 case IRQ_SPORT1_ERROR:
341 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
345 bfin_write_CAN_GIS(CAN_ERR_MASK);
349 bfin_write_SPI_STAT(SPI_ERR_MASK);
357 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
362 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
363 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
364 __func__, __FILE__, __LINE__);
367 #endif /* BF537_GENERIC_ERROR_INT_DEMUX */
369 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
371 struct irq_desc *desc = irq_desc + irq;
372 /* May not call generic set_irq_handler() due to spinlock
374 desc->handle_irq = handle;
377 #if !defined(CONFIG_BF54x)
379 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
380 static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
382 extern void bfin_gpio_irq_prepare(unsigned gpio);
384 static void bfin_gpio_ack_irq(unsigned int irq)
386 u16 gpionr = irq - IRQ_PF0;
388 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
389 set_gpio_data(gpionr, 0);
394 static void bfin_gpio_mask_ack_irq(unsigned int irq)
396 u16 gpionr = irq - IRQ_PF0;
398 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
399 set_gpio_data(gpionr, 0);
403 set_gpio_maska(gpionr, 0);
407 static void bfin_gpio_mask_irq(unsigned int irq)
409 set_gpio_maska(irq - IRQ_PF0, 0);
413 static void bfin_gpio_unmask_irq(unsigned int irq)
415 set_gpio_maska(irq - IRQ_PF0, 1);
419 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
421 u16 gpionr = irq - IRQ_PF0;
423 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
424 bfin_gpio_irq_prepare(gpionr);
426 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
427 bfin_gpio_unmask_irq(irq);
432 static void bfin_gpio_irq_shutdown(unsigned int irq)
434 bfin_gpio_mask_irq(irq);
435 gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
438 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
440 u16 gpionr = irq - IRQ_PF0;
442 if (type == IRQ_TYPE_PROBE) {
443 /* only probe unenabled GPIO interrupt lines */
444 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
446 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
449 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
450 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
451 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
452 bfin_gpio_irq_prepare(gpionr);
454 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
456 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
460 set_gpio_inen(gpionr, 0);
461 set_gpio_dir(gpionr, 0);
463 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
464 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
465 set_gpio_both(gpionr, 1);
467 set_gpio_both(gpionr, 0);
469 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
470 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
472 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
474 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
475 set_gpio_edge(gpionr, 1);
476 set_gpio_inen(gpionr, 1);
477 gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
478 set_gpio_data(gpionr, 0);
481 set_gpio_edge(gpionr, 0);
482 gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
483 set_gpio_inen(gpionr, 1);
488 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
489 bfin_set_irq_handler(irq, handle_edge_irq);
491 bfin_set_irq_handler(irq, handle_level_irq);
497 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
499 unsigned gpio = irq_to_gpio(irq);
502 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
504 gpio_pm_wakeup_free(gpio);
510 static struct irq_chip bfin_gpio_irqchip = {
512 .ack = bfin_gpio_ack_irq,
513 .mask = bfin_gpio_mask_irq,
514 .mask_ack = bfin_gpio_mask_ack_irq,
515 .unmask = bfin_gpio_unmask_irq,
516 .disable = bfin_gpio_mask_irq,
517 .enable = bfin_gpio_unmask_irq,
518 .set_type = bfin_gpio_irq_type,
519 .startup = bfin_gpio_irq_startup,
520 .shutdown = bfin_gpio_irq_shutdown,
522 .set_wake = bfin_gpio_set_wake,
526 static void bfin_demux_gpio_irq(unsigned int inta_irq,
527 struct irq_desc *desc)
529 unsigned int i, gpio, mask, irq, search = 0;
532 #if defined(CONFIG_BF53x)
537 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
542 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
546 #elif defined(CONFIG_BF52x)
556 #elif defined(CONFIG_BF561)
573 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
576 mask = get_gpiop_data(i) &
577 (gpio_enabled[gpio_bank(i)] &
582 desc = irq_desc + irq;
583 desc->handle_irq(irq, desc);
590 gpio = irq_to_gpio(irq);
591 mask = get_gpiop_data(gpio) &
592 (gpio_enabled[gpio_bank(gpio)] &
593 get_gpiop_maska(gpio));
597 desc = irq_desc + irq;
598 desc->handle_irq(irq, desc);
607 #else /* CONFIG_BF54x */
609 #define NR_PINT_SYS_IRQS 4
610 #define NR_PINT_BITS 32
612 #define IRQ_NOT_AVAIL 0xFF
614 #define PINT_2_BANK(x) ((x) >> 5)
615 #define PINT_2_BIT(x) ((x) & 0x1F)
616 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
618 static unsigned char irq2pint_lut[NR_PINTS];
619 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
621 static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS];
622 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
626 unsigned int mask_set;
627 unsigned int mask_clear;
628 unsigned int request;
630 unsigned int edge_set;
631 unsigned int edge_clear;
632 unsigned int invert_set;
633 unsigned int invert_clear;
634 unsigned int pinstate;
638 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
639 (struct pin_int_t *)PINT0_MASK_SET,
640 (struct pin_int_t *)PINT1_MASK_SET,
641 (struct pin_int_t *)PINT2_MASK_SET,
642 (struct pin_int_t *)PINT3_MASK_SET,
645 extern void bfin_gpio_irq_prepare(unsigned gpio);
647 inline unsigned short get_irq_base(u8 bank, u8 bmap)
652 if (bank < 2) { /*PA-PB */
653 irq_base = IRQ_PA0 + bmap * 16;
655 irq_base = IRQ_PC0 + bmap * 16;
662 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
663 void init_pint_lut(void)
665 u16 bank, bit, irq_base, bit_pos;
669 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
671 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
673 pint_assign = pint[bank]->assign;
675 for (bit = 0; bit < NR_PINT_BITS; bit++) {
677 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
679 irq_base = get_irq_base(bank, bmap);
681 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
682 bit_pos = bit + bank * NR_PINT_BITS;
684 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
685 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
693 static void bfin_gpio_ack_irq(unsigned int irq)
695 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
696 u32 pintbit = PINT_BIT(pint_val);
697 u8 bank = PINT_2_BANK(pint_val);
699 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
700 if (pint[bank]->invert_set & pintbit)
701 pint[bank]->invert_clear = pintbit;
703 pint[bank]->invert_set = pintbit;
705 pint[bank]->request = pintbit;
710 static void bfin_gpio_mask_ack_irq(unsigned int irq)
712 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
713 u32 pintbit = PINT_BIT(pint_val);
714 u8 bank = PINT_2_BANK(pint_val);
716 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
717 if (pint[bank]->invert_set & pintbit)
718 pint[bank]->invert_clear = pintbit;
720 pint[bank]->invert_set = pintbit;
723 pint[bank]->request = pintbit;
724 pint[bank]->mask_clear = pintbit;
728 static void bfin_gpio_mask_irq(unsigned int irq)
730 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
732 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
736 static void bfin_gpio_unmask_irq(unsigned int irq)
738 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
739 u32 pintbit = PINT_BIT(pint_val);
740 u8 bank = PINT_2_BANK(pint_val);
742 pint[bank]->request = pintbit;
743 pint[bank]->mask_set = pintbit;
747 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
749 u16 gpionr = irq_to_gpio(irq);
750 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
752 if (pint_val == IRQ_NOT_AVAIL) {
754 "GPIO IRQ %d :Not in PINT Assign table "
755 "Reconfigure Interrupt to Port Assignemt\n", irq);
759 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
760 bfin_gpio_irq_prepare(gpionr);
762 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
763 bfin_gpio_unmask_irq(irq);
768 static void bfin_gpio_irq_shutdown(unsigned int irq)
770 u16 gpionr = irq_to_gpio(irq);
772 bfin_gpio_mask_irq(irq);
773 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
776 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
779 u16 gpionr = irq_to_gpio(irq);
780 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
781 u32 pintbit = PINT_BIT(pint_val);
782 u8 bank = PINT_2_BANK(pint_val);
784 if (pint_val == IRQ_NOT_AVAIL)
787 if (type == IRQ_TYPE_PROBE) {
788 /* only probe unenabled GPIO interrupt lines */
789 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
791 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
794 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
795 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
796 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
797 bfin_gpio_irq_prepare(gpionr);
799 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
801 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
805 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
806 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
808 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
810 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
811 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
813 gpio_both_edge_triggered[bank] |= pintbit;
815 if (gpio_get_value(gpionr))
816 pint[bank]->invert_set = pintbit;
818 pint[bank]->invert_clear = pintbit;
820 gpio_both_edge_triggered[bank] &= ~pintbit;
823 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
824 pint[bank]->edge_set = pintbit;
825 bfin_set_irq_handler(irq, handle_edge_irq);
827 pint[bank]->edge_clear = pintbit;
828 bfin_set_irq_handler(irq, handle_level_irq);
837 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
838 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
840 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
843 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
844 u32 bank = PINT_2_BANK(pint_val);
845 u32 pintbit = PINT_BIT(pint_val);
849 pint_irq = IRQ_PINT0;
852 pint_irq = IRQ_PINT2;
855 pint_irq = IRQ_PINT3;
858 pint_irq = IRQ_PINT1;
864 bfin_internal_set_wake(pint_irq, state);
867 pint_wakeup_masks[bank] |= pintbit;
869 pint_wakeup_masks[bank] &= ~pintbit;
874 u32 bfin_pm_setup(void)
878 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
879 val = pint[i]->mask_clear;
880 pint_saved_masks[i] = val;
881 if (val ^ pint_wakeup_masks[i]) {
882 pint[i]->mask_clear = val;
883 pint[i]->mask_set = pint_wakeup_masks[i];
890 void bfin_pm_restore(void)
894 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
895 val = pint_saved_masks[i];
896 if (val ^ pint_wakeup_masks[i]) {
897 pint[i]->mask_clear = pint[i]->mask_clear;
898 pint[i]->mask_set = val;
904 static struct irq_chip bfin_gpio_irqchip = {
906 .ack = bfin_gpio_ack_irq,
907 .mask = bfin_gpio_mask_irq,
908 .mask_ack = bfin_gpio_mask_ack_irq,
909 .unmask = bfin_gpio_unmask_irq,
910 .disable = bfin_gpio_mask_irq,
911 .enable = bfin_gpio_unmask_irq,
912 .set_type = bfin_gpio_irq_type,
913 .startup = bfin_gpio_irq_startup,
914 .shutdown = bfin_gpio_irq_shutdown,
916 .set_wake = bfin_gpio_set_wake,
920 static void bfin_demux_gpio_irq(unsigned int inta_irq,
921 struct irq_desc *desc)
943 pint_val = bank * NR_PINT_BITS;
945 request = pint[bank]->request;
949 irq = pint2irq_lut[pint_val] + SYS_IRQS;
950 desc = irq_desc + irq;
951 desc->handle_irq(irq, desc);
960 void __init init_exception_vectors(void)
964 /* cannot program in software:
965 * evt0 - emulation (jtag)
968 bfin_write_EVT2(evt_nmi);
969 bfin_write_EVT3(trap);
970 bfin_write_EVT5(evt_ivhw);
971 bfin_write_EVT6(evt_timer);
972 bfin_write_EVT7(evt_evt7);
973 bfin_write_EVT8(evt_evt8);
974 bfin_write_EVT9(evt_evt9);
975 bfin_write_EVT10(evt_evt10);
976 bfin_write_EVT11(evt_evt11);
977 bfin_write_EVT12(evt_evt12);
978 bfin_write_EVT13(evt_evt13);
979 bfin_write_EVT14(evt14_softirq);
980 bfin_write_EVT15(evt_system_call);
985 * This function should be called during kernel startup to initialize
986 * the BFin IRQ handling routines.
988 int __init init_arch_irq(void)
991 unsigned long ilat = 0;
992 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
993 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || defined(BF538_FAMILY)
994 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
995 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
997 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1000 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1003 local_irq_disable();
1005 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
1006 /* Clear EMAC Interrupt Status bits so we can demux it later */
1007 bfin_write_EMAC_SYSTAT(-1);
1011 # ifdef CONFIG_PINTx_REASSIGN
1012 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1013 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1014 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1015 pint[3]->assign = CONFIG_PINT3_ASSIGN;
1017 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1021 for (irq = 0; irq <= SYS_IRQS; irq++) {
1022 if (irq <= IRQ_CORETMR)
1023 set_irq_chip(irq, &bfin_core_irqchip);
1025 set_irq_chip(irq, &bfin_internal_irqchip);
1028 #if defined(CONFIG_BF53x)
1030 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1033 #elif defined(CONFIG_BF54x)
1038 #elif defined(CONFIG_BF52x)
1039 case IRQ_PORTF_INTA:
1040 case IRQ_PORTG_INTA:
1041 case IRQ_PORTH_INTA:
1042 #elif defined(CONFIG_BF561)
1043 case IRQ_PROG0_INTA:
1044 case IRQ_PROG1_INTA:
1045 case IRQ_PROG2_INTA:
1046 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1047 case IRQ_PORTF_INTA:
1050 set_irq_chained_handler(irq,
1051 bfin_demux_gpio_irq);
1053 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1054 case IRQ_GENERIC_ERROR:
1055 set_irq_handler(irq, bfin_demux_error_irq);
1060 set_irq_handler(irq, handle_simple_irq);
1065 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1066 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1067 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1071 /* if configured as edge, then will be changed to do_edge_IRQ */
1072 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1073 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1077 bfin_write_IMASK(0);
1079 ilat = bfin_read_ILAT();
1081 bfin_write_ILAT(ilat);
1084 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1085 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
1086 * local_irq_enable()
1089 /* Therefore it's better to setup IARs before interrupts enabled */
1092 /* Enable interrupts IVG7-15 */
1093 irq_flags = irq_flags | IMASK_IVG15 |
1094 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1095 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1097 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || defined(BF538_FAMILY)
1098 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1099 #if defined(CONFIG_BF52x)
1100 /* BF52x system reset does not properly reset SIC_IWR1 which
1101 * will screw up the bootrom as it relies on MDMA0/1 waking it
1102 * up from IDLE instructions. See this report for more info:
1103 * http://blackfin.uclinux.org/gf/tracker/4323
1105 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1107 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1109 # ifdef CONFIG_BF54x
1110 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1113 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1119 #ifdef CONFIG_DO_IRQ_L1
1120 __attribute__((l1_text))
1122 void do_irq(int vec, struct pt_regs *fp)
1124 if (vec == EVT_IVTMR_P) {
1127 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1128 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1129 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || defined(BF538_FAMILY)
1130 unsigned long sic_status[3];
1132 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1133 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1135 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1138 if (ivg >= ivg_stop) {
1139 atomic_inc(&num_spurious);
1142 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1146 unsigned long sic_status;
1148 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1151 if (ivg >= ivg_stop) {
1152 atomic_inc(&num_spurious);
1154 } else if (sic_status & ivg->isrflag)
1160 asm_do_IRQ(vec, fp);