2 * File: arch/blackfin/mach-bf537/head.S
3 * Based on: arch/blackfin/mach-bf533/head.S
4 * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
7 * Description: Startup code for Blackfin BF537
10 * Copyright 2004-2006 Analog Devices Inc.
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 #include <linux/linkage.h>
31 #include <linux/init.h>
32 #include <asm/blackfin.h>
33 #ifdef CONFIG_BFIN_KERNEL_CLOCK
34 #include <asm/mach-common/clocks.h>
35 #include <asm/mach/mem_init.h>
38 .extern _bf53x_relocate_l1_mem
42 ENTRY(_mach_early_start)
43 /* Initialise General-Purpose I/O Modules on BF537 */
44 p0.h = hi(BFIN_PORT_MUX);
45 p0.l = lo(BFIN_PORT_MUX);
46 R0 = (PGDE_UART | PFTE_UART)(Z);
47 W[P0] = R0.L; /* Enable both UARTS */
50 /* Enable peripheral function of PORTF for UART0 and UART1 */
57 #if !defined(CONFIG_BF534)
58 p0.h = hi(EMAC_SYSTAT);
59 p0.l = lo(EMAC_SYSTAT);
60 R0.h = 0xFFFF; /* Clear EMAC Interrupt Status bits */
66 /* Initialise UART - when booting from u-boot, the UART is not disabled
67 * so if we dont initalize here, our serial console gets hosed */
68 p0.h = hi(BFIN_UART_LCR);
69 p0.l = lo(BFIN_UART_LCR);
71 w[p0] = r0.L; /* To enable DLL writes */
74 p0.h = hi(BFIN_UART_DLL);
75 p0.l = lo(BFIN_UART_DLL);
80 p0.h = hi(BFIN_UART_DLH);
81 p0.l = lo(BFIN_UART_DLH);
86 p0.h = hi(BFIN_UART_GCTL);
87 p0.l = lo(BFIN_UART_GCTL);
89 w[p0] = r0.L; /* To enable UART clock */
93 ENDPROC(_mach_early_start)
98 #ifdef CONFIG_BFIN_KERNEL_CLOCK
99 ENTRY(_start_dma_code)
101 /* Enable PHY CLK buffer output */
118 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
119 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
120 * - [7] = output delay (add 200ps of delay to mem signals)
121 * - [6] = input delay (add 200ps of input delay to mem signals)
122 * - [5] = PDWN : 1=All Clocks off
123 * - [3] = STOPCK : 1=Core Clock off
124 * - [1] = PLL_OFF : 1=Disable Power to PLL
125 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
126 * all other bits set to zero
129 p0.h = hi(PLL_LOCKCNT);
130 p0.l = lo(PLL_LOCKCNT);
135 P2.H = hi(EBIU_SDGCTL);
136 P2.L = lo(EBIU_SDGCTL);
142 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
143 r0 = r0 << 9; /* Shift it over, */
144 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
146 r1 = PLL_BYPASS; /* Bypass the PLL? */
147 r1 = r1 << 8; /* Shift it over */
148 r0 = r1 | r0; /* add them all together */
151 p0.l = lo(PLL_CTL); /* Load the address */
152 cli r2; /* Disable interrupts */
154 w[p0] = r0.l; /* Set the value */
155 idle; /* Wait for the PLL to stablize */
156 sti r2; /* Enable interrupts */
163 if ! CC jump .Lcheck_again;
165 /* Configure SCLK & CCLK Dividers */
166 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
172 p0.l = lo(EBIU_SDRRC);
173 p0.h = hi(EBIU_SDRRC);
178 P2.H = hi(EBIU_SDGCTL);
179 P2.L = lo(EBIU_SDGCTL);
182 p0.h = hi(EBIU_SDSTAT);
183 p0.l = lo(EBIU_SDSTAT);
193 R0.L = lo(mem_SDGCTL);
194 R0.H = hi(mem_SDGCTL);
202 r0.l = lo(IWR_ENABLE_ALL);
203 r0.h = hi(IWR_ENABLE_ALL);
208 ENDPROC(_start_dma_code)
209 #endif /* CONFIG_BFIN_KERNEL_CLOCK */