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   1 /*
   2  * arch/blackfin/kernel/kgdb.c - Blackfin kgdb pieces
   3  *
   4  * Copyright 2005-2008 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <linux/string.h>
  10 #include <linux/kernel.h>
  11 #include <linux/sched.h>
  12 #include <linux/smp.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/delay.h>
  15 #include <linux/ptrace.h>               /* for linux pt_regs struct */
  16 #include <linux/kgdb.h>
  17 #include <linux/console.h>
  18 #include <linux/init.h>
  19 #include <linux/errno.h>
  20 #include <linux/irq.h>
  21 #include <linux/uaccess.h>
  22 #include <asm/system.h>
  23 #include <asm/traps.h>
  24 #include <asm/blackfin.h>
  25 #include <asm/dma.h>
  26
  27 /* Put the error code here just in case the user cares.  */
  28 int gdb_bfin_errcode;
  29 /* Likewise, the vector number here (since GDB only gets the signal
  30    number through the usual means, and that's not very specific).  */
  31 int gdb_bfin_vector = -1;
  32
  33 #if KGDB_MAX_NO_CPUS != 8
  34 #error change the definition of slavecpulocks
  35 #endif
  36
  37 #ifdef CONFIG_BFIN_WDT
  38 # error "Please unselect blackfin watchdog driver before build KGDB."
  39 #endif
  40
  41 void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
  42 {
  43         gdb_regs[BFIN_R0] = regs->r0;
  44         gdb_regs[BFIN_R1] = regs->r1;
  45         gdb_regs[BFIN_R2] = regs->r2;
  46         gdb_regs[BFIN_R3] = regs->r3;
  47         gdb_regs[BFIN_R4] = regs->r4;
  48         gdb_regs[BFIN_R5] = regs->r5;
  49         gdb_regs[BFIN_R6] = regs->r6;
  50         gdb_regs[BFIN_R7] = regs->r7;
  51         gdb_regs[BFIN_P0] = regs->p0;
  52         gdb_regs[BFIN_P1] = regs->p1;
  53         gdb_regs[BFIN_P2] = regs->p2;
  54         gdb_regs[BFIN_P3] = regs->p3;
  55         gdb_regs[BFIN_P4] = regs->p4;
  56         gdb_regs[BFIN_P5] = regs->p5;
  57         gdb_regs[BFIN_SP] = regs->reserved;
  58         gdb_regs[BFIN_FP] = regs->fp;
  59         gdb_regs[BFIN_I0] = regs->i0;
  60         gdb_regs[BFIN_I1] = regs->i1;
  61         gdb_regs[BFIN_I2] = regs->i2;
  62         gdb_regs[BFIN_I3] = regs->i3;
  63         gdb_regs[BFIN_M0] = regs->m0;
  64         gdb_regs[BFIN_M1] = regs->m1;
  65         gdb_regs[BFIN_M2] = regs->m2;
  66         gdb_regs[BFIN_M3] = regs->m3;
  67         gdb_regs[BFIN_B0] = regs->b0;
  68         gdb_regs[BFIN_B1] = regs->b1;
  69         gdb_regs[BFIN_B2] = regs->b2;
  70         gdb_regs[BFIN_B3] = regs->b3;
  71         gdb_regs[BFIN_L0] = regs->l0;
  72         gdb_regs[BFIN_L1] = regs->l1;
  73         gdb_regs[BFIN_L2] = regs->l2;
  74         gdb_regs[BFIN_L3] = regs->l3;
  75         gdb_regs[BFIN_A0_DOT_X] = regs->a0x;
  76         gdb_regs[BFIN_A0_DOT_W] = regs->a0w;
  77         gdb_regs[BFIN_A1_DOT_X] = regs->a1x;
  78         gdb_regs[BFIN_A1_DOT_W] = regs->a1w;
  79         gdb_regs[BFIN_ASTAT] = regs->astat;
  80         gdb_regs[BFIN_RETS] = regs->rets;
  81         gdb_regs[BFIN_LC0] = regs->lc0;
  82         gdb_regs[BFIN_LT0] = regs->lt0;
  83         gdb_regs[BFIN_LB0] = regs->lb0;
  84         gdb_regs[BFIN_LC1] = regs->lc1;
  85         gdb_regs[BFIN_LT1] = regs->lt1;
  86         gdb_regs[BFIN_LB1] = regs->lb1;
  87         gdb_regs[BFIN_CYCLES] = 0;
  88         gdb_regs[BFIN_CYCLES2] = 0;
  89         gdb_regs[BFIN_USP] = regs->usp;
  90         gdb_regs[BFIN_SEQSTAT] = regs->seqstat;
  91         gdb_regs[BFIN_SYSCFG] = regs->syscfg;
  92         gdb_regs[BFIN_RETI] = regs->pc;
  93         gdb_regs[BFIN_RETX] = regs->retx;
  94         gdb_regs[BFIN_RETN] = regs->retn;
  95         gdb_regs[BFIN_RETE] = regs->rete;
  96         gdb_regs[BFIN_PC] = regs->pc;
  97         gdb_regs[BFIN_CC] = 0;
  98         gdb_regs[BFIN_EXTRA1] = 0;
  99         gdb_regs[BFIN_EXTRA2] = 0;
 100         gdb_regs[BFIN_EXTRA3] = 0;
 101         gdb_regs[BFIN_IPEND] = regs->ipend;
 102 }
 103
 104 /*
 105  * Extracts ebp, esp and eip values understandable by gdb from the values
 106  * saved by switch_to.
 107  * thread.esp points to ebp. flags and ebp are pushed in switch_to hence esp
 108  * prior to entering switch_to is 8 greater then the value that is saved.
 109  * If switch_to changes, change following code appropriately.
 110  */
 111 void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
 112 {
 113         gdb_regs[BFIN_SP] = p->thread.ksp;
 114         gdb_regs[BFIN_PC] = p->thread.pc;
 115         gdb_regs[BFIN_SEQSTAT] = p->thread.seqstat;
 116 }
 117
 118 void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
 119 {
 120         regs->r0 = gdb_regs[BFIN_R0];
 121         regs->r1 = gdb_regs[BFIN_R1];
 122         regs->r2 = gdb_regs[BFIN_R2];
 123         regs->r3 = gdb_regs[BFIN_R3];
 124         regs->r4 = gdb_regs[BFIN_R4];
 125         regs->r5 = gdb_regs[BFIN_R5];
 126         regs->r6 = gdb_regs[BFIN_R6];
 127         regs->r7 = gdb_regs[BFIN_R7];
 128         regs->p0 = gdb_regs[BFIN_P0];
 129         regs->p1 = gdb_regs[BFIN_P1];
 130         regs->p2 = gdb_regs[BFIN_P2];
 131         regs->p3 = gdb_regs[BFIN_P3];
 132         regs->p4 = gdb_regs[BFIN_P4];
 133         regs->p5 = gdb_regs[BFIN_P5];
 134         regs->fp = gdb_regs[BFIN_FP];
 135         regs->i0 = gdb_regs[BFIN_I0];
 136         regs->i1 = gdb_regs[BFIN_I1];
 137         regs->i2 = gdb_regs[BFIN_I2];
 138         regs->i3 = gdb_regs[BFIN_I3];
 139         regs->m0 = gdb_regs[BFIN_M0];
 140         regs->m1 = gdb_regs[BFIN_M1];
 141         regs->m2 = gdb_regs[BFIN_M2];
 142         regs->m3 = gdb_regs[BFIN_M3];
 143         regs->b0 = gdb_regs[BFIN_B0];
 144         regs->b1 = gdb_regs[BFIN_B1];
 145         regs->b2 = gdb_regs[BFIN_B2];
 146         regs->b3 = gdb_regs[BFIN_B3];
 147         regs->l0 = gdb_regs[BFIN_L0];
 148         regs->l1 = gdb_regs[BFIN_L1];
 149         regs->l2 = gdb_regs[BFIN_L2];
 150         regs->l3 = gdb_regs[BFIN_L3];
 151         regs->a0x = gdb_regs[BFIN_A0_DOT_X];
 152         regs->a0w = gdb_regs[BFIN_A0_DOT_W];
 153         regs->a1x = gdb_regs[BFIN_A1_DOT_X];
 154         regs->a1w = gdb_regs[BFIN_A1_DOT_W];
 155         regs->rets = gdb_regs[BFIN_RETS];
 156         regs->lc0 = gdb_regs[BFIN_LC0];
 157         regs->lt0 = gdb_regs[BFIN_LT0];
 158         regs->lb0 = gdb_regs[BFIN_LB0];
 159         regs->lc1 = gdb_regs[BFIN_LC1];
 160         regs->lt1 = gdb_regs[BFIN_LT1];
 161         regs->lb1 = gdb_regs[BFIN_LB1];
 162         regs->usp = gdb_regs[BFIN_USP];
 163         regs->syscfg = gdb_regs[BFIN_SYSCFG];
 164         regs->retx = gdb_regs[BFIN_PC];
 165         regs->retn = gdb_regs[BFIN_RETN];
 166         regs->rete = gdb_regs[BFIN_RETE];
 167         regs->pc = gdb_regs[BFIN_PC];
 168
 169 #if 0                           /* can't change these */
 170         regs->astat = gdb_regs[BFIN_ASTAT];
 171         regs->seqstat = gdb_regs[BFIN_SEQSTAT];
 172         regs->ipend = gdb_regs[BFIN_IPEND];
 173 #endif
 174 }
 175
 176 struct hw_breakpoint {
 177         unsigned int occupied:1;
 178         unsigned int skip:1;
 179         unsigned int enabled:1;
 180         unsigned int type:1;
 181         unsigned int dataacc:2;
 182         unsigned short count;
 183         unsigned int addr;
 184 } breakinfo[HW_WATCHPOINT_NUM];
 185
 186 int bfin_set_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
 187 {
 188         int breakno;
 189         int bfin_type;
 190         int dataacc = 0;
 191
 192         switch (type) {
 193         case BP_HARDWARE_BREAKPOINT:
 194                 bfin_type = TYPE_INST_WATCHPOINT;
 195                 break;
 196         case BP_WRITE_WATCHPOINT:
 197                 dataacc = 1;
 198                 bfin_type = TYPE_DATA_WATCHPOINT;
 199                 break;
 200         case BP_READ_WATCHPOINT:
 201                 dataacc = 2;
 202                 bfin_type = TYPE_DATA_WATCHPOINT;
 203                 break;
 204         case BP_ACCESS_WATCHPOINT:
 205                 dataacc = 3;
 206                 bfin_type = TYPE_DATA_WATCHPOINT;
 207                 break;
 208         default:
 209                 return -ENOSPC;
 210         }
 211
 212         /* Becasue hardware data watchpoint impelemented in current
 213          * Blackfin can not trigger an exception event as the hardware
 214          * instrction watchpoint does, we ignaore all data watch point here.
 215          * They can be turned on easily after future blackfin design
 216          * supports this feature.
 217          */
 218         for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
 219                 if (bfin_type == breakinfo[breakno].type
 220                         && !breakinfo[breakno].occupied) {
 221                         breakinfo[breakno].occupied = 1;
 222                         breakinfo[breakno].skip = 0;
 223                         breakinfo[breakno].enabled = 1;
 224                         breakinfo[breakno].addr = addr;
 225                         breakinfo[breakno].dataacc = dataacc;
 226                         breakinfo[breakno].count = 0;
 227                         return 0;
 228                 }
 229
 230         return -ENOSPC;
 231 }
 232
 233 int bfin_remove_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
 234 {
 235         int breakno;
 236         int bfin_type;
 237
 238         switch (type) {
 239         case BP_HARDWARE_BREAKPOINT:
 240                 bfin_type = TYPE_INST_WATCHPOINT;
 241                 break;
 242         case BP_WRITE_WATCHPOINT:
 243         case BP_READ_WATCHPOINT:
 244         case BP_ACCESS_WATCHPOINT:
 245                 bfin_type = TYPE_DATA_WATCHPOINT;
 246                 break;
 247         default:
 248                 return 0;
 249         }
 250         for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
 251                 if (bfin_type == breakinfo[breakno].type
 252                         && breakinfo[breakno].occupied
 253                         && breakinfo[breakno].addr == addr) {
 254                         breakinfo[breakno].occupied = 0;
 255                         breakinfo[breakno].enabled = 0;
 256                 }
 257
 258         return 0;
 259 }
 260
 261 void bfin_remove_all_hw_break(void)
 262 {
 263         int breakno;
 264
 265         memset(breakinfo, 0, sizeof(struct hw_breakpoint)*HW_WATCHPOINT_NUM);
 266
 267         for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
 268                 breakinfo[breakno].type = TYPE_INST_WATCHPOINT;
 269         for (; breakno < HW_WATCHPOINT_NUM; breakno++)
 270                 breakinfo[breakno].type = TYPE_DATA_WATCHPOINT;
 271 }
 272
 273 void bfin_correct_hw_break(void)
 274 {
 275         int breakno;
 276         unsigned int wpiactl = 0;
 277         unsigned int wpdactl = 0;
 278         int enable_wp = 0;
 279
 280         for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
 281                 if (breakinfo[breakno].enabled) {
 282                         enable_wp = 1;
 283
 284                         switch (breakno) {
 285                         case 0:
 286                                 wpiactl |= WPIAEN0|WPICNTEN0;
 287                                 bfin_write_WPIA0(breakinfo[breakno].addr);
 288                                 bfin_write_WPIACNT0(breakinfo[breakno].count
 289                                         + breakinfo->skip);
 290                                 break;
 291                         case 1:
 292                                 wpiactl |= WPIAEN1|WPICNTEN1;
 293                                 bfin_write_WPIA1(breakinfo[breakno].addr);
 294                                 bfin_write_WPIACNT1(breakinfo[breakno].count
 295                                         + breakinfo->skip);
 296                                 break;
 297                         case 2:
 298                                 wpiactl |= WPIAEN2|WPICNTEN2;
 299                                 bfin_write_WPIA2(breakinfo[breakno].addr);
 300                                 bfin_write_WPIACNT2(breakinfo[breakno].count
 301                                         + breakinfo->skip);
 302                                 break;
 303                         case 3:
 304                                 wpiactl |= WPIAEN3|WPICNTEN3;
 305                                 bfin_write_WPIA3(breakinfo[breakno].addr);
 306                                 bfin_write_WPIACNT3(breakinfo[breakno].count
 307                                         + breakinfo->skip);
 308                                 break;
 309                         case 4:
 310                                 wpiactl |= WPIAEN4|WPICNTEN4;
 311                                 bfin_write_WPIA4(breakinfo[breakno].addr);
 312                                 bfin_write_WPIACNT4(breakinfo[breakno].count
 313                                         + breakinfo->skip);
 314                                 break;
 315                         case 5:
 316                                 wpiactl |= WPIAEN5|WPICNTEN5;
 317                                 bfin_write_WPIA5(breakinfo[breakno].addr);
 318                                 bfin_write_WPIACNT5(breakinfo[breakno].count
 319                                         + breakinfo->skip);
 320                                 break;
 321                         case 6:
 322                                 wpdactl |= WPDAEN0|WPDCNTEN0|WPDSRC0;
 323                                 wpdactl |= breakinfo[breakno].dataacc
 324                                         << WPDACC0_OFFSET;
 325                                 bfin_write_WPDA0(breakinfo[breakno].addr);
 326                                 bfin_write_WPDACNT0(breakinfo[breakno].count
 327                                         + breakinfo->skip);
 328                                 break;
 329                         case 7:
 330                                 wpdactl |= WPDAEN1|WPDCNTEN1|WPDSRC1;
 331                                 wpdactl |= breakinfo[breakno].dataacc
 332                                         << WPDACC1_OFFSET;
 333                                 bfin_write_WPDA1(breakinfo[breakno].addr);
 334                                 bfin_write_WPDACNT1(breakinfo[breakno].count
 335                                         + breakinfo->skip);
 336                                 break;
 337                         }
 338                 }
 339
 340         /* Should enable WPPWR bit first before set any other
 341          * WPIACTL and WPDACTL bits */
 342         if (enable_wp) {
 343                 bfin_write_WPIACTL(WPPWR);
 344                 CSYNC();
 345                 bfin_write_WPIACTL(wpiactl|WPPWR);
 346                 bfin_write_WPDACTL(wpdactl);
 347                 CSYNC();
 348         }
 349 }
 350
 351 void kgdb_disable_hw_debug(struct pt_regs *regs)
 352 {
 353         /* Disable hardware debugging while we are in kgdb */
 354         bfin_write_WPIACTL(0);
 355         bfin_write_WPDACTL(0);
 356         CSYNC();
 357 }
 358
 359 #ifdef CONFIG_SMP
 360 void kgdb_passive_cpu_callback(void *info)
 361 {
 362         kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs());
 363 }
 364
 365 void kgdb_roundup_cpus(unsigned long flags)
 366 {
 367         smp_call_function(kgdb_passive_cpu_callback, NULL, 0);
 368 }
 369
 370 void kgdb_roundup_cpu(int cpu, unsigned long flags)
 371 {
 372         smp_call_function_single(cpu, kgdb_passive_cpu_callback, NULL, 0);
 373 }
 374 #endif
 375
 376 void kgdb_post_primary_code(struct pt_regs *regs, int eVector, int err_code)
 377 {
 378         /* Master processor is completely in the debugger */
 379         gdb_bfin_vector = eVector;
 380         gdb_bfin_errcode = err_code;
 381 }
 382
 383 int kgdb_arch_handle_exception(int vector, int signo,
 384                                int err_code, char *remcom_in_buffer,
 385                                char *remcom_out_buffer,
 386                                struct pt_regs *regs)
 387 {
 388         long addr;
 389         long breakno;
 390         char *ptr;
 391         int newPC;
 392         int wp_status;
 393         int i;
 394
 395         switch (remcom_in_buffer[0]) {
 396         case 'c':
 397         case 's':
 398                 if (kgdb_contthread && kgdb_contthread != current) {
 399                         strcpy(remcom_out_buffer, "E00");
 400                         break;
 401                 }
 402
 403                 kgdb_contthread = NULL;
 404
 405                 /* try to read optional parameter, pc unchanged if no parm */
 406                 ptr = &remcom_in_buffer[1];
 407                 if (kgdb_hex2long(&ptr, &addr)) {
 408                         regs->retx = addr;
 409                 }
 410                 newPC = regs->retx;
 411
 412                 /* clear the trace bit */
 413                 regs->syscfg &= 0xfffffffe;
 414
 415                 /* set the trace bit if we're stepping */
 416                 if (remcom_in_buffer[0] == 's') {
 417                         regs->syscfg |= 0x1;
 418                         kgdb_single_step = regs->ipend;
 419                         kgdb_single_step >>= 6;
 420                         for (i = 10; i > 0; i--, kgdb_single_step >>= 1)
 421                                 if (kgdb_single_step & 1)
 422                                         break;
 423                         /* i indicate event priority of current stopped instruction
 424                          * user space instruction is 0, IVG15 is 1, IVTMR is 10.
 425                          * kgdb_single_step > 0 means in single step mode
 426                          */
 427                         kgdb_single_step = i + 1;
 428                 }
 429
 430                 bfin_correct_hw_break();
 431
 432                 return 0;
 433         }                       /* switch */
 434         return -1;              /* this means that we do not want to exit from the handler */
 435 }
 436
 437 struct kgdb_arch arch_kgdb_ops = {
 438         .gdb_bpt_instr = {0xa1},
 439 #ifdef CONFIG_SMP
 440         .flags = KGDB_HW_BREAKPOINT|KGDB_THR_PROC_SWAP,
 441 #else
 442         .flags = KGDB_HW_BREAKPOINT,
 443 #endif
 444         .set_hw_breakpoint = bfin_set_hw_break,
 445         .remove_hw_breakpoint = bfin_remove_hw_break,
 446         .remove_all_hw_break = bfin_remove_all_hw_break,
 447         .correct_hw_break = bfin_correct_hw_break,
 448 };
 449
 450 static int hex(char ch)
 451 {
 452         if ((ch >= 'a') && (ch <= 'f'))
 453                 return ch - 'a' + 10;
 454         if ((ch >= '0') && (ch <= '9'))
 455                 return ch - '0';
 456         if ((ch >= 'A') && (ch <= 'F'))
 457                 return ch - 'A' + 10;
 458         return -1;
 459 }
 460
 461 static int validate_memory_access_address(unsigned long addr, int size)
 462 {
 463         int cpu = raw_smp_processor_id();
 464
 465         if (size < 0)
 466                 return EFAULT;
 467         if (addr >= 0x1000 && (addr + size) <= physical_mem_end)
 468                 return 0;
 469         if (addr >= SYSMMR_BASE)
 470                 return 0;
 471         if (addr >= ASYNC_BANK0_BASE
 472            && addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
 473                 return 0;
 474         if (cpu == 0) {
 475                 if (addr >= L1_SCRATCH_START
 476                    && (addr + size <= L1_SCRATCH_START + L1_SCRATCH_LENGTH))
 477                         return 0;
 478 #if L1_CODE_LENGTH != 0
 479                 if (addr >= L1_CODE_START
 480                    && (addr + size <= L1_CODE_START + L1_CODE_LENGTH))
 481                         return 0;
 482 #endif
 483 #if L1_DATA_A_LENGTH != 0
 484                 if (addr >= L1_DATA_A_START
 485                    && (addr + size <= L1_DATA_A_START + L1_DATA_A_LENGTH))
 486                         return 0;
 487 #endif
 488 #if L1_DATA_B_LENGTH != 0
 489                 if (addr >= L1_DATA_B_START
 490                    && (addr + size <= L1_DATA_B_START + L1_DATA_B_LENGTH))
 491                         return 0;
 492 #endif
 493 #ifdef CONFIG_SMP
 494         } else if (cpu == 1) {
 495                 if (addr >= COREB_L1_SCRATCH_START
 496                    && (addr + size <= COREB_L1_SCRATCH_START
 497                    + L1_SCRATCH_LENGTH))
 498                         return 0;
 499 # if L1_CODE_LENGTH != 0
 500                 if (addr >= COREB_L1_CODE_START
 501                    && (addr + size <= COREB_L1_CODE_START + L1_CODE_LENGTH))
 502                         return 0;
 503 # endif
 504 # if L1_DATA_A_LENGTH != 0
 505                 if (addr >= COREB_L1_DATA_A_START
 506                    && (addr + size <= COREB_L1_DATA_A_START + L1_DATA_A_LENGTH))
 507                         return 0;
 508 # endif
 509 # if L1_DATA_B_LENGTH != 0
 510                 if (addr >= COREB_L1_DATA_B_START
 511                    && (addr + size <= COREB_L1_DATA_B_START + L1_DATA_B_LENGTH))
 512                         return 0;
 513 # endif
 514 #endif
 515         }
 516
 517 #if L2_LENGTH != 0
 518         if (addr >= L2_START
 519            && addr + size <= L2_START + L2_LENGTH)
 520                 return 0;
 521 #endif
 522
 523         return EFAULT;
 524 }
 525
 526 /*
 527  * Convert the memory pointed to by mem into hex, placing result in buf.
 528  * Return a pointer to the last char put in buf (null). May return an error.
 529  */
 530 int kgdb_mem2hex(char *mem, char *buf, int count)
 531 {
 532         char *tmp;
 533         int err = 0;
 534         unsigned char *pch;
 535         unsigned short mmr16;
 536         unsigned long mmr32;
 537         int cpu = raw_smp_processor_id();
 538
 539         if (validate_memory_access_address((unsigned long)mem, count))
 540                 return EFAULT;
 541
 542         /*
 543          * We use the upper half of buf as an intermediate buffer for the
 544          * raw memory copy.  Hex conversion will work against this one.
 545          */
 546         tmp = buf + count;
 547
 548         if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/
 549                 switch (count) {
 550                 case 2:
 551                         if ((unsigned int)mem % 2 == 0) {
 552                                 mmr16 = *(unsigned short *)mem;
 553                                 pch = (unsigned char *)&mmr16;
 554                                 *tmp++ = *pch++;
 555                                 *tmp++ = *pch++;
 556                                 tmp -= 2;
 557                         } else
 558                                 err = EFAULT;
 559                         break;
 560                 case 4:
 561                         if ((unsigned int)mem % 4 == 0) {
 562                                 mmr32 = *(unsigned long *)mem;
 563                                 pch = (unsigned char *)&mmr32;
 564                                 *tmp++ = *pch++;
 565                                 *tmp++ = *pch++;
 566                                 *tmp++ = *pch++;
 567                                 *tmp++ = *pch++;
 568                                 tmp -= 4;
 569                         } else
 570                                 err = EFAULT;
 571                         break;
 572                 default:
 573                         err = EFAULT;
 574                 }
 575         } else if (cpu == 0 && (unsigned int)mem >= L1_CODE_START &&
 576                 (unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH
 577 #ifdef CONFIG_SMP
 578                 || cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START &&
 579                 (unsigned int)(mem + count) <=
 580                 COREB_L1_CODE_START + L1_CODE_LENGTH
 581 #endif
 582                 ) {
 583                 /* access L1 instruction SRAM*/
 584                 if (dma_memcpy(tmp, mem, count) == NULL)
 585                         err = EFAULT;
 586         } else
 587                 err = probe_kernel_read(tmp, mem, count);
 588
 589         if (!err) {
 590                 while (count > 0) {
 591                         buf = pack_hex_byte(buf, *tmp);
 592                         tmp++;
 593                         count--;
 594                 }
 595
 596                 *buf = 0;
 597         }
 598
 599         return err;
 600 }
 601
 602 /*
 603  * Copy the binary array pointed to by buf into mem.  Fix $, #, and
 604  * 0x7d escaped with 0x7d.  Return a pointer to the character after
 605  * the last byte written.
 606  */
 607 int kgdb_ebin2mem(char *buf, char *mem, int count)
 608 {
 609         char *tmp_old;
 610         char *tmp_new;
 611         unsigned short *mmr16;
 612         unsigned long *mmr32;
 613         int err = 0;
 614         int size = 0;
 615         int cpu = raw_smp_processor_id();
 616
 617         tmp_old = tmp_new = buf;
 618
 619         while (count-- > 0) {
 620                 if (*tmp_old == 0x7d)
 621                         *tmp_new = *(++tmp_old) ^ 0x20;
 622                 else
 623                         *tmp_new = *tmp_old;
 624                 tmp_new++;
 625                 tmp_old++;
 626                 size++;
 627         }
 628
 629         if (validate_memory_access_address((unsigned long)mem, size))
 630                 return EFAULT;
 631
 632         if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/
 633                 switch (size) {
 634                 case 2:
 635                         if ((unsigned int)mem % 2 == 0) {
 636                                 mmr16 = (unsigned short *)buf;
 637                                 *(unsigned short *)mem = *mmr16;
 638                         } else
 639                                 return EFAULT;
 640                         break;
 641                 case 4:
 642                         if ((unsigned int)mem % 4 == 0) {
 643                                 mmr32 = (unsigned long *)buf;
 644                                 *(unsigned long *)mem = *mmr32;
 645                         } else
 646                                 return EFAULT;
 647                         break;
 648                 default:
 649                         return EFAULT;
 650                 }
 651         } else if (cpu == 0 && (unsigned int)mem >= L1_CODE_START &&
 652                 (unsigned int)(mem + count) < L1_CODE_START + L1_CODE_LENGTH
 653 #ifdef CONFIG_SMP
 654                 || cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START &&
 655                 (unsigned int)(mem + count) <=
 656                 COREB_L1_CODE_START + L1_CODE_LENGTH
 657 #endif
 658                 ) {
 659                 /* access L1 instruction SRAM */
 660                 if (dma_memcpy(mem, buf, size) == NULL)
 661                         err = EFAULT;
 662         } else
 663                 err = probe_kernel_write(mem, buf, size);
 664
 665         return err;
 666 }
 667
 668 /*
 669  * Convert the hex array pointed to by buf into binary to be placed in mem.
 670  * Return a pointer to the character AFTER the last byte written.
 671  * May return an error.
 672  */
 673 int kgdb_hex2mem(char *buf, char *mem, int count)
 674 {
 675         char *tmp_raw;
 676         char *tmp_hex;
 677         unsigned short *mmr16;
 678         unsigned long *mmr32;
 679         int cpu = raw_smp_processor_id();
 680
 681         if (validate_memory_access_address((unsigned long)mem, count))
 682                 return EFAULT;
 683
 684         /*
 685          * We use the upper half of buf as an intermediate buffer for the
 686          * raw memory that is converted from hex.
 687          */
 688         tmp_raw = buf + count * 2;
 689
 690         tmp_hex = tmp_raw - 1;
 691         while (tmp_hex >= buf) {
 692                 tmp_raw--;
 693                 *tmp_raw = hex(*tmp_hex--);
 694                 *tmp_raw |= hex(*tmp_hex--) << 4;
 695         }
 696
 697         if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/
 698                 switch (count) {
 699                 case 2:
 700                         if ((unsigned int)mem % 2 == 0) {
 701                                 mmr16 = (unsigned short *)tmp_raw;
 702                                 *(unsigned short *)mem = *mmr16;
 703                         } else
 704                                 return EFAULT;
 705                         break;
 706                 case 4:
 707                         if ((unsigned int)mem % 4 == 0) {
 708                                 mmr32 = (unsigned long *)tmp_raw;
 709                                 *(unsigned long *)mem = *mmr32;
 710                         } else
 711                                 return EFAULT;
 712                         break;
 713                 default:
 714                         return EFAULT;
 715                 }
 716         } else if (cpu == 0 && (unsigned int)mem >= L1_CODE_START &&
 717                 (unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH
 718 #ifdef CONFIG_SMP
 719                 || cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START &&
 720                 (unsigned int)(mem + count) <=
 721                 COREB_L1_CODE_START + L1_CODE_LENGTH
 722 #endif
 723                 ) {
 724                 /* access L1 instruction SRAM */
 725                 if (dma_memcpy(mem, tmp_raw, count) == NULL)
 726                         return EFAULT;
 727         } else
 728                 return probe_kernel_write(mem, tmp_raw, count);
 729         return 0;
 730 }
 731
 732 int kgdb_validate_break_address(unsigned long addr)
 733 {
 734         int cpu = raw_smp_processor_id();
 735
 736         if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end)
 737                 return 0;
 738         if (addr >= ASYNC_BANK0_BASE
 739            && addr + BREAK_INSTR_SIZE <= ASYNC_BANK3_BASE + ASYNC_BANK3_BASE)
 740                 return 0;
 741 #if L1_CODE_LENGTH != 0
 742         if (cpu == 0 && addr >= L1_CODE_START
 743            && addr + BREAK_INSTR_SIZE <= L1_CODE_START + L1_CODE_LENGTH)
 744                 return 0;
 745 # ifdef CONFIG_SMP
 746         else if (cpu == 1 && addr >= COREB_L1_CODE_START
 747            && addr + BREAK_INSTR_SIZE <= COREB_L1_CODE_START + L1_CODE_LENGTH)
 748                 return 0;
 749 # endif
 750 #endif
 751 #if L2_LENGTH != 0
 752         if (addr >= L2_START
 753            && addr + BREAK_INSTR_SIZE <= L2_START + L2_LENGTH)
 754                 return 0;
 755 #endif
 756
 757         return EFAULT;
 758 }
 759
 760 int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr)
 761 {
 762         int err;
 763         int cpu = raw_smp_processor_id();
 764
 765         if ((cpu == 0 && (unsigned int)addr >= L1_CODE_START
 766                 && (unsigned int)(addr + BREAK_INSTR_SIZE)
 767                 < L1_CODE_START + L1_CODE_LENGTH)
 768 #ifdef CONFIG_SMP
 769                 || (cpu == 1 && (unsigned int)addr >= COREB_L1_CODE_START
 770                 && (unsigned int)(addr + BREAK_INSTR_SIZE)
 771                 < COREB_L1_CODE_START + L1_CODE_LENGTH)
 772 #endif
 773                 ) {
 774                 /* access L1 instruction SRAM */
 775                 if (dma_memcpy(saved_instr, (void *)addr, BREAK_INSTR_SIZE)
 776                         == NULL)
 777                         return -EFAULT;
 778
 779                 if (dma_memcpy((void *)addr, arch_kgdb_ops.gdb_bpt_instr,
 780                         BREAK_INSTR_SIZE) == NULL)
 781                         return -EFAULT;
 782
 783                 return 0;
 784         } else {
 785                 err = probe_kernel_read(saved_instr, (char *)addr,
 786                         BREAK_INSTR_SIZE);
 787                 if (err)
 788                         return err;
 789
 790                 return probe_kernel_write((char *)addr,
 791                         arch_kgdb_ops.gdb_bpt_instr, BREAK_INSTR_SIZE);
 792         }
 793 }
 794
 795 int kgdb_arch_remove_breakpoint(unsigned long addr, char *bundle)
 796 {
 797         if ((unsigned int)addr >= L1_CODE_START &&
 798                 (unsigned int)(addr + BREAK_INSTR_SIZE) <
 799                         L1_CODE_START + L1_CODE_LENGTH) {
 800                 /* access L1 instruction SRAM */
 801                 if (dma_memcpy((void *)addr, bundle, BREAK_INSTR_SIZE) == NULL)
 802                         return -EFAULT;
 803
 804                 return 0;
 805         } else
 806                 return probe_kernel_write((char *)addr,
 807                                 (char *)bundle, BREAK_INSTR_SIZE);
 808 }
 809
 810 int kgdb_arch_init(void)
 811 {
 812         kgdb_single_step = 0;
 813
 814         bfin_remove_all_hw_break();
 815         return 0;
 816 }
 817
 818 void kgdb_arch_exit(void)
 819 {
 820 }