2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
16 config RWSEM_GENERIC_SPINLOCK
20 config RWSEM_XCHGADD_ALGORITHM
34 config GENERIC_FIND_NEXT_BIT
38 config GENERIC_HWEIGHT
42 config GENERIC_HARDIRQS
46 config GENERIC_IRQ_PROBE
54 config FORCE_MAX_ZONEORDER
58 config GENERIC_CALIBRATE_DELAY
67 source "kernel/Kconfig.preempt"
69 menu "Blackfin Processor Options"
71 comment "Processor and Board Settings"
80 BF522 Processor Support.
85 BF523 Processor Support.
90 BF524 Processor Support.
95 BF525 Processor Support.
100 BF526 Processor Support.
105 BF527 Processor Support.
110 BF531 Processor Support.
115 BF532 Processor Support.
120 BF533 Processor Support.
125 BF534 Processor Support.
130 BF536 Processor Support.
135 BF537 Processor Support.
140 BF542 Processor Support.
145 BF544 Processor Support.
150 BF547 Processor Support.
155 BF548 Processor Support.
160 BF549 Processor Support.
165 Not Supported Yet - Work in progress - BF561 Processor Support.
171 default BF_REV_0_1 if BF527
172 default BF_REV_0_2 if BF537
173 default BF_REV_0_3 if BF533
174 default BF_REV_0_0 if BF549
178 depends on (BF52x || BF54x)
182 depends on (BF52x || BF54x)
186 depends on (BF537 || BF536 || BF534)
190 depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
194 depends on (BF561 || BF533 || BF532 || BF531)
198 depends on (BF561 || BF533 || BF532 || BF531)
210 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
215 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
220 depends on (BF542 || BF544 || BF547 || BF548 || BF549)
223 config MEM_GENERIC_BOARD
225 depends on GENERIC_BOARD
228 config MEM_MT48LC64M4A2FB_7E
230 depends on (BFIN533_STAMP)
233 config MEM_MT48LC16M16A2TG_75
235 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
236 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
240 config MEM_MT48LC32M8A2_75
242 depends on (BFIN537_STAMP || PNAV10)
245 config MEM_MT48LC8M32B2B5_7
247 depends on (BFIN561_BLUETECHNIX_CM)
250 config MEM_MT48LC32M16A2TG_75
252 depends on (BFIN527_EZKIT || BFIN532_IP0X)
255 source "arch/blackfin/mach-bf527/Kconfig"
256 source "arch/blackfin/mach-bf533/Kconfig"
257 source "arch/blackfin/mach-bf561/Kconfig"
258 source "arch/blackfin/mach-bf537/Kconfig"
259 source "arch/blackfin/mach-bf548/Kconfig"
261 menu "Board customizations"
264 bool "Default bootloader kernel arguments"
267 string "Initial kernel command string"
268 depends on CMDLINE_BOOL
269 default "console=ttyBF0,57600"
271 If you don't have a boot loader capable of passing a command line string
272 to the kernel, you may specify one here. As a minimum, you should specify
273 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
276 hex "Kernel load address for booting"
278 range 0x1000 0x20000000
280 This option allows you to set the load address of the kernel.
281 This can be useful if you are on a board which has a small amount
282 of memory or you wish to reserve some memory at the beginning of
285 Note that you need to keep this value above 4k (0x1000) as this
286 memory region is used to capture NULL pointer references as well
287 as some core kernel functions.
289 comment "Clock/PLL Setup"
292 int "Frequency of the crystal on the board in Hz"
293 default "11059200" if BFIN533_STAMP
294 default "27000000" if BFIN533_EZKIT
295 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
296 default "30000000" if BFIN561_EZKIT
297 default "24576000" if PNAV10
298 default "10000000" if BFIN532_IP0X
300 The frequency of CLKIN crystal oscillator on the board in Hz.
301 Warning: This value should match the crystal on the board. Otherwise,
302 peripherals won't work properly.
304 config BFIN_KERNEL_CLOCK
305 bool "Re-program Clocks while Kernel boots?"
308 This option decides if kernel clocks are re-programed from the
309 bootloader settings. If the clocks are not set, the SDRAM settings
310 are also not changed, and the Bootloader does 100% of the hardware
314 int "SDRAM Memory Size in MBytes"
315 depends on BFIN_KERNEL_CLOCK
319 int "Memory Address Width"
320 depends on BFIN_KERNEL_CLOCK
323 default 9 if BFIN533_EZKIT
324 default 9 if BFIN561_EZKIT
325 default 9 if H8606_HVSISTEMAS
326 default 10 if BFIN527_EZKIT
327 default 10 if BFIN537_STAMP
328 default 11 if BFIN533_STAMP
330 default 10 if BFIN532_IP0X
334 depends on BFIN_KERNEL_CLOCK
339 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
342 If this is set the clock will be divided by 2, before it goes to the PLL.
346 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
348 default "22" if BFIN533_EZKIT
349 default "45" if BFIN533_STAMP
350 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
351 default "22" if BFIN533_BLUETECHNIX_CM
352 default "20" if BFIN537_BLUETECHNIX_CM
353 default "20" if BFIN561_BLUETECHNIX_CM
354 default "20" if BFIN561_EZKIT
355 default "16" if H8606_HVSISTEMAS
357 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
358 PLL Frequency = (Crystal Frequency) * (this setting)
361 prompt "Core Clock Divider"
362 depends on BFIN_KERNEL_CLOCK
365 This sets the frequency of the core. It can be 1, 2, 4 or 8
366 Core Frequency = (PLL frequency) / (this setting)
382 int "System Clock Divider"
383 depends on BFIN_KERNEL_CLOCK
387 This sets the frequency of the system clock (including SDRAM or DDR).
388 This can be between 1 and 15
389 System Clock = (PLL frequency) / (this setting)
392 int "Max SDRAM Memory Size in MBytes"
393 depends on !BFIN_KERNEL_CLOCK && !MPU
396 This is the max memory size that the kernel will create CPLB
397 tables for. Your system will not be able to handle any more.
400 prompt "DDR SDRAM Chip Type"
401 depends on BFIN_KERNEL_CLOCK
403 default MEM_MT46V32M16_5B
405 config MEM_MT46V32M16_6T
408 config MEM_MT46V32M16_5B
413 # Max & Min Speeds for various Chips
417 default 600000000 if BF522
418 default 400000000 if BF523
419 default 400000000 if BF524
420 default 600000000 if BF525
421 default 400000000 if BF526
422 default 600000000 if BF527
423 default 400000000 if BF531
424 default 400000000 if BF532
425 default 750000000 if BF533
426 default 500000000 if BF534
427 default 400000000 if BF536
428 default 600000000 if BF537
429 default 533333333 if BF538
430 default 533333333 if BF539
431 default 600000000 if BF542
432 default 533333333 if BF544
433 default 600000000 if BF547
434 default 600000000 if BF548
435 default 533333333 if BF549
436 default 600000000 if BF561
450 comment "Kernel Timer/Scheduler"
452 source kernel/Kconfig.hz
458 config GENERIC_CLOCKEVENTS
459 bool "Generic clock events"
460 depends on GENERIC_TIME
463 config CYCLES_CLOCKSOURCE
464 bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
465 depends on EXPERIMENTAL
466 depends on GENERIC_CLOCKEVENTS
467 depends on !BFIN_SCRATCH_REG_CYCLES
470 If you say Y here, you will enable support for using the 'cycles'
471 registers as a clock source. Doing so means you will be unable to
472 safely write to the 'cycles' register during runtime. You will
473 still be able to read it (such as for performance monitoring), but
474 writing the registers will most likely crash the kernel.
476 source kernel/time/Kconfig
478 comment "Memory Setup"
483 prompt "Blackfin Exception Scratch Register"
484 default BFIN_SCRATCH_REG_RETN
486 Select the resource to reserve for the Exception handler:
487 - RETN: Non-Maskable Interrupt (NMI)
488 - RETE: Exception Return (JTAG/ICE)
489 - CYCLES: Performance counter
491 If you are unsure, please select "RETN".
493 config BFIN_SCRATCH_REG_RETN
496 Use the RETN register in the Blackfin exception handler
497 as a stack scratch register. This means you cannot
498 safely use NMI on the Blackfin while running Linux, but
499 you can debug the system with a JTAG ICE and use the
500 CYCLES performance registers.
502 If you are unsure, please select "RETN".
504 config BFIN_SCRATCH_REG_RETE
507 Use the RETE register in the Blackfin exception handler
508 as a stack scratch register. This means you cannot
509 safely use a JTAG ICE while debugging a Blackfin board,
510 but you can safely use the CYCLES performance registers
513 If you are unsure, please select "RETN".
515 config BFIN_SCRATCH_REG_CYCLES
518 Use the CYCLES register in the Blackfin exception handler
519 as a stack scratch register. This means you cannot
520 safely use the CYCLES performance registers on a Blackfin
521 board at anytime, but you can debug the system with a JTAG
524 If you are unsure, please select "RETN".
531 menu "Blackfin Kernel Optimizations"
533 comment "Memory Optimizations"
536 bool "Locate interrupt entry code in L1 Memory"
539 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
540 into L1 instruction memory. (less latency)
542 config EXCPT_IRQ_SYSC_L1
543 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
546 If enabled, the entire ASM lowlevel exception and interrupt entry code
547 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
551 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
554 If enabled, the frequently called do_irq dispatcher function is linked
555 into L1 instruction memory. (less latency)
557 config CORE_TIMER_IRQ_L1
558 bool "Locate frequently called timer_interrupt() function in L1 Memory"
561 If enabled, the frequently called timer_interrupt() function is linked
562 into L1 instruction memory. (less latency)
565 bool "Locate frequently idle function in L1 Memory"
568 If enabled, the frequently called idle function is linked
569 into L1 instruction memory. (less latency)
572 bool "Locate kernel schedule function in L1 Memory"
575 If enabled, the frequently called kernel schedule is linked
576 into L1 instruction memory. (less latency)
578 config ARITHMETIC_OPS_L1
579 bool "Locate kernel owned arithmetic functions in L1 Memory"
582 If enabled, arithmetic functions are linked
583 into L1 instruction memory. (less latency)
586 bool "Locate access_ok function in L1 Memory"
589 If enabled, the access_ok function is linked
590 into L1 instruction memory. (less latency)
593 bool "Locate memset function in L1 Memory"
596 If enabled, the memset function is linked
597 into L1 instruction memory. (less latency)
600 bool "Locate memcpy function in L1 Memory"
603 If enabled, the memcpy function is linked
604 into L1 instruction memory. (less latency)
606 config SYS_BFIN_SPINLOCK_L1
607 bool "Locate sys_bfin_spinlock function in L1 Memory"
610 If enabled, sys_bfin_spinlock function is linked
611 into L1 instruction memory. (less latency)
613 config IP_CHECKSUM_L1
614 bool "Locate IP Checksum function in L1 Memory"
617 If enabled, the IP Checksum function is linked
618 into L1 instruction memory. (less latency)
620 config CACHELINE_ALIGNED_L1
621 bool "Locate cacheline_aligned data to L1 Data Memory"
626 If enabled, cacheline_anligned data is linked
627 into L1 data memory. (less latency)
629 config SYSCALL_TAB_L1
630 bool "Locate Syscall Table L1 Data Memory"
634 If enabled, the Syscall LUT is linked
635 into L1 data memory. (less latency)
637 config CPLB_SWITCH_TAB_L1
638 bool "Locate CPLB Switch Tables L1 Data Memory"
642 If enabled, the CPLB Switch Tables are linked
643 into L1 data memory. (less latency)
649 prompt "Kernel executes from"
651 Choose the memory type that the kernel will be running in.
656 The kernel will be resident in RAM when running.
661 The kernel will be resident in FLASH/ROM when running.
668 tristate "Enable Blackfin General Purpose Timers API"
671 Enable support for the General Purpose Timers API. If you
674 To compile this driver as a module, choose M here: the module
675 will be called gptimers.ko.
678 bool "Enable DMA Support"
679 depends on (BF52x || BF53x || BF561 || BF54x)
682 DMA driver for BF5xx.
685 prompt "Uncached SDRAM region"
686 default DMA_UNCACHED_1M
687 depends on BFIN_DMA_5XX
688 config DMA_UNCACHED_2M
689 bool "Enable 2M DMA region"
690 config DMA_UNCACHED_1M
691 bool "Enable 1M DMA region"
692 config DMA_UNCACHED_NONE
693 bool "Disable DMA region"
697 comment "Cache Support"
702 config BFIN_DCACHE_BANKA
703 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
704 depends on BFIN_DCACHE && !BF531
706 config BFIN_ICACHE_LOCK
707 bool "Enable Instruction Cache Locking"
711 depends on BFIN_DCACHE
717 Cached data will be written back to SDRAM only when needed.
718 This can give a nice increase in performance, but beware of
719 broken drivers that do not properly invalidate/flush their
722 Write Through Policy:
723 Cached data will always be written back to SDRAM when the
724 cache is updated. This is a completely safe setting, but
725 performance is worse than Write Back.
727 If you are unsure of the options and you want to be safe,
728 then go with Write Through.
734 Cached data will be written back to SDRAM only when needed.
735 This can give a nice increase in performance, but beware of
736 broken drivers that do not properly invalidate/flush their
739 Write Through Policy:
740 Cached data will always be written back to SDRAM when the
741 cache is updated. This is a completely safe setting, but
742 performance is worse than Write Back.
744 If you are unsure of the options and you want to be safe,
745 then go with Write Through.
750 int "Set the max L1 SRAM pieces"
753 Set the max memory pieces for the L1 SRAM allocation algorithm.
754 Min value is 16. Max value is 1024.
758 bool "Enable the memory protection unit (EXPERIMENTAL)"
761 Use the processor's MPU to protect applications from accessing
762 memory they do not own. This comes at a performance penalty
763 and is recommended only for debugging.
765 comment "Asynchonous Memory Configuration"
767 menu "EBIU_AMGCTL Global Control"
773 bool "DMA has priority over core for ext. accesses"
778 bool "Bank 0 16 bit packing enable"
783 bool "Bank 1 16 bit packing enable"
788 bool "Bank 2 16 bit packing enable"
793 bool "Bank 3 16 bit packing enable"
797 prompt"Enable Asynchonous Memory Banks"
801 bool "Disable All Banks"
807 bool "Enable Bank 0 & 1"
809 config C_AMBEN_B0_B1_B2
810 bool "Enable Bank 0 & 1 & 2"
813 bool "Enable All Banks"
817 menu "EBIU_AMBCTL Control"
825 default 0x5558 if BF54x
836 config EBIU_MBSCTLVAL
837 hex "EBIU Bank Select Control Register"
842 hex "Flash Memory Mode Control Register"
847 hex "Flash Memory Bank Control Register"
852 #############################################################################
853 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
860 source "drivers/pci/Kconfig"
863 bool "Support for hot-pluggable device"
865 Say Y here if you want to plug devices into your computer while
866 the system is running, and be able to use them quickly. In many
867 cases, the devices can likewise be unplugged at any time too.
869 One well known example of this is PCMCIA- or PC-cards, credit-card
870 size devices such as network cards, modems or hard drives which are
871 plugged into slots found on all modern laptop computers. Another
872 example, used on modern desktops as well as laptops, is USB.
874 Enable HOTPLUG and KMOD, and build a modular kernel. Get agent
875 software (at <http://linux-hotplug.sourceforge.net/>) and install it.
876 Then your kernel will automatically call out to a user mode "policy
877 agent" (/sbin/hotplug) to load modules and set up software needed
878 to use devices as you hotplug them.
880 source "drivers/pcmcia/Kconfig"
882 source "drivers/pci/hotplug/Kconfig"
886 menu "Executable file formats"
888 source "fs/Kconfig.binfmt"
892 menu "Power management options"
893 source "kernel/power/Kconfig"
895 config ARCH_SUSPEND_POSSIBLE
900 prompt "Default Power Saving Mode"
902 default PM_BFIN_SLEEP_DEEPER
903 config PM_BFIN_SLEEP_DEEPER
906 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
907 power dissipation by disabling the clock to the processor core (CCLK).
908 Furthermore, Standby sets the internal power supply voltage (VDDINT)
909 to 0.85 V to provide the greatest power savings, while preserving the
911 The PLL and system clock (SCLK) continue to operate at a very low
912 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
913 the SDRAM is put into Self Refresh Mode. Typically an external event
914 such as GPIO interrupt or RTC activity wakes up the processor.
915 Various Peripherals such as UART, SPORT, PPI may not function as
916 normal during Sleep Deeper, due to the reduced SCLK frequency.
917 When in the sleep mode, system DMA access to L1 memory is not supported.
922 Sleep Mode (High Power Savings) - The sleep mode reduces power
923 dissipation by disabling the clock to the processor core (CCLK).
924 The PLL and system clock (SCLK), however, continue to operate in
925 this mode. Typically an external event or RTC activity will wake
926 up the processor. When in the sleep mode,
927 system DMA access to L1 memory is not supported.
930 config PM_WAKEUP_BY_GPIO
931 bool "Cause Wakeup Event by GPIO"
933 config PM_WAKEUP_GPIO_NUMBER
934 int "Wakeup GPIO number"
936 depends on PM_WAKEUP_BY_GPIO
937 default 2 if BFIN537_STAMP
940 prompt "GPIO Polarity"
941 depends on PM_WAKEUP_BY_GPIO
942 default PM_WAKEUP_GPIO_POLAR_H
943 config PM_WAKEUP_GPIO_POLAR_H
945 config PM_WAKEUP_GPIO_POLAR_L
947 config PM_WAKEUP_GPIO_POLAR_EDGE_F
949 config PM_WAKEUP_GPIO_POLAR_EDGE_R
951 config PM_WAKEUP_GPIO_POLAR_EDGE_B
957 menu "CPU Frequency scaling"
959 source "drivers/cpufreq/Kconfig"
962 bool "CPU Voltage scaling"
963 depends on EXPERIMENTAL
967 Say Y here if you want CPU voltage scaling according to the CPU frequency.
968 This option violates the PLL BYPASS recommendation in the Blackfin Processor
969 manuals. There is a theoretical risk that during VDDINT transitions
976 source "drivers/Kconfig"
980 source "arch/blackfin/Kconfig.debug"
982 source "security/Kconfig"
984 source "crypto/Kconfig"