2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
16 config RWSEM_GENERIC_SPINLOCK
20 config RWSEM_XCHGADD_ALGORITHM
29 select ARCH_WANT_OPTIONAL_GPIOLIB
39 config GENERIC_FIND_NEXT_BIT
43 config GENERIC_HWEIGHT
47 config GENERIC_HARDIRQS
51 config GENERIC_IRQ_PROBE
59 config FORCE_MAX_ZONEORDER
63 config GENERIC_CALIBRATE_DELAY
69 source "kernel/Kconfig.preempt"
71 source "kernel/Kconfig.freezer"
73 menu "Blackfin Processor Options"
75 comment "Processor and Board Settings"
84 BF512 Processor Support.
89 BF514 Processor Support.
94 BF516 Processor Support.
99 BF518 Processor Support.
104 BF522 Processor Support.
109 BF523 Processor Support.
114 BF524 Processor Support.
119 BF525 Processor Support.
124 BF526 Processor Support.
129 BF527 Processor Support.
134 BF531 Processor Support.
139 BF532 Processor Support.
144 BF533 Processor Support.
149 BF534 Processor Support.
154 BF536 Processor Support.
159 BF537 Processor Support.
164 BF538 Processor Support.
169 BF539 Processor Support.
174 BF542 Processor Support.
179 BF542 Processor Support.
184 BF544 Processor Support.
189 BF544 Processor Support.
194 BF547 Processor Support.
199 BF547 Processor Support.
204 BF548 Processor Support.
209 BF548 Processor Support.
214 BF549 Processor Support.
219 BF549 Processor Support.
224 BF561 Processor Support.
231 bool "Symmetric multi-processing support"
233 This enables support for systems with more than one CPU,
234 like the dual core BF561. If you have a system with only one
235 CPU, say N. If you have a system with more than one CPU, say Y.
237 If you don't know what to do here, say N.
251 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
252 default 2 if (BF537 || BF536 || BF534)
253 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
254 default 4 if (BF538 || BF539)
258 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
259 default 3 if (BF537 || BF536 || BF534 || BF54xM)
260 default 5 if (BF561 || BF538 || BF539)
261 default 6 if (BF533 || BF532 || BF531)
265 default BF_REV_0_0 if (BF51x || BF52x)
266 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
267 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
271 depends on (BF51x || BF52x || (BF54x && !BF54xM))
275 depends on (BF52x || (BF54x && !BF54xM))
279 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
283 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
287 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
291 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
295 depends on (BF533 || BF532 || BF531)
307 depends on (BF512 || BF514 || BF516 || BF518)
312 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
317 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
322 depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
327 depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
330 config MEM_GENERIC_BOARD
332 depends on GENERIC_BOARD
335 config MEM_MT48LC64M4A2FB_7E
337 depends on (BFIN533_STAMP)
340 config MEM_MT48LC16M16A2TG_75
342 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
343 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
344 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
347 config MEM_MT48LC32M8A2_75
349 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
352 config MEM_MT48LC8M32B2B5_7
354 depends on (BFIN561_BLUETECHNIX_CM)
357 config MEM_MT48LC32M16A2TG_75
359 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
362 config MEM_MT48LC32M8A2_75
364 depends on (BFIN518F_EZBRD)
367 source "arch/blackfin/mach-bf518/Kconfig"
368 source "arch/blackfin/mach-bf527/Kconfig"
369 source "arch/blackfin/mach-bf533/Kconfig"
370 source "arch/blackfin/mach-bf561/Kconfig"
371 source "arch/blackfin/mach-bf537/Kconfig"
372 source "arch/blackfin/mach-bf538/Kconfig"
373 source "arch/blackfin/mach-bf548/Kconfig"
375 menu "Board customizations"
378 bool "Default bootloader kernel arguments"
381 string "Initial kernel command string"
382 depends on CMDLINE_BOOL
383 default "console=ttyBF0,57600"
385 If you don't have a boot loader capable of passing a command line string
386 to the kernel, you may specify one here. As a minimum, you should specify
387 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
390 hex "Kernel load address for booting"
392 range 0x1000 0x20000000
394 This option allows you to set the load address of the kernel.
395 This can be useful if you are on a board which has a small amount
396 of memory or you wish to reserve some memory at the beginning of
399 Note that you need to keep this value above 4k (0x1000) as this
400 memory region is used to capture NULL pointer references as well
401 as some core kernel functions.
404 hex "Kernel ROM Base"
407 range 0x20000000 0x20400000 if !(BF54x || BF561)
408 range 0x20000000 0x30000000 if (BF54x || BF561)
411 comment "Clock/PLL Setup"
414 int "Frequency of the crystal on the board in Hz"
415 default "11059200" if BFIN533_STAMP
416 default "27000000" if BFIN533_EZKIT
417 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
418 default "30000000" if BFIN561_EZKIT
419 default "24576000" if PNAV10
420 default "10000000" if BFIN532_IP0X
422 The frequency of CLKIN crystal oscillator on the board in Hz.
423 Warning: This value should match the crystal on the board. Otherwise,
424 peripherals won't work properly.
426 config BFIN_KERNEL_CLOCK
427 bool "Re-program Clocks while Kernel boots?"
430 This option decides if kernel clocks are re-programed from the
431 bootloader settings. If the clocks are not set, the SDRAM settings
432 are also not changed, and the Bootloader does 100% of the hardware
437 depends on BFIN_KERNEL_CLOCK
442 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
445 If this is set the clock will be divided by 2, before it goes to the PLL.
449 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
451 default "22" if BFIN533_EZKIT
452 default "45" if BFIN533_STAMP
453 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
454 default "22" if BFIN533_BLUETECHNIX_CM
455 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
456 default "20" if BFIN561_EZKIT
457 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
459 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
460 PLL Frequency = (Crystal Frequency) * (this setting)
463 prompt "Core Clock Divider"
464 depends on BFIN_KERNEL_CLOCK
467 This sets the frequency of the core. It can be 1, 2, 4 or 8
468 Core Frequency = (PLL frequency) / (this setting)
484 int "System Clock Divider"
485 depends on BFIN_KERNEL_CLOCK
489 This sets the frequency of the system clock (including SDRAM or DDR).
490 This can be between 1 and 15
491 System Clock = (PLL frequency) / (this setting)
494 prompt "DDR SDRAM Chip Type"
495 depends on BFIN_KERNEL_CLOCK
497 default MEM_MT46V32M16_5B
499 config MEM_MT46V32M16_6T
502 config MEM_MT46V32M16_5B
507 prompt "DDR/SDRAM Timing"
508 depends on BFIN_KERNEL_CLOCK
509 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
511 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
512 The calculated SDRAM timing parameters may not be 100%
513 accurate - This option is therefore marked experimental.
515 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
516 bool "Calculate Timings (EXPERIMENTAL)"
517 depends on EXPERIMENTAL
519 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
520 bool "Provide accurate Timings based on target SCLK"
522 Please consult the Blackfin Hardware Reference Manuals as well
523 as the memory device datasheet.
524 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
527 menu "Memory Init Control"
528 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
545 config MEM_EBIU_DDRQUE
562 # Max & Min Speeds for various Chips
566 default 400000000 if BF512
567 default 400000000 if BF514
568 default 400000000 if BF516
569 default 400000000 if BF518
570 default 600000000 if BF522
571 default 400000000 if BF523
572 default 400000000 if BF524
573 default 600000000 if BF525
574 default 400000000 if BF526
575 default 600000000 if BF527
576 default 400000000 if BF531
577 default 400000000 if BF532
578 default 750000000 if BF533
579 default 500000000 if BF534
580 default 400000000 if BF536
581 default 600000000 if BF537
582 default 533333333 if BF538
583 default 533333333 if BF539
584 default 600000000 if BF542
585 default 533333333 if BF544
586 default 600000000 if BF547
587 default 600000000 if BF548
588 default 533333333 if BF549
589 default 600000000 if BF561
603 comment "Kernel Timer/Scheduler"
605 source kernel/Kconfig.hz
611 config GENERIC_CLOCKEVENTS
612 bool "Generic clock events"
613 depends on GENERIC_TIME
617 prompt "Kernel Tick Source"
618 depends on GENERIC_CLOCKEVENTS
619 default TICKSOURCE_CORETMR
621 config TICKSOURCE_GPTMR0
622 bool "Gptimer0 (SCLK domain)"
626 config TICKSOURCE_CORETMR
627 bool "Core timer (CCLK domain)"
631 config CYCLES_CLOCKSOURCE
632 bool "Use 'CYCLES' as a clocksource"
633 depends on GENERIC_CLOCKEVENTS
634 depends on !BFIN_SCRATCH_REG_CYCLES
637 If you say Y here, you will enable support for using the 'cycles'
638 registers as a clock source. Doing so means you will be unable to
639 safely write to the 'cycles' register during runtime. You will
640 still be able to read it (such as for performance monitoring), but
641 writing the registers will most likely crash the kernel.
643 config GPTMR0_CLOCKSOURCE
644 bool "Use GPTimer0 as a clocksource (higher rating)"
645 depends on GENERIC_CLOCKEVENTS
646 depends on !TICKSOURCE_GPTMR0
648 source kernel/time/Kconfig
653 prompt "Blackfin Exception Scratch Register"
654 default BFIN_SCRATCH_REG_RETN
656 Select the resource to reserve for the Exception handler:
657 - RETN: Non-Maskable Interrupt (NMI)
658 - RETE: Exception Return (JTAG/ICE)
659 - CYCLES: Performance counter
661 If you are unsure, please select "RETN".
663 config BFIN_SCRATCH_REG_RETN
666 Use the RETN register in the Blackfin exception handler
667 as a stack scratch register. This means you cannot
668 safely use NMI on the Blackfin while running Linux, but
669 you can debug the system with a JTAG ICE and use the
670 CYCLES performance registers.
672 If you are unsure, please select "RETN".
674 config BFIN_SCRATCH_REG_RETE
677 Use the RETE register in the Blackfin exception handler
678 as a stack scratch register. This means you cannot
679 safely use a JTAG ICE while debugging a Blackfin board,
680 but you can safely use the CYCLES performance registers
683 If you are unsure, please select "RETN".
685 config BFIN_SCRATCH_REG_CYCLES
688 Use the CYCLES register in the Blackfin exception handler
689 as a stack scratch register. This means you cannot
690 safely use the CYCLES performance registers on a Blackfin
691 board at anytime, but you can debug the system with a JTAG
694 If you are unsure, please select "RETN".
701 menu "Blackfin Kernel Optimizations"
704 comment "Memory Optimizations"
707 bool "Locate interrupt entry code in L1 Memory"
710 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
711 into L1 instruction memory. (less latency)
713 config EXCPT_IRQ_SYSC_L1
714 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
717 If enabled, the entire ASM lowlevel exception and interrupt entry code
718 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
722 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
725 If enabled, the frequently called do_irq dispatcher function is linked
726 into L1 instruction memory. (less latency)
728 config CORE_TIMER_IRQ_L1
729 bool "Locate frequently called timer_interrupt() function in L1 Memory"
732 If enabled, the frequently called timer_interrupt() function is linked
733 into L1 instruction memory. (less latency)
736 bool "Locate frequently idle function in L1 Memory"
739 If enabled, the frequently called idle function is linked
740 into L1 instruction memory. (less latency)
743 bool "Locate kernel schedule function in L1 Memory"
746 If enabled, the frequently called kernel schedule is linked
747 into L1 instruction memory. (less latency)
749 config ARITHMETIC_OPS_L1
750 bool "Locate kernel owned arithmetic functions in L1 Memory"
753 If enabled, arithmetic functions are linked
754 into L1 instruction memory. (less latency)
757 bool "Locate access_ok function in L1 Memory"
760 If enabled, the access_ok function is linked
761 into L1 instruction memory. (less latency)
764 bool "Locate memset function in L1 Memory"
767 If enabled, the memset function is linked
768 into L1 instruction memory. (less latency)
771 bool "Locate memcpy function in L1 Memory"
774 If enabled, the memcpy function is linked
775 into L1 instruction memory. (less latency)
777 config SYS_BFIN_SPINLOCK_L1
778 bool "Locate sys_bfin_spinlock function in L1 Memory"
781 If enabled, sys_bfin_spinlock function is linked
782 into L1 instruction memory. (less latency)
784 config IP_CHECKSUM_L1
785 bool "Locate IP Checksum function in L1 Memory"
788 If enabled, the IP Checksum function is linked
789 into L1 instruction memory. (less latency)
791 config CACHELINE_ALIGNED_L1
792 bool "Locate cacheline_aligned data to L1 Data Memory"
797 If enabled, cacheline_aligned data is linked
798 into L1 data memory. (less latency)
800 config SYSCALL_TAB_L1
801 bool "Locate Syscall Table L1 Data Memory"
805 If enabled, the Syscall LUT is linked
806 into L1 data memory. (less latency)
808 config CPLB_SWITCH_TAB_L1
809 bool "Locate CPLB Switch Tables L1 Data Memory"
813 If enabled, the CPLB Switch Tables are linked
814 into L1 data memory. (less latency)
817 bool "Support locating application stack in L1 Scratch Memory"
820 If enabled the application stack can be located in L1
821 scratch memory (less latency).
823 Currently only works with FLAT binaries.
825 config EXCEPTION_L1_SCRATCH
826 bool "Locate exception stack in L1 Scratch Memory"
828 depends on !APP_STACK_L1
830 Whenever an exception occurs, use the L1 Scratch memory for
831 stack storage. You cannot place the stacks of FLAT binaries
832 in L1 when using this option.
834 If you don't use L1 Scratch, then you should say Y here.
836 comment "Speed Optimizations"
837 config BFIN_INS_LOWOVERHEAD
838 bool "ins[bwl] low overhead, higher interrupt latency"
841 Reads on the Blackfin are speculative. In Blackfin terms, this means
842 they can be interrupted at any time (even after they have been issued
843 on to the external bus), and re-issued after the interrupt occurs.
844 For memory - this is not a big deal, since memory does not change if
847 If a FIFO is sitting on the end of the read, it will see two reads,
848 when the core only sees one since the FIFO receives both the read
849 which is cancelled (and not delivered to the core) and the one which
850 is re-issued (which is delivered to the core).
852 To solve this, interrupts are turned off before reads occur to
853 I/O space. This option controls which the overhead/latency of
854 controlling interrupts during this time
855 "n" turns interrupts off every read
856 (higher overhead, but lower interrupt latency)
857 "y" turns interrupts off every loop
858 (low overhead, but longer interrupt latency)
860 default behavior is to leave this set to on (type "Y"). If you are experiencing
861 interrupt latency issues, it is safe and OK to turn this off.
866 prompt "Kernel executes from"
868 Choose the memory type that the kernel will be running in.
873 The kernel will be resident in RAM when running.
878 The kernel will be resident in FLASH/ROM when running.
885 tristate "Enable Blackfin General Purpose Timers API"
888 Enable support for the General Purpose Timers API. If you
891 To compile this driver as a module, choose M here: the module
892 will be called gptimers.ko.
895 prompt "Uncached DMA region"
896 default DMA_UNCACHED_1M
897 config DMA_UNCACHED_4M
898 bool "Enable 4M DMA region"
899 config DMA_UNCACHED_2M
900 bool "Enable 2M DMA region"
901 config DMA_UNCACHED_1M
902 bool "Enable 1M DMA region"
903 config DMA_UNCACHED_NONE
904 bool "Disable DMA region"
908 comment "Cache Support"
913 config BFIN_DCACHE_BANKA
914 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
915 depends on BFIN_DCACHE && !BF531
917 config BFIN_ICACHE_LOCK
918 bool "Enable Instruction Cache Locking"
921 prompt "External memory cache policy"
922 depends on BFIN_DCACHE
923 default BFIN_WB if !SMP
924 default BFIN_WT if SMP
930 Cached data will be written back to SDRAM only when needed.
931 This can give a nice increase in performance, but beware of
932 broken drivers that do not properly invalidate/flush their
935 Write Through Policy:
936 Cached data will always be written back to SDRAM when the
937 cache is updated. This is a completely safe setting, but
938 performance is worse than Write Back.
940 If you are unsure of the options and you want to be safe,
941 then go with Write Through.
947 Cached data will be written back to SDRAM only when needed.
948 This can give a nice increase in performance, but beware of
949 broken drivers that do not properly invalidate/flush their
952 Write Through Policy:
953 Cached data will always be written back to SDRAM when the
954 cache is updated. This is a completely safe setting, but
955 performance is worse than Write Back.
957 If you are unsure of the options and you want to be safe,
958 then go with Write Through.
963 prompt "L2 SRAM cache policy"
964 depends on (BF54x || BF561)
974 config BFIN_L2_NOT_CACHED
980 bool "Enable the memory protection unit (EXPERIMENTAL)"
983 Use the processor's MPU to protect applications from accessing
984 memory they do not own. This comes at a performance penalty
985 and is recommended only for debugging.
987 comment "Asynchronous Memory Configuration"
989 menu "EBIU_AMGCTL Global Control"
995 bool "DMA has priority over core for ext. accesses"
1000 bool "Bank 0 16 bit packing enable"
1005 bool "Bank 1 16 bit packing enable"
1010 bool "Bank 2 16 bit packing enable"
1015 bool "Bank 3 16 bit packing enable"
1019 prompt "Enable Asynchronous Memory Banks"
1023 bool "Disable All Banks"
1026 bool "Enable Bank 0"
1028 config C_AMBEN_B0_B1
1029 bool "Enable Bank 0 & 1"
1031 config C_AMBEN_B0_B1_B2
1032 bool "Enable Bank 0 & 1 & 2"
1035 bool "Enable All Banks"
1039 menu "EBIU_AMBCTL Control"
1041 hex "Bank 0 (AMBCTL0.L)"
1044 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1045 used to control the Asynchronous Memory Bank 0 settings.
1048 hex "Bank 1 (AMBCTL0.H)"
1050 default 0x5558 if BF54x
1052 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1053 used to control the Asynchronous Memory Bank 1 settings.
1056 hex "Bank 2 (AMBCTL1.L)"
1059 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1060 used to control the Asynchronous Memory Bank 2 settings.
1063 hex "Bank 3 (AMBCTL1.H)"
1066 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1067 used to control the Asynchronous Memory Bank 3 settings.
1071 config EBIU_MBSCTLVAL
1072 hex "EBIU Bank Select Control Register"
1077 hex "Flash Memory Mode Control Register"
1082 hex "Flash Memory Bank Control Register"
1087 #############################################################################
1088 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1094 Support for PCI bus.
1096 source "drivers/pci/Kconfig"
1099 bool "Support for hot-pluggable device"
1101 Say Y here if you want to plug devices into your computer while
1102 the system is running, and be able to use them quickly. In many
1103 cases, the devices can likewise be unplugged at any time too.
1105 One well known example of this is PCMCIA- or PC-cards, credit-card
1106 size devices such as network cards, modems or hard drives which are
1107 plugged into slots found on all modern laptop computers. Another
1108 example, used on modern desktops as well as laptops, is USB.
1110 Enable HOTPLUG and build a modular kernel. Get agent software
1111 (from <http://linux-hotplug.sourceforge.net/>) and install it.
1112 Then your kernel will automatically call out to a user mode "policy
1113 agent" (/sbin/hotplug) to load modules and set up software needed
1114 to use devices as you hotplug them.
1116 source "drivers/pcmcia/Kconfig"
1118 source "drivers/pci/hotplug/Kconfig"
1122 menu "Executable file formats"
1124 source "fs/Kconfig.binfmt"
1128 menu "Power management options"
1129 source "kernel/power/Kconfig"
1131 config ARCH_SUSPEND_POSSIBLE
1136 prompt "Standby Power Saving Mode"
1138 default PM_BFIN_SLEEP_DEEPER
1139 config PM_BFIN_SLEEP_DEEPER
1142 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1143 power dissipation by disabling the clock to the processor core (CCLK).
1144 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1145 to 0.85 V to provide the greatest power savings, while preserving the
1147 The PLL and system clock (SCLK) continue to operate at a very low
1148 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1149 the SDRAM is put into Self Refresh Mode. Typically an external event
1150 such as GPIO interrupt or RTC activity wakes up the processor.
1151 Various Peripherals such as UART, SPORT, PPI may not function as
1152 normal during Sleep Deeper, due to the reduced SCLK frequency.
1153 When in the sleep mode, system DMA access to L1 memory is not supported.
1155 If unsure, select "Sleep Deeper".
1157 config PM_BFIN_SLEEP
1160 Sleep Mode (High Power Savings) - The sleep mode reduces power
1161 dissipation by disabling the clock to the processor core (CCLK).
1162 The PLL and system clock (SCLK), however, continue to operate in
1163 this mode. Typically an external event or RTC activity will wake
1164 up the processor. When in the sleep mode, system DMA access to L1
1165 memory is not supported.
1167 If unsure, select "Sleep Deeper".
1170 config PM_WAKEUP_BY_GPIO
1171 bool "Allow Wakeup from Standby by GPIO"
1172 depends on PM && !BF54x
1174 config PM_WAKEUP_GPIO_NUMBER
1177 depends on PM_WAKEUP_BY_GPIO
1181 prompt "GPIO Polarity"
1182 depends on PM_WAKEUP_BY_GPIO
1183 default PM_WAKEUP_GPIO_POLAR_H
1184 config PM_WAKEUP_GPIO_POLAR_H
1186 config PM_WAKEUP_GPIO_POLAR_L
1188 config PM_WAKEUP_GPIO_POLAR_EDGE_F
1190 config PM_WAKEUP_GPIO_POLAR_EDGE_R
1192 config PM_WAKEUP_GPIO_POLAR_EDGE_B
1196 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1199 config PM_BFIN_WAKE_PH6
1200 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1201 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1204 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1206 config PM_BFIN_WAKE_GP
1207 bool "Allow Wake-Up from GPIOs"
1208 depends on PM && BF54x
1211 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1212 (all processors, except ADSP-BF549). This option sets
1213 the general-purpose wake-up enable (GPWE) control bit to enable
1214 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1215 On ADSP-BF549 this option enables the the same functionality on the
1216 /MRXON pin also PH7.
1220 menu "CPU Frequency scaling"
1222 source "drivers/cpufreq/Kconfig"
1224 config BFIN_CPU_FREQ
1227 select CPU_FREQ_TABLE
1231 bool "CPU Voltage scaling"
1232 depends on EXPERIMENTAL
1236 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1237 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1238 manuals. There is a theoretical risk that during VDDINT transitions
1243 source "net/Kconfig"
1245 source "drivers/Kconfig"
1249 source "arch/blackfin/Kconfig.debug"
1251 source "security/Kconfig"
1253 source "crypto/Kconfig"
1255 source "lib/Kconfig"