2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
14 config RWSEM_GENERIC_SPINLOCK
17 config RWSEM_XCHGADD_ALGORITHM
23 select HAVE_KERNEL_GZIP
24 select HAVE_KERNEL_BZIP2
25 select HAVE_KERNEL_LZMA
27 select ARCH_WANT_OPTIONAL_GPIOLIB
36 config GENERIC_FIND_NEXT_BIT
39 config GENERIC_HWEIGHT
42 config GENERIC_HARDIRQS
45 config GENERIC_IRQ_PROBE
51 config FORCE_MAX_ZONEORDER
55 config GENERIC_CALIBRATE_DELAY
60 source "kernel/Kconfig.preempt"
62 source "kernel/Kconfig.freezer"
64 menu "Blackfin Processor Options"
66 comment "Processor and Board Settings"
75 BF512 Processor Support.
80 BF514 Processor Support.
85 BF516 Processor Support.
90 BF518 Processor Support.
95 BF522 Processor Support.
100 BF523 Processor Support.
105 BF524 Processor Support.
110 BF525 Processor Support.
115 BF526 Processor Support.
120 BF527 Processor Support.
125 BF531 Processor Support.
130 BF532 Processor Support.
135 BF533 Processor Support.
140 BF534 Processor Support.
145 BF536 Processor Support.
150 BF537 Processor Support.
155 BF538 Processor Support.
160 BF539 Processor Support.
165 BF542 Processor Support.
170 BF542 Processor Support.
175 BF544 Processor Support.
180 BF544 Processor Support.
185 BF547 Processor Support.
190 BF547 Processor Support.
195 BF548 Processor Support.
200 BF548 Processor Support.
205 BF549 Processor Support.
210 BF549 Processor Support.
215 BF561 Processor Support.
222 bool "Symmetric multi-processing support"
224 This enables support for systems with more than one CPU,
225 like the dual core BF561. If you have a system with only one
226 CPU, say N. If you have a system with more than one CPU, say Y.
228 If you don't know what to do here, say N.
242 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
243 default 2 if (BF537 || BF536 || BF534)
244 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
245 default 4 if (BF538 || BF539)
249 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
250 default 3 if (BF537 || BF536 || BF534 || BF54xM)
251 default 5 if (BF561 || BF538 || BF539)
252 default 6 if (BF533 || BF532 || BF531)
256 default BF_REV_0_0 if (BF51x || BF52x)
257 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
258 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
262 depends on (BF51x || BF52x || (BF54x && !BF54xM))
266 depends on (BF52x || (BF54x && !BF54xM))
270 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
274 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
278 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
282 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
286 depends on (BF533 || BF532 || BF531)
298 depends on (BF512 || BF514 || BF516 || BF518)
303 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
308 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
313 depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
318 depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
321 config MEM_GENERIC_BOARD
323 depends on GENERIC_BOARD
326 config MEM_MT48LC64M4A2FB_7E
328 depends on (BFIN533_STAMP)
331 config MEM_MT48LC16M16A2TG_75
333 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
334 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
335 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
338 config MEM_MT48LC32M8A2_75
340 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
343 config MEM_MT48LC8M32B2B5_7
345 depends on (BFIN561_BLUETECHNIX_CM)
348 config MEM_MT48LC32M16A2TG_75
350 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
353 config MEM_MT48LC32M8A2_75
355 depends on (BFIN518F_EZBRD)
358 source "arch/blackfin/mach-bf518/Kconfig"
359 source "arch/blackfin/mach-bf527/Kconfig"
360 source "arch/blackfin/mach-bf533/Kconfig"
361 source "arch/blackfin/mach-bf561/Kconfig"
362 source "arch/blackfin/mach-bf537/Kconfig"
363 source "arch/blackfin/mach-bf538/Kconfig"
364 source "arch/blackfin/mach-bf548/Kconfig"
366 menu "Board customizations"
369 bool "Default bootloader kernel arguments"
372 string "Initial kernel command string"
373 depends on CMDLINE_BOOL
374 default "console=ttyBF0,57600"
376 If you don't have a boot loader capable of passing a command line string
377 to the kernel, you may specify one here. As a minimum, you should specify
378 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
381 hex "Kernel load address for booting"
383 range 0x1000 0x20000000
385 This option allows you to set the load address of the kernel.
386 This can be useful if you are on a board which has a small amount
387 of memory or you wish to reserve some memory at the beginning of
390 Note that you need to keep this value above 4k (0x1000) as this
391 memory region is used to capture NULL pointer references as well
392 as some core kernel functions.
395 hex "Kernel ROM Base"
398 range 0x20000000 0x20400000 if !(BF54x || BF561)
399 range 0x20000000 0x30000000 if (BF54x || BF561)
402 comment "Clock/PLL Setup"
405 int "Frequency of the crystal on the board in Hz"
406 default "11059200" if BFIN533_STAMP
407 default "27000000" if BFIN533_EZKIT
408 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
409 default "30000000" if BFIN561_EZKIT
410 default "24576000" if PNAV10
411 default "10000000" if BFIN532_IP0X
413 The frequency of CLKIN crystal oscillator on the board in Hz.
414 Warning: This value should match the crystal on the board. Otherwise,
415 peripherals won't work properly.
417 config BFIN_KERNEL_CLOCK
418 bool "Re-program Clocks while Kernel boots?"
421 This option decides if kernel clocks are re-programed from the
422 bootloader settings. If the clocks are not set, the SDRAM settings
423 are also not changed, and the Bootloader does 100% of the hardware
428 depends on BFIN_KERNEL_CLOCK
433 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
436 If this is set the clock will be divided by 2, before it goes to the PLL.
440 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
442 default "22" if BFIN533_EZKIT
443 default "45" if BFIN533_STAMP
444 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
445 default "22" if BFIN533_BLUETECHNIX_CM
446 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
447 default "20" if BFIN561_EZKIT
448 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
450 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
451 PLL Frequency = (Crystal Frequency) * (this setting)
454 prompt "Core Clock Divider"
455 depends on BFIN_KERNEL_CLOCK
458 This sets the frequency of the core. It can be 1, 2, 4 or 8
459 Core Frequency = (PLL frequency) / (this setting)
475 int "System Clock Divider"
476 depends on BFIN_KERNEL_CLOCK
480 This sets the frequency of the system clock (including SDRAM or DDR).
481 This can be between 1 and 15
482 System Clock = (PLL frequency) / (this setting)
485 prompt "DDR SDRAM Chip Type"
486 depends on BFIN_KERNEL_CLOCK
488 default MEM_MT46V32M16_5B
490 config MEM_MT46V32M16_6T
493 config MEM_MT46V32M16_5B
498 prompt "DDR/SDRAM Timing"
499 depends on BFIN_KERNEL_CLOCK
500 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
502 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
503 The calculated SDRAM timing parameters may not be 100%
504 accurate - This option is therefore marked experimental.
506 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
507 bool "Calculate Timings (EXPERIMENTAL)"
508 depends on EXPERIMENTAL
510 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
511 bool "Provide accurate Timings based on target SCLK"
513 Please consult the Blackfin Hardware Reference Manuals as well
514 as the memory device datasheet.
515 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
518 menu "Memory Init Control"
519 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
536 config MEM_EBIU_DDRQUE
553 # Max & Min Speeds for various Chips
557 default 400000000 if BF512
558 default 400000000 if BF514
559 default 400000000 if BF516
560 default 400000000 if BF518
561 default 600000000 if BF522
562 default 400000000 if BF523
563 default 400000000 if BF524
564 default 600000000 if BF525
565 default 400000000 if BF526
566 default 600000000 if BF527
567 default 400000000 if BF531
568 default 400000000 if BF532
569 default 750000000 if BF533
570 default 500000000 if BF534
571 default 400000000 if BF536
572 default 600000000 if BF537
573 default 533333333 if BF538
574 default 533333333 if BF539
575 default 600000000 if BF542
576 default 533333333 if BF544
577 default 600000000 if BF547
578 default 600000000 if BF548
579 default 533333333 if BF549
580 default 600000000 if BF561
594 comment "Kernel Timer/Scheduler"
596 source kernel/Kconfig.hz
602 config GENERIC_CLOCKEVENTS
603 bool "Generic clock events"
604 depends on GENERIC_TIME
608 prompt "Kernel Tick Source"
609 depends on GENERIC_CLOCKEVENTS
610 default TICKSOURCE_CORETMR
612 config TICKSOURCE_GPTMR0
613 bool "Gptimer0 (SCLK domain)"
617 config TICKSOURCE_CORETMR
618 bool "Core timer (CCLK domain)"
622 config CYCLES_CLOCKSOURCE
623 bool "Use 'CYCLES' as a clocksource"
624 depends on GENERIC_CLOCKEVENTS
625 depends on !BFIN_SCRATCH_REG_CYCLES
628 If you say Y here, you will enable support for using the 'cycles'
629 registers as a clock source. Doing so means you will be unable to
630 safely write to the 'cycles' register during runtime. You will
631 still be able to read it (such as for performance monitoring), but
632 writing the registers will most likely crash the kernel.
634 config GPTMR0_CLOCKSOURCE
635 bool "Use GPTimer0 as a clocksource (higher rating)"
636 depends on GENERIC_CLOCKEVENTS
637 depends on !TICKSOURCE_GPTMR0
639 source kernel/time/Kconfig
644 prompt "Blackfin Exception Scratch Register"
645 default BFIN_SCRATCH_REG_RETN
647 Select the resource to reserve for the Exception handler:
648 - RETN: Non-Maskable Interrupt (NMI)
649 - RETE: Exception Return (JTAG/ICE)
650 - CYCLES: Performance counter
652 If you are unsure, please select "RETN".
654 config BFIN_SCRATCH_REG_RETN
657 Use the RETN register in the Blackfin exception handler
658 as a stack scratch register. This means you cannot
659 safely use NMI on the Blackfin while running Linux, but
660 you can debug the system with a JTAG ICE and use the
661 CYCLES performance registers.
663 If you are unsure, please select "RETN".
665 config BFIN_SCRATCH_REG_RETE
668 Use the RETE register in the Blackfin exception handler
669 as a stack scratch register. This means you cannot
670 safely use a JTAG ICE while debugging a Blackfin board,
671 but you can safely use the CYCLES performance registers
674 If you are unsure, please select "RETN".
676 config BFIN_SCRATCH_REG_CYCLES
679 Use the CYCLES register in the Blackfin exception handler
680 as a stack scratch register. This means you cannot
681 safely use the CYCLES performance registers on a Blackfin
682 board at anytime, but you can debug the system with a JTAG
685 If you are unsure, please select "RETN".
692 menu "Blackfin Kernel Optimizations"
695 comment "Memory Optimizations"
698 bool "Locate interrupt entry code in L1 Memory"
701 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
702 into L1 instruction memory. (less latency)
704 config EXCPT_IRQ_SYSC_L1
705 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
708 If enabled, the entire ASM lowlevel exception and interrupt entry code
709 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
713 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
716 If enabled, the frequently called do_irq dispatcher function is linked
717 into L1 instruction memory. (less latency)
719 config CORE_TIMER_IRQ_L1
720 bool "Locate frequently called timer_interrupt() function in L1 Memory"
723 If enabled, the frequently called timer_interrupt() function is linked
724 into L1 instruction memory. (less latency)
727 bool "Locate frequently idle function in L1 Memory"
730 If enabled, the frequently called idle function is linked
731 into L1 instruction memory. (less latency)
734 bool "Locate kernel schedule function in L1 Memory"
737 If enabled, the frequently called kernel schedule is linked
738 into L1 instruction memory. (less latency)
740 config ARITHMETIC_OPS_L1
741 bool "Locate kernel owned arithmetic functions in L1 Memory"
744 If enabled, arithmetic functions are linked
745 into L1 instruction memory. (less latency)
748 bool "Locate access_ok function in L1 Memory"
751 If enabled, the access_ok function is linked
752 into L1 instruction memory. (less latency)
755 bool "Locate memset function in L1 Memory"
758 If enabled, the memset function is linked
759 into L1 instruction memory. (less latency)
762 bool "Locate memcpy function in L1 Memory"
765 If enabled, the memcpy function is linked
766 into L1 instruction memory. (less latency)
768 config SYS_BFIN_SPINLOCK_L1
769 bool "Locate sys_bfin_spinlock function in L1 Memory"
772 If enabled, sys_bfin_spinlock function is linked
773 into L1 instruction memory. (less latency)
775 config IP_CHECKSUM_L1
776 bool "Locate IP Checksum function in L1 Memory"
779 If enabled, the IP Checksum function is linked
780 into L1 instruction memory. (less latency)
782 config CACHELINE_ALIGNED_L1
783 bool "Locate cacheline_aligned data to L1 Data Memory"
788 If enabled, cacheline_aligned data is linked
789 into L1 data memory. (less latency)
791 config SYSCALL_TAB_L1
792 bool "Locate Syscall Table L1 Data Memory"
796 If enabled, the Syscall LUT is linked
797 into L1 data memory. (less latency)
799 config CPLB_SWITCH_TAB_L1
800 bool "Locate CPLB Switch Tables L1 Data Memory"
804 If enabled, the CPLB Switch Tables are linked
805 into L1 data memory. (less latency)
808 bool "Support locating application stack in L1 Scratch Memory"
811 If enabled the application stack can be located in L1
812 scratch memory (less latency).
814 Currently only works with FLAT binaries.
816 config EXCEPTION_L1_SCRATCH
817 bool "Locate exception stack in L1 Scratch Memory"
819 depends on !APP_STACK_L1
821 Whenever an exception occurs, use the L1 Scratch memory for
822 stack storage. You cannot place the stacks of FLAT binaries
823 in L1 when using this option.
825 If you don't use L1 Scratch, then you should say Y here.
827 comment "Speed Optimizations"
828 config BFIN_INS_LOWOVERHEAD
829 bool "ins[bwl] low overhead, higher interrupt latency"
832 Reads on the Blackfin are speculative. In Blackfin terms, this means
833 they can be interrupted at any time (even after they have been issued
834 on to the external bus), and re-issued after the interrupt occurs.
835 For memory - this is not a big deal, since memory does not change if
838 If a FIFO is sitting on the end of the read, it will see two reads,
839 when the core only sees one since the FIFO receives both the read
840 which is cancelled (and not delivered to the core) and the one which
841 is re-issued (which is delivered to the core).
843 To solve this, interrupts are turned off before reads occur to
844 I/O space. This option controls which the overhead/latency of
845 controlling interrupts during this time
846 "n" turns interrupts off every read
847 (higher overhead, but lower interrupt latency)
848 "y" turns interrupts off every loop
849 (low overhead, but longer interrupt latency)
851 default behavior is to leave this set to on (type "Y"). If you are experiencing
852 interrupt latency issues, it is safe and OK to turn this off.
857 prompt "Kernel executes from"
859 Choose the memory type that the kernel will be running in.
864 The kernel will be resident in RAM when running.
869 The kernel will be resident in FLASH/ROM when running.
876 tristate "Enable Blackfin General Purpose Timers API"
879 Enable support for the General Purpose Timers API. If you
882 To compile this driver as a module, choose M here: the module
883 will be called gptimers.ko.
886 prompt "Uncached DMA region"
887 default DMA_UNCACHED_1M
888 config DMA_UNCACHED_4M
889 bool "Enable 4M DMA region"
890 config DMA_UNCACHED_2M
891 bool "Enable 2M DMA region"
892 config DMA_UNCACHED_1M
893 bool "Enable 1M DMA region"
894 config DMA_UNCACHED_NONE
895 bool "Disable DMA region"
899 comment "Cache Support"
904 config BFIN_DCACHE_BANKA
905 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
906 depends on BFIN_DCACHE && !BF531
908 config BFIN_ICACHE_LOCK
909 bool "Enable Instruction Cache Locking"
912 prompt "External memory cache policy"
913 depends on BFIN_DCACHE
914 default BFIN_WB if !SMP
915 default BFIN_WT if SMP
921 Cached data will be written back to SDRAM only when needed.
922 This can give a nice increase in performance, but beware of
923 broken drivers that do not properly invalidate/flush their
926 Write Through Policy:
927 Cached data will always be written back to SDRAM when the
928 cache is updated. This is a completely safe setting, but
929 performance is worse than Write Back.
931 If you are unsure of the options and you want to be safe,
932 then go with Write Through.
938 Cached data will be written back to SDRAM only when needed.
939 This can give a nice increase in performance, but beware of
940 broken drivers that do not properly invalidate/flush their
943 Write Through Policy:
944 Cached data will always be written back to SDRAM when the
945 cache is updated. This is a completely safe setting, but
946 performance is worse than Write Back.
948 If you are unsure of the options and you want to be safe,
949 then go with Write Through.
954 prompt "L2 SRAM cache policy"
955 depends on (BF54x || BF561)
965 config BFIN_L2_NOT_CACHED
971 bool "Enable the memory protection unit (EXPERIMENTAL)"
974 Use the processor's MPU to protect applications from accessing
975 memory they do not own. This comes at a performance penalty
976 and is recommended only for debugging.
978 comment "Asynchronous Memory Configuration"
980 menu "EBIU_AMGCTL Global Control"
986 bool "DMA has priority over core for ext. accesses"
991 bool "Bank 0 16 bit packing enable"
996 bool "Bank 1 16 bit packing enable"
1001 bool "Bank 2 16 bit packing enable"
1006 bool "Bank 3 16 bit packing enable"
1010 prompt "Enable Asynchronous Memory Banks"
1014 bool "Disable All Banks"
1017 bool "Enable Bank 0"
1019 config C_AMBEN_B0_B1
1020 bool "Enable Bank 0 & 1"
1022 config C_AMBEN_B0_B1_B2
1023 bool "Enable Bank 0 & 1 & 2"
1026 bool "Enable All Banks"
1030 menu "EBIU_AMBCTL Control"
1032 hex "Bank 0 (AMBCTL0.L)"
1035 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1036 used to control the Asynchronous Memory Bank 0 settings.
1039 hex "Bank 1 (AMBCTL0.H)"
1041 default 0x5558 if BF54x
1043 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1044 used to control the Asynchronous Memory Bank 1 settings.
1047 hex "Bank 2 (AMBCTL1.L)"
1050 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1051 used to control the Asynchronous Memory Bank 2 settings.
1054 hex "Bank 3 (AMBCTL1.H)"
1057 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1058 used to control the Asynchronous Memory Bank 3 settings.
1062 config EBIU_MBSCTLVAL
1063 hex "EBIU Bank Select Control Register"
1068 hex "Flash Memory Mode Control Register"
1073 hex "Flash Memory Bank Control Register"
1078 #############################################################################
1079 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1085 Support for PCI bus.
1087 source "drivers/pci/Kconfig"
1090 bool "Support for hot-pluggable device"
1092 Say Y here if you want to plug devices into your computer while
1093 the system is running, and be able to use them quickly. In many
1094 cases, the devices can likewise be unplugged at any time too.
1096 One well known example of this is PCMCIA- or PC-cards, credit-card
1097 size devices such as network cards, modems or hard drives which are
1098 plugged into slots found on all modern laptop computers. Another
1099 example, used on modern desktops as well as laptops, is USB.
1101 Enable HOTPLUG and build a modular kernel. Get agent software
1102 (from <http://linux-hotplug.sourceforge.net/>) and install it.
1103 Then your kernel will automatically call out to a user mode "policy
1104 agent" (/sbin/hotplug) to load modules and set up software needed
1105 to use devices as you hotplug them.
1107 source "drivers/pcmcia/Kconfig"
1109 source "drivers/pci/hotplug/Kconfig"
1113 menu "Executable file formats"
1115 source "fs/Kconfig.binfmt"
1119 menu "Power management options"
1120 source "kernel/power/Kconfig"
1122 config ARCH_SUSPEND_POSSIBLE
1127 prompt "Standby Power Saving Mode"
1129 default PM_BFIN_SLEEP_DEEPER
1130 config PM_BFIN_SLEEP_DEEPER
1133 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1134 power dissipation by disabling the clock to the processor core (CCLK).
1135 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1136 to 0.85 V to provide the greatest power savings, while preserving the
1138 The PLL and system clock (SCLK) continue to operate at a very low
1139 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1140 the SDRAM is put into Self Refresh Mode. Typically an external event
1141 such as GPIO interrupt or RTC activity wakes up the processor.
1142 Various Peripherals such as UART, SPORT, PPI may not function as
1143 normal during Sleep Deeper, due to the reduced SCLK frequency.
1144 When in the sleep mode, system DMA access to L1 memory is not supported.
1146 If unsure, select "Sleep Deeper".
1148 config PM_BFIN_SLEEP
1151 Sleep Mode (High Power Savings) - The sleep mode reduces power
1152 dissipation by disabling the clock to the processor core (CCLK).
1153 The PLL and system clock (SCLK), however, continue to operate in
1154 this mode. Typically an external event or RTC activity will wake
1155 up the processor. When in the sleep mode, system DMA access to L1
1156 memory is not supported.
1158 If unsure, select "Sleep Deeper".
1161 config PM_WAKEUP_BY_GPIO
1162 bool "Allow Wakeup from Standby by GPIO"
1163 depends on PM && !BF54x
1165 config PM_WAKEUP_GPIO_NUMBER
1168 depends on PM_WAKEUP_BY_GPIO
1172 prompt "GPIO Polarity"
1173 depends on PM_WAKEUP_BY_GPIO
1174 default PM_WAKEUP_GPIO_POLAR_H
1175 config PM_WAKEUP_GPIO_POLAR_H
1177 config PM_WAKEUP_GPIO_POLAR_L
1179 config PM_WAKEUP_GPIO_POLAR_EDGE_F
1181 config PM_WAKEUP_GPIO_POLAR_EDGE_R
1183 config PM_WAKEUP_GPIO_POLAR_EDGE_B
1187 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1190 config PM_BFIN_WAKE_PH6
1191 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1192 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1195 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1197 config PM_BFIN_WAKE_GP
1198 bool "Allow Wake-Up from GPIOs"
1199 depends on PM && BF54x
1202 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1203 (all processors, except ADSP-BF549). This option sets
1204 the general-purpose wake-up enable (GPWE) control bit to enable
1205 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1206 On ADSP-BF549 this option enables the the same functionality on the
1207 /MRXON pin also PH7.
1211 menu "CPU Frequency scaling"
1213 source "drivers/cpufreq/Kconfig"
1215 config BFIN_CPU_FREQ
1218 select CPU_FREQ_TABLE
1222 bool "CPU Voltage scaling"
1223 depends on EXPERIMENTAL
1227 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1228 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1229 manuals. There is a theoretical risk that during VDDINT transitions
1234 source "net/Kconfig"
1236 source "drivers/Kconfig"
1240 source "arch/blackfin/Kconfig.debug"
1242 source "security/Kconfig"
1244 source "crypto/Kconfig"
1246 source "lib/Kconfig"
git://ftp.safe.ca / safe / jmp / linux-2.6 / blob