2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
14 config RWSEM_GENERIC_SPINLOCK
17 config RWSEM_XCHGADD_ALGORITHM
23 select HAVE_KERNEL_GZIP
24 select HAVE_KERNEL_BZIP2
25 select HAVE_KERNEL_LZMA
27 select ARCH_WANT_OPTIONAL_GPIOLIB
36 config GENERIC_FIND_NEXT_BIT
39 config GENERIC_HWEIGHT
42 config GENERIC_HARDIRQS
45 config GENERIC_IRQ_PROBE
51 config FORCE_MAX_ZONEORDER
55 config GENERIC_CALIBRATE_DELAY
58 config TRACE_IRQFLAGS_SUPPORT
63 source "kernel/Kconfig.preempt"
65 source "kernel/Kconfig.freezer"
67 menu "Blackfin Processor Options"
69 comment "Processor and Board Settings"
78 BF512 Processor Support.
83 BF514 Processor Support.
88 BF516 Processor Support.
93 BF518 Processor Support.
98 BF522 Processor Support.
103 BF523 Processor Support.
108 BF524 Processor Support.
113 BF525 Processor Support.
118 BF526 Processor Support.
123 BF527 Processor Support.
128 BF531 Processor Support.
133 BF532 Processor Support.
138 BF533 Processor Support.
143 BF534 Processor Support.
148 BF536 Processor Support.
153 BF537 Processor Support.
158 BF538 Processor Support.
163 BF539 Processor Support.
168 BF542 Processor Support.
173 BF542 Processor Support.
178 BF544 Processor Support.
183 BF544 Processor Support.
188 BF547 Processor Support.
193 BF547 Processor Support.
198 BF548 Processor Support.
203 BF548 Processor Support.
208 BF549 Processor Support.
213 BF549 Processor Support.
218 BF561 Processor Support.
225 bool "Symmetric multi-processing support"
227 This enables support for systems with more than one CPU,
228 like the dual core BF561. If you have a system with only one
229 CPU, say N. If you have a system with more than one CPU, say Y.
231 If you don't know what to do here, say N.
245 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
246 default 2 if (BF537 || BF536 || BF534)
247 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
248 default 4 if (BF538 || BF539)
252 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
253 default 3 if (BF537 || BF536 || BF534 || BF54xM)
254 default 5 if (BF561 || BF538 || BF539)
255 default 6 if (BF533 || BF532 || BF531)
259 default BF_REV_0_0 if (BF51x || BF52x)
260 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
261 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
265 depends on (BF51x || BF52x || (BF54x && !BF54xM))
269 depends on (BF52x || (BF54x && !BF54xM))
273 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
277 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
281 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
285 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
289 depends on (BF533 || BF532 || BF531)
301 depends on (BF512 || BF514 || BF516 || BF518)
306 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
311 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
316 depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
321 depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
324 config MEM_GENERIC_BOARD
326 depends on GENERIC_BOARD
329 config MEM_MT48LC64M4A2FB_7E
331 depends on (BFIN533_STAMP)
334 config MEM_MT48LC16M16A2TG_75
336 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
337 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
338 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
341 config MEM_MT48LC32M8A2_75
343 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
346 config MEM_MT48LC8M32B2B5_7
348 depends on (BFIN561_BLUETECHNIX_CM)
351 config MEM_MT48LC32M16A2TG_75
353 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
356 config MEM_MT48LC32M8A2_75
358 depends on (BFIN518F_EZBRD)
361 source "arch/blackfin/mach-bf518/Kconfig"
362 source "arch/blackfin/mach-bf527/Kconfig"
363 source "arch/blackfin/mach-bf533/Kconfig"
364 source "arch/blackfin/mach-bf561/Kconfig"
365 source "arch/blackfin/mach-bf537/Kconfig"
366 source "arch/blackfin/mach-bf538/Kconfig"
367 source "arch/blackfin/mach-bf548/Kconfig"
369 menu "Board customizations"
372 bool "Default bootloader kernel arguments"
375 string "Initial kernel command string"
376 depends on CMDLINE_BOOL
377 default "console=ttyBF0,57600"
379 If you don't have a boot loader capable of passing a command line string
380 to the kernel, you may specify one here. As a minimum, you should specify
381 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
384 hex "Kernel load address for booting"
386 range 0x1000 0x20000000
388 This option allows you to set the load address of the kernel.
389 This can be useful if you are on a board which has a small amount
390 of memory or you wish to reserve some memory at the beginning of
393 Note that you need to keep this value above 4k (0x1000) as this
394 memory region is used to capture NULL pointer references as well
395 as some core kernel functions.
398 hex "Kernel ROM Base"
401 range 0x20000000 0x20400000 if !(BF54x || BF561)
402 range 0x20000000 0x30000000 if (BF54x || BF561)
405 comment "Clock/PLL Setup"
408 int "Frequency of the crystal on the board in Hz"
409 default "11059200" if BFIN533_STAMP
410 default "27000000" if BFIN533_EZKIT
411 default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
412 default "30000000" if BFIN561_EZKIT
413 default "24576000" if PNAV10
414 default "10000000" if BFIN532_IP0X
416 The frequency of CLKIN crystal oscillator on the board in Hz.
417 Warning: This value should match the crystal on the board. Otherwise,
418 peripherals won't work properly.
420 config BFIN_KERNEL_CLOCK
421 bool "Re-program Clocks while Kernel boots?"
424 This option decides if kernel clocks are re-programed from the
425 bootloader settings. If the clocks are not set, the SDRAM settings
426 are also not changed, and the Bootloader does 100% of the hardware
431 depends on BFIN_KERNEL_CLOCK
436 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
439 If this is set the clock will be divided by 2, before it goes to the PLL.
443 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
445 default "22" if BFIN533_EZKIT
446 default "45" if BFIN533_STAMP
447 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
448 default "22" if BFIN533_BLUETECHNIX_CM
449 default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
450 default "20" if BFIN561_EZKIT
451 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
453 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
454 PLL Frequency = (Crystal Frequency) * (this setting)
457 prompt "Core Clock Divider"
458 depends on BFIN_KERNEL_CLOCK
461 This sets the frequency of the core. It can be 1, 2, 4 or 8
462 Core Frequency = (PLL frequency) / (this setting)
478 int "System Clock Divider"
479 depends on BFIN_KERNEL_CLOCK
483 This sets the frequency of the system clock (including SDRAM or DDR).
484 This can be between 1 and 15
485 System Clock = (PLL frequency) / (this setting)
488 prompt "DDR SDRAM Chip Type"
489 depends on BFIN_KERNEL_CLOCK
491 default MEM_MT46V32M16_5B
493 config MEM_MT46V32M16_6T
496 config MEM_MT46V32M16_5B
501 prompt "DDR/SDRAM Timing"
502 depends on BFIN_KERNEL_CLOCK
503 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
505 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
506 The calculated SDRAM timing parameters may not be 100%
507 accurate - This option is therefore marked experimental.
509 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
510 bool "Calculate Timings (EXPERIMENTAL)"
511 depends on EXPERIMENTAL
513 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
514 bool "Provide accurate Timings based on target SCLK"
516 Please consult the Blackfin Hardware Reference Manuals as well
517 as the memory device datasheet.
518 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
521 menu "Memory Init Control"
522 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
539 config MEM_EBIU_DDRQUE
556 # Max & Min Speeds for various Chips
560 default 400000000 if BF512
561 default 400000000 if BF514
562 default 400000000 if BF516
563 default 400000000 if BF518
564 default 600000000 if BF522
565 default 400000000 if BF523
566 default 400000000 if BF524
567 default 600000000 if BF525
568 default 400000000 if BF526
569 default 600000000 if BF527
570 default 400000000 if BF531
571 default 400000000 if BF532
572 default 750000000 if BF533
573 default 500000000 if BF534
574 default 400000000 if BF536
575 default 600000000 if BF537
576 default 533333333 if BF538
577 default 533333333 if BF539
578 default 600000000 if BF542
579 default 533333333 if BF544
580 default 600000000 if BF547
581 default 600000000 if BF548
582 default 533333333 if BF549
583 default 600000000 if BF561
597 comment "Kernel Timer/Scheduler"
599 source kernel/Kconfig.hz
605 config GENERIC_CLOCKEVENTS
606 bool "Generic clock events"
607 depends on GENERIC_TIME
611 prompt "Kernel Tick Source"
612 depends on GENERIC_CLOCKEVENTS
613 default TICKSOURCE_CORETMR
615 config TICKSOURCE_GPTMR0
616 bool "Gptimer0 (SCLK domain)"
620 config TICKSOURCE_CORETMR
621 bool "Core timer (CCLK domain)"
625 config CYCLES_CLOCKSOURCE
626 bool "Use 'CYCLES' as a clocksource"
627 depends on GENERIC_CLOCKEVENTS
628 depends on !BFIN_SCRATCH_REG_CYCLES
631 If you say Y here, you will enable support for using the 'cycles'
632 registers as a clock source. Doing so means you will be unable to
633 safely write to the 'cycles' register during runtime. You will
634 still be able to read it (such as for performance monitoring), but
635 writing the registers will most likely crash the kernel.
637 config GPTMR0_CLOCKSOURCE
638 bool "Use GPTimer0 as a clocksource (higher rating)"
639 depends on GENERIC_CLOCKEVENTS
640 depends on !TICKSOURCE_GPTMR0
642 source kernel/time/Kconfig
647 prompt "Blackfin Exception Scratch Register"
648 default BFIN_SCRATCH_REG_RETN
650 Select the resource to reserve for the Exception handler:
651 - RETN: Non-Maskable Interrupt (NMI)
652 - RETE: Exception Return (JTAG/ICE)
653 - CYCLES: Performance counter
655 If you are unsure, please select "RETN".
657 config BFIN_SCRATCH_REG_RETN
660 Use the RETN register in the Blackfin exception handler
661 as a stack scratch register. This means you cannot
662 safely use NMI on the Blackfin while running Linux, but
663 you can debug the system with a JTAG ICE and use the
664 CYCLES performance registers.
666 If you are unsure, please select "RETN".
668 config BFIN_SCRATCH_REG_RETE
671 Use the RETE register in the Blackfin exception handler
672 as a stack scratch register. This means you cannot
673 safely use a JTAG ICE while debugging a Blackfin board,
674 but you can safely use the CYCLES performance registers
677 If you are unsure, please select "RETN".
679 config BFIN_SCRATCH_REG_CYCLES
682 Use the CYCLES register in the Blackfin exception handler
683 as a stack scratch register. This means you cannot
684 safely use the CYCLES performance registers on a Blackfin
685 board at anytime, but you can debug the system with a JTAG
688 If you are unsure, please select "RETN".
695 menu "Blackfin Kernel Optimizations"
698 comment "Memory Optimizations"
701 bool "Locate interrupt entry code in L1 Memory"
704 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
705 into L1 instruction memory. (less latency)
707 config EXCPT_IRQ_SYSC_L1
708 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
711 If enabled, the entire ASM lowlevel exception and interrupt entry code
712 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
716 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
719 If enabled, the frequently called do_irq dispatcher function is linked
720 into L1 instruction memory. (less latency)
722 config CORE_TIMER_IRQ_L1
723 bool "Locate frequently called timer_interrupt() function in L1 Memory"
726 If enabled, the frequently called timer_interrupt() function is linked
727 into L1 instruction memory. (less latency)
730 bool "Locate frequently idle function in L1 Memory"
733 If enabled, the frequently called idle function is linked
734 into L1 instruction memory. (less latency)
737 bool "Locate kernel schedule function in L1 Memory"
740 If enabled, the frequently called kernel schedule is linked
741 into L1 instruction memory. (less latency)
743 config ARITHMETIC_OPS_L1
744 bool "Locate kernel owned arithmetic functions in L1 Memory"
747 If enabled, arithmetic functions are linked
748 into L1 instruction memory. (less latency)
751 bool "Locate access_ok function in L1 Memory"
754 If enabled, the access_ok function is linked
755 into L1 instruction memory. (less latency)
758 bool "Locate memset function in L1 Memory"
761 If enabled, the memset function is linked
762 into L1 instruction memory. (less latency)
765 bool "Locate memcpy function in L1 Memory"
768 If enabled, the memcpy function is linked
769 into L1 instruction memory. (less latency)
771 config SYS_BFIN_SPINLOCK_L1
772 bool "Locate sys_bfin_spinlock function in L1 Memory"
775 If enabled, sys_bfin_spinlock function is linked
776 into L1 instruction memory. (less latency)
778 config IP_CHECKSUM_L1
779 bool "Locate IP Checksum function in L1 Memory"
782 If enabled, the IP Checksum function is linked
783 into L1 instruction memory. (less latency)
785 config CACHELINE_ALIGNED_L1
786 bool "Locate cacheline_aligned data to L1 Data Memory"
791 If enabled, cacheline_aligned data is linked
792 into L1 data memory. (less latency)
794 config SYSCALL_TAB_L1
795 bool "Locate Syscall Table L1 Data Memory"
799 If enabled, the Syscall LUT is linked
800 into L1 data memory. (less latency)
802 config CPLB_SWITCH_TAB_L1
803 bool "Locate CPLB Switch Tables L1 Data Memory"
807 If enabled, the CPLB Switch Tables are linked
808 into L1 data memory. (less latency)
811 bool "Support locating application stack in L1 Scratch Memory"
814 If enabled the application stack can be located in L1
815 scratch memory (less latency).
817 Currently only works with FLAT binaries.
819 config EXCEPTION_L1_SCRATCH
820 bool "Locate exception stack in L1 Scratch Memory"
822 depends on !APP_STACK_L1
824 Whenever an exception occurs, use the L1 Scratch memory for
825 stack storage. You cannot place the stacks of FLAT binaries
826 in L1 when using this option.
828 If you don't use L1 Scratch, then you should say Y here.
830 comment "Speed Optimizations"
831 config BFIN_INS_LOWOVERHEAD
832 bool "ins[bwl] low overhead, higher interrupt latency"
835 Reads on the Blackfin are speculative. In Blackfin terms, this means
836 they can be interrupted at any time (even after they have been issued
837 on to the external bus), and re-issued after the interrupt occurs.
838 For memory - this is not a big deal, since memory does not change if
841 If a FIFO is sitting on the end of the read, it will see two reads,
842 when the core only sees one since the FIFO receives both the read
843 which is cancelled (and not delivered to the core) and the one which
844 is re-issued (which is delivered to the core).
846 To solve this, interrupts are turned off before reads occur to
847 I/O space. This option controls which the overhead/latency of
848 controlling interrupts during this time
849 "n" turns interrupts off every read
850 (higher overhead, but lower interrupt latency)
851 "y" turns interrupts off every loop
852 (low overhead, but longer interrupt latency)
854 default behavior is to leave this set to on (type "Y"). If you are experiencing
855 interrupt latency issues, it is safe and OK to turn this off.
860 prompt "Kernel executes from"
862 Choose the memory type that the kernel will be running in.
867 The kernel will be resident in RAM when running.
872 The kernel will be resident in FLASH/ROM when running.
879 tristate "Enable Blackfin General Purpose Timers API"
882 Enable support for the General Purpose Timers API. If you
885 To compile this driver as a module, choose M here: the module
886 will be called gptimers.ko.
889 prompt "Uncached DMA region"
890 default DMA_UNCACHED_1M
891 config DMA_UNCACHED_4M
892 bool "Enable 4M DMA region"
893 config DMA_UNCACHED_2M
894 bool "Enable 2M DMA region"
895 config DMA_UNCACHED_1M
896 bool "Enable 1M DMA region"
897 config DMA_UNCACHED_NONE
898 bool "Disable DMA region"
902 comment "Cache Support"
907 config BFIN_DCACHE_BANKA
908 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
909 depends on BFIN_DCACHE && !BF531
911 config BFIN_ICACHE_LOCK
912 bool "Enable Instruction Cache Locking"
915 prompt "External memory cache policy"
916 depends on BFIN_DCACHE
917 default BFIN_WB if !SMP
918 default BFIN_WT if SMP
924 Cached data will be written back to SDRAM only when needed.
925 This can give a nice increase in performance, but beware of
926 broken drivers that do not properly invalidate/flush their
929 Write Through Policy:
930 Cached data will always be written back to SDRAM when the
931 cache is updated. This is a completely safe setting, but
932 performance is worse than Write Back.
934 If you are unsure of the options and you want to be safe,
935 then go with Write Through.
941 Cached data will be written back to SDRAM only when needed.
942 This can give a nice increase in performance, but beware of
943 broken drivers that do not properly invalidate/flush their
946 Write Through Policy:
947 Cached data will always be written back to SDRAM when the
948 cache is updated. This is a completely safe setting, but
949 performance is worse than Write Back.
951 If you are unsure of the options and you want to be safe,
952 then go with Write Through.
957 prompt "L2 SRAM cache policy"
958 depends on (BF54x || BF561)
968 config BFIN_L2_NOT_CACHED
974 bool "Enable the memory protection unit (EXPERIMENTAL)"
977 Use the processor's MPU to protect applications from accessing
978 memory they do not own. This comes at a performance penalty
979 and is recommended only for debugging.
981 comment "Asynchronous Memory Configuration"
983 menu "EBIU_AMGCTL Global Control"
989 bool "DMA has priority over core for ext. accesses"
994 bool "Bank 0 16 bit packing enable"
999 bool "Bank 1 16 bit packing enable"
1004 bool "Bank 2 16 bit packing enable"
1009 bool "Bank 3 16 bit packing enable"
1013 prompt "Enable Asynchronous Memory Banks"
1017 bool "Disable All Banks"
1020 bool "Enable Bank 0"
1022 config C_AMBEN_B0_B1
1023 bool "Enable Bank 0 & 1"
1025 config C_AMBEN_B0_B1_B2
1026 bool "Enable Bank 0 & 1 & 2"
1029 bool "Enable All Banks"
1033 menu "EBIU_AMBCTL Control"
1035 hex "Bank 0 (AMBCTL0.L)"
1038 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1039 used to control the Asynchronous Memory Bank 0 settings.
1042 hex "Bank 1 (AMBCTL0.H)"
1044 default 0x5558 if BF54x
1046 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1047 used to control the Asynchronous Memory Bank 1 settings.
1050 hex "Bank 2 (AMBCTL1.L)"
1053 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1054 used to control the Asynchronous Memory Bank 2 settings.
1057 hex "Bank 3 (AMBCTL1.H)"
1060 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1061 used to control the Asynchronous Memory Bank 3 settings.
1065 config EBIU_MBSCTLVAL
1066 hex "EBIU Bank Select Control Register"
1071 hex "Flash Memory Mode Control Register"
1076 hex "Flash Memory Bank Control Register"
1081 #############################################################################
1082 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1088 Support for PCI bus.
1090 source "drivers/pci/Kconfig"
1093 bool "Support for hot-pluggable device"
1095 Say Y here if you want to plug devices into your computer while
1096 the system is running, and be able to use them quickly. In many
1097 cases, the devices can likewise be unplugged at any time too.
1099 One well known example of this is PCMCIA- or PC-cards, credit-card
1100 size devices such as network cards, modems or hard drives which are
1101 plugged into slots found on all modern laptop computers. Another
1102 example, used on modern desktops as well as laptops, is USB.
1104 Enable HOTPLUG and build a modular kernel. Get agent software
1105 (from <http://linux-hotplug.sourceforge.net/>) and install it.
1106 Then your kernel will automatically call out to a user mode "policy
1107 agent" (/sbin/hotplug) to load modules and set up software needed
1108 to use devices as you hotplug them.
1110 source "drivers/pcmcia/Kconfig"
1112 source "drivers/pci/hotplug/Kconfig"
1116 menu "Executable file formats"
1118 source "fs/Kconfig.binfmt"
1122 menu "Power management options"
1123 source "kernel/power/Kconfig"
1125 config ARCH_SUSPEND_POSSIBLE
1130 prompt "Standby Power Saving Mode"
1132 default PM_BFIN_SLEEP_DEEPER
1133 config PM_BFIN_SLEEP_DEEPER
1136 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1137 power dissipation by disabling the clock to the processor core (CCLK).
1138 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1139 to 0.85 V to provide the greatest power savings, while preserving the
1141 The PLL and system clock (SCLK) continue to operate at a very low
1142 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1143 the SDRAM is put into Self Refresh Mode. Typically an external event
1144 such as GPIO interrupt or RTC activity wakes up the processor.
1145 Various Peripherals such as UART, SPORT, PPI may not function as
1146 normal during Sleep Deeper, due to the reduced SCLK frequency.
1147 When in the sleep mode, system DMA access to L1 memory is not supported.
1149 If unsure, select "Sleep Deeper".
1151 config PM_BFIN_SLEEP
1154 Sleep Mode (High Power Savings) - The sleep mode reduces power
1155 dissipation by disabling the clock to the processor core (CCLK).
1156 The PLL and system clock (SCLK), however, continue to operate in
1157 this mode. Typically an external event or RTC activity will wake
1158 up the processor. When in the sleep mode, system DMA access to L1
1159 memory is not supported.
1161 If unsure, select "Sleep Deeper".
1164 config PM_WAKEUP_BY_GPIO
1165 bool "Allow Wakeup from Standby by GPIO"
1166 depends on PM && !BF54x
1168 config PM_WAKEUP_GPIO_NUMBER
1171 depends on PM_WAKEUP_BY_GPIO
1175 prompt "GPIO Polarity"
1176 depends on PM_WAKEUP_BY_GPIO
1177 default PM_WAKEUP_GPIO_POLAR_H
1178 config PM_WAKEUP_GPIO_POLAR_H
1180 config PM_WAKEUP_GPIO_POLAR_L
1182 config PM_WAKEUP_GPIO_POLAR_EDGE_F
1184 config PM_WAKEUP_GPIO_POLAR_EDGE_R
1186 config PM_WAKEUP_GPIO_POLAR_EDGE_B
1190 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1193 config PM_BFIN_WAKE_PH6
1194 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1195 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1198 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1200 config PM_BFIN_WAKE_GP
1201 bool "Allow Wake-Up from GPIOs"
1202 depends on PM && BF54x
1205 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1206 (all processors, except ADSP-BF549). This option sets
1207 the general-purpose wake-up enable (GPWE) control bit to enable
1208 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1209 On ADSP-BF549 this option enables the the same functionality on the
1210 /MRXON pin also PH7.
1214 menu "CPU Frequency scaling"
1216 source "drivers/cpufreq/Kconfig"
1218 config BFIN_CPU_FREQ
1221 select CPU_FREQ_TABLE
1225 bool "CPU Voltage scaling"
1226 depends on EXPERIMENTAL
1230 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1231 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1232 manuals. There is a theoretical risk that during VDDINT transitions
1237 source "net/Kconfig"
1239 source "drivers/Kconfig"
1243 source "arch/blackfin/Kconfig.debug"
1245 source "security/Kconfig"
1247 source "crypto/Kconfig"
1249 source "lib/Kconfig"