2 * Copyright (C) 2005-2006 Atmel Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/init.h>
11 #include <linux/platform_device.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/spi/spi.h>
17 #include <asm/arch/at32ap7000.h>
18 #include <asm/arch/board.h>
19 #include <asm/arch/portmux.h>
21 #include <video/atmel_lcdc.h>
29 * We can reduce the code size a bit by using a constant here. Since
30 * this file is completely chip-specific, it's safe to not use
31 * ioremap. Generic drivers should of course never do this.
33 #define AT32_PM_BASE 0xfff00000
38 .end = base + 0x3ff, \
39 .flags = IORESOURCE_MEM, \
45 .flags = IORESOURCE_IRQ, \
47 #define NAMED_IRQ(num, _name) \
52 .flags = IORESOURCE_IRQ, \
55 /* REVISIT these assume *every* device supports DMA, but several
56 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
58 #define DEFINE_DEV(_name, _id) \
59 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
60 static struct platform_device _name##_id##_device = { \
64 .dma_mask = &_name##_id##_dma_mask, \
65 .coherent_dma_mask = DMA_32BIT_MASK, \
67 .resource = _name##_id##_resource, \
68 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
70 #define DEFINE_DEV_DATA(_name, _id) \
71 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
72 static struct platform_device _name##_id##_device = { \
76 .dma_mask = &_name##_id##_dma_mask, \
77 .platform_data = &_name##_id##_data, \
78 .coherent_dma_mask = DMA_32BIT_MASK, \
80 .resource = _name##_id##_resource, \
81 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
84 #define select_peripheral(pin, periph, flags) \
85 at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
87 #define DEV_CLK(_name, devname, bus, _index) \
88 static struct clk devname##_##_name = { \
90 .dev = &devname##_device.dev, \
91 .parent = &bus##_clk, \
92 .mode = bus##_clk_mode, \
93 .get_rate = bus##_clk_get_rate, \
97 static DEFINE_SPINLOCK(pm_lock);
99 unsigned long at32ap7000_osc_rates[3] = {
101 /* FIXME: these are ATSTK1002-specific */
106 static unsigned long osc_get_rate(struct clk *clk)
108 return at32ap7000_osc_rates[clk->index];
111 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
113 unsigned long div, mul, rate;
115 if (!(control & PM_BIT(PLLEN)))
118 div = PM_BFEXT(PLLDIV, control) + 1;
119 mul = PM_BFEXT(PLLMUL, control) + 1;
121 rate = clk->parent->get_rate(clk->parent);
122 rate = (rate + div / 2) / div;
128 static unsigned long pll0_get_rate(struct clk *clk)
132 control = pm_readl(PLL0);
134 return pll_get_rate(clk, control);
137 static unsigned long pll1_get_rate(struct clk *clk)
141 control = pm_readl(PLL1);
143 return pll_get_rate(clk, control);
147 * The AT32AP7000 has five primary clock sources: One 32kHz
148 * oscillator, two crystal oscillators and two PLLs.
150 static struct clk osc32k = {
152 .get_rate = osc_get_rate,
156 static struct clk osc0 = {
158 .get_rate = osc_get_rate,
162 static struct clk osc1 = {
164 .get_rate = osc_get_rate,
167 static struct clk pll0 = {
169 .get_rate = pll0_get_rate,
172 static struct clk pll1 = {
174 .get_rate = pll1_get_rate,
179 * The main clock can be either osc0 or pll0. The boot loader may
180 * have chosen one for us, so we don't really know which one until we
181 * have a look at the SM.
183 static struct clk *main_clock;
186 * Synchronous clocks are generated from the main clock. The clocks
187 * must satisfy the constraint
188 * fCPU >= fHSB >= fPB
189 * i.e. each clock must not be faster than its parent.
191 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
193 return main_clock->get_rate(main_clock) >> shift;
196 static void cpu_clk_mode(struct clk *clk, int enabled)
201 spin_lock_irqsave(&pm_lock, flags);
202 mask = pm_readl(CPU_MASK);
204 mask |= 1 << clk->index;
206 mask &= ~(1 << clk->index);
207 pm_writel(CPU_MASK, mask);
208 spin_unlock_irqrestore(&pm_lock, flags);
211 static unsigned long cpu_clk_get_rate(struct clk *clk)
213 unsigned long cksel, shift = 0;
215 cksel = pm_readl(CKSEL);
216 if (cksel & PM_BIT(CPUDIV))
217 shift = PM_BFEXT(CPUSEL, cksel) + 1;
219 return bus_clk_get_rate(clk, shift);
222 static void hsb_clk_mode(struct clk *clk, int enabled)
227 spin_lock_irqsave(&pm_lock, flags);
228 mask = pm_readl(HSB_MASK);
230 mask |= 1 << clk->index;
232 mask &= ~(1 << clk->index);
233 pm_writel(HSB_MASK, mask);
234 spin_unlock_irqrestore(&pm_lock, flags);
237 static unsigned long hsb_clk_get_rate(struct clk *clk)
239 unsigned long cksel, shift = 0;
241 cksel = pm_readl(CKSEL);
242 if (cksel & PM_BIT(HSBDIV))
243 shift = PM_BFEXT(HSBSEL, cksel) + 1;
245 return bus_clk_get_rate(clk, shift);
248 static void pba_clk_mode(struct clk *clk, int enabled)
253 spin_lock_irqsave(&pm_lock, flags);
254 mask = pm_readl(PBA_MASK);
256 mask |= 1 << clk->index;
258 mask &= ~(1 << clk->index);
259 pm_writel(PBA_MASK, mask);
260 spin_unlock_irqrestore(&pm_lock, flags);
263 static unsigned long pba_clk_get_rate(struct clk *clk)
265 unsigned long cksel, shift = 0;
267 cksel = pm_readl(CKSEL);
268 if (cksel & PM_BIT(PBADIV))
269 shift = PM_BFEXT(PBASEL, cksel) + 1;
271 return bus_clk_get_rate(clk, shift);
274 static void pbb_clk_mode(struct clk *clk, int enabled)
279 spin_lock_irqsave(&pm_lock, flags);
280 mask = pm_readl(PBB_MASK);
282 mask |= 1 << clk->index;
284 mask &= ~(1 << clk->index);
285 pm_writel(PBB_MASK, mask);
286 spin_unlock_irqrestore(&pm_lock, flags);
289 static unsigned long pbb_clk_get_rate(struct clk *clk)
291 unsigned long cksel, shift = 0;
293 cksel = pm_readl(CKSEL);
294 if (cksel & PM_BIT(PBBDIV))
295 shift = PM_BFEXT(PBBSEL, cksel) + 1;
297 return bus_clk_get_rate(clk, shift);
300 static struct clk cpu_clk = {
302 .get_rate = cpu_clk_get_rate,
305 static struct clk hsb_clk = {
308 .get_rate = hsb_clk_get_rate,
310 static struct clk pba_clk = {
313 .mode = hsb_clk_mode,
314 .get_rate = pba_clk_get_rate,
317 static struct clk pbb_clk = {
320 .mode = hsb_clk_mode,
321 .get_rate = pbb_clk_get_rate,
326 /* --------------------------------------------------------------------
327 * Generic Clock operations
328 * -------------------------------------------------------------------- */
330 static void genclk_mode(struct clk *clk, int enabled)
334 control = pm_readl(GCCTRL(clk->index));
336 control |= PM_BIT(CEN);
338 control &= ~PM_BIT(CEN);
339 pm_writel(GCCTRL(clk->index), control);
342 static unsigned long genclk_get_rate(struct clk *clk)
345 unsigned long div = 1;
347 control = pm_readl(GCCTRL(clk->index));
348 if (control & PM_BIT(DIVEN))
349 div = 2 * (PM_BFEXT(DIV, control) + 1);
351 return clk->parent->get_rate(clk->parent) / div;
354 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
357 unsigned long parent_rate, actual_rate, div;
359 parent_rate = clk->parent->get_rate(clk->parent);
360 control = pm_readl(GCCTRL(clk->index));
362 if (rate > 3 * parent_rate / 4) {
363 actual_rate = parent_rate;
364 control &= ~PM_BIT(DIVEN);
366 div = (parent_rate + rate) / (2 * rate) - 1;
367 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
368 actual_rate = parent_rate / (2 * (div + 1));
371 dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
372 clk->name, rate, actual_rate);
375 pm_writel(GCCTRL(clk->index), control);
380 int genclk_set_parent(struct clk *clk, struct clk *parent)
384 dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
385 clk->name, parent->name, clk->parent->name);
387 control = pm_readl(GCCTRL(clk->index));
389 if (parent == &osc1 || parent == &pll1)
390 control |= PM_BIT(OSCSEL);
391 else if (parent == &osc0 || parent == &pll0)
392 control &= ~PM_BIT(OSCSEL);
396 if (parent == &pll0 || parent == &pll1)
397 control |= PM_BIT(PLLSEL);
399 control &= ~PM_BIT(PLLSEL);
401 pm_writel(GCCTRL(clk->index), control);
402 clk->parent = parent;
407 static void __init genclk_init_parent(struct clk *clk)
412 BUG_ON(clk->index > 7);
414 control = pm_readl(GCCTRL(clk->index));
415 if (control & PM_BIT(OSCSEL))
416 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
418 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
420 clk->parent = parent;
423 /* --------------------------------------------------------------------
425 * -------------------------------------------------------------------- */
426 static struct resource at32_pm0_resource[] = {
430 .flags = IORESOURCE_MEM,
435 static struct resource at32ap700x_rtc0_resource[] = {
439 .flags = IORESOURCE_MEM,
444 static struct resource at32_wdt0_resource[] = {
448 .flags = IORESOURCE_MEM,
452 static struct resource at32_eic0_resource[] = {
456 .flags = IORESOURCE_MEM,
461 DEFINE_DEV(at32_pm, 0);
462 DEFINE_DEV(at32ap700x_rtc, 0);
463 DEFINE_DEV(at32_wdt, 0);
464 DEFINE_DEV(at32_eic, 0);
467 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
470 static struct clk at32_pm_pclk = {
472 .dev = &at32_pm0_device.dev,
474 .mode = pbb_clk_mode,
475 .get_rate = pbb_clk_get_rate,
480 static struct resource intc0_resource[] = {
483 struct platform_device at32_intc0_device = {
486 .resource = intc0_resource,
487 .num_resources = ARRAY_SIZE(intc0_resource),
489 DEV_CLK(pclk, at32_intc0, pbb, 1);
491 static struct clk ebi_clk = {
494 .mode = hsb_clk_mode,
495 .get_rate = hsb_clk_get_rate,
498 static struct clk hramc_clk = {
501 .mode = hsb_clk_mode,
502 .get_rate = hsb_clk_get_rate,
507 static struct resource smc0_resource[] = {
511 DEV_CLK(pclk, smc0, pbb, 13);
512 DEV_CLK(mck, smc0, hsb, 0);
514 static struct platform_device pdc_device = {
518 DEV_CLK(hclk, pdc, hsb, 4);
519 DEV_CLK(pclk, pdc, pba, 16);
521 static struct clk pico_clk = {
524 .mode = cpu_clk_mode,
525 .get_rate = cpu_clk_get_rate,
529 /* --------------------------------------------------------------------
531 * -------------------------------------------------------------------- */
533 static struct clk hmatrix_clk = {
534 .name = "hmatrix_clk",
536 .mode = pbb_clk_mode,
537 .get_rate = pbb_clk_get_rate,
541 #define HMATRIX_BASE ((void __iomem *)0xfff00800)
543 #define hmatrix_readl(reg) \
544 __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
545 #define hmatrix_writel(reg,value) \
546 __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
549 * Set bits in the HMATRIX Special Function Register (SFR) used by the
550 * External Bus Interface (EBI). This can be used to enable special
551 * features like CompactFlash support, NAND Flash support, etc. on
552 * certain chipselects.
554 static inline void set_ebi_sfr_bits(u32 mask)
558 clk_enable(&hmatrix_clk);
559 sfr = hmatrix_readl(SFR4);
561 hmatrix_writel(SFR4, sfr);
562 clk_disable(&hmatrix_clk);
565 /* --------------------------------------------------------------------
566 * System Timer/Counter (TC)
567 * -------------------------------------------------------------------- */
568 static struct resource at32_systc0_resource[] = {
572 struct platform_device at32_systc0_device = {
575 .resource = at32_systc0_resource,
576 .num_resources = ARRAY_SIZE(at32_systc0_resource),
578 DEV_CLK(pclk, at32_systc0, pbb, 3);
580 /* --------------------------------------------------------------------
582 * -------------------------------------------------------------------- */
584 static struct resource pio0_resource[] = {
589 DEV_CLK(mck, pio0, pba, 10);
591 static struct resource pio1_resource[] = {
596 DEV_CLK(mck, pio1, pba, 11);
598 static struct resource pio2_resource[] = {
603 DEV_CLK(mck, pio2, pba, 12);
605 static struct resource pio3_resource[] = {
610 DEV_CLK(mck, pio3, pba, 13);
612 static struct resource pio4_resource[] = {
617 DEV_CLK(mck, pio4, pba, 14);
619 void __init at32_add_system_devices(void)
621 platform_device_register(&at32_pm0_device);
622 platform_device_register(&at32_intc0_device);
623 platform_device_register(&at32ap700x_rtc0_device);
624 platform_device_register(&at32_wdt0_device);
625 platform_device_register(&at32_eic0_device);
626 platform_device_register(&smc0_device);
627 platform_device_register(&pdc_device);
629 platform_device_register(&at32_systc0_device);
631 platform_device_register(&pio0_device);
632 platform_device_register(&pio1_device);
633 platform_device_register(&pio2_device);
634 platform_device_register(&pio3_device);
635 platform_device_register(&pio4_device);
638 /* --------------------------------------------------------------------
640 * -------------------------------------------------------------------- */
642 static struct atmel_uart_data atmel_usart0_data = {
646 static struct resource atmel_usart0_resource[] = {
650 DEFINE_DEV_DATA(atmel_usart, 0);
651 DEV_CLK(usart, atmel_usart0, pba, 4);
653 static struct atmel_uart_data atmel_usart1_data = {
657 static struct resource atmel_usart1_resource[] = {
661 DEFINE_DEV_DATA(atmel_usart, 1);
662 DEV_CLK(usart, atmel_usart1, pba, 4);
664 static struct atmel_uart_data atmel_usart2_data = {
668 static struct resource atmel_usart2_resource[] = {
672 DEFINE_DEV_DATA(atmel_usart, 2);
673 DEV_CLK(usart, atmel_usart2, pba, 5);
675 static struct atmel_uart_data atmel_usart3_data = {
679 static struct resource atmel_usart3_resource[] = {
683 DEFINE_DEV_DATA(atmel_usart, 3);
684 DEV_CLK(usart, atmel_usart3, pba, 6);
686 static inline void configure_usart0_pins(void)
688 select_peripheral(PA(8), PERIPH_B, 0); /* RXD */
689 select_peripheral(PA(9), PERIPH_B, 0); /* TXD */
692 static inline void configure_usart1_pins(void)
694 select_peripheral(PA(17), PERIPH_A, 0); /* RXD */
695 select_peripheral(PA(18), PERIPH_A, 0); /* TXD */
698 static inline void configure_usart2_pins(void)
700 select_peripheral(PB(26), PERIPH_B, 0); /* RXD */
701 select_peripheral(PB(27), PERIPH_B, 0); /* TXD */
704 static inline void configure_usart3_pins(void)
706 select_peripheral(PB(18), PERIPH_B, 0); /* RXD */
707 select_peripheral(PB(17), PERIPH_B, 0); /* TXD */
710 static struct platform_device *__initdata at32_usarts[4];
712 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
714 struct platform_device *pdev;
718 pdev = &atmel_usart0_device;
719 configure_usart0_pins();
722 pdev = &atmel_usart1_device;
723 configure_usart1_pins();
726 pdev = &atmel_usart2_device;
727 configure_usart2_pins();
730 pdev = &atmel_usart3_device;
731 configure_usart3_pins();
737 if (PXSEG(pdev->resource[0].start) == P4SEG) {
738 /* Addresses in the P4 segment are permanently mapped 1:1 */
739 struct atmel_uart_data *data = pdev->dev.platform_data;
740 data->regs = (void __iomem *)pdev->resource[0].start;
744 at32_usarts[line] = pdev;
747 struct platform_device *__init at32_add_device_usart(unsigned int id)
749 platform_device_register(at32_usarts[id]);
750 return at32_usarts[id];
753 struct platform_device *atmel_default_console_device;
755 void __init at32_setup_serial_console(unsigned int usart_id)
757 atmel_default_console_device = at32_usarts[usart_id];
760 /* --------------------------------------------------------------------
762 * -------------------------------------------------------------------- */
764 static struct eth_platform_data macb0_data;
765 static struct resource macb0_resource[] = {
769 DEFINE_DEV_DATA(macb, 0);
770 DEV_CLK(hclk, macb0, hsb, 8);
771 DEV_CLK(pclk, macb0, pbb, 6);
773 static struct eth_platform_data macb1_data;
774 static struct resource macb1_resource[] = {
778 DEFINE_DEV_DATA(macb, 1);
779 DEV_CLK(hclk, macb1, hsb, 9);
780 DEV_CLK(pclk, macb1, pbb, 7);
782 struct platform_device *__init
783 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
785 struct platform_device *pdev;
789 pdev = &macb0_device;
791 select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */
792 select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */
793 select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */
794 select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */
795 select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */
796 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
797 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
798 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
799 select_peripheral(PC(16), PERIPH_A, 0); /* MDC */
800 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
802 if (!data->is_rmii) {
803 select_peripheral(PC(0), PERIPH_A, 0); /* COL */
804 select_peripheral(PC(1), PERIPH_A, 0); /* CRS */
805 select_peripheral(PC(2), PERIPH_A, 0); /* TXER */
806 select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */
807 select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */
808 select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
809 select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
810 select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
811 select_peripheral(PC(18), PERIPH_A, 0); /* SPD */
816 pdev = &macb1_device;
818 select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */
819 select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */
820 select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */
821 select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */
822 select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */
823 select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */
824 select_peripheral(PD(5), PERIPH_B, 0); /* RXER */
825 select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */
826 select_peripheral(PD(3), PERIPH_B, 0); /* MDC */
827 select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */
829 if (!data->is_rmii) {
830 select_peripheral(PC(19), PERIPH_B, 0); /* COL */
831 select_peripheral(PC(23), PERIPH_B, 0); /* CRS */
832 select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
833 select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
834 select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
835 select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
836 select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
837 select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
838 select_peripheral(PD(15), PERIPH_B, 0); /* SPD */
846 memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
847 platform_device_register(pdev);
852 /* --------------------------------------------------------------------
854 * -------------------------------------------------------------------- */
855 static struct resource atmel_spi0_resource[] = {
859 DEFINE_DEV(atmel_spi, 0);
860 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
862 static struct resource atmel_spi1_resource[] = {
866 DEFINE_DEV(atmel_spi, 1);
867 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
870 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
871 unsigned int n, const u8 *pins)
873 unsigned int pin, mode;
875 for (; n; n--, b++) {
876 b->bus_num = bus_num;
877 if (b->chip_select >= 4)
879 pin = (unsigned)b->controller_data;
881 pin = pins[b->chip_select];
882 b->controller_data = (void *)pin;
884 mode = AT32_GPIOF_OUTPUT;
885 if (!(b->mode & SPI_CS_HIGH))
886 mode |= AT32_GPIOF_HIGH;
887 at32_select_gpio(pin, mode);
891 struct platform_device *__init
892 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
895 * Manage the chipselects as GPIOs, normally using the same pins
896 * the SPI controller expects; but boards can use other pins.
898 static u8 __initdata spi0_pins[] =
899 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
900 GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
901 static u8 __initdata spi1_pins[] =
902 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
903 GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
904 struct platform_device *pdev;
908 pdev = &atmel_spi0_device;
909 select_peripheral(PA(0), PERIPH_A, 0); /* MISO */
910 select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
911 select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
912 at32_spi_setup_slaves(0, b, n, spi0_pins);
916 pdev = &atmel_spi1_device;
917 select_peripheral(PB(0), PERIPH_B, 0); /* MISO */
918 select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
919 select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
920 at32_spi_setup_slaves(1, b, n, spi1_pins);
927 spi_register_board_info(b, n);
928 platform_device_register(pdev);
932 /* --------------------------------------------------------------------
934 * -------------------------------------------------------------------- */
935 static struct atmel_lcdfb_info atmel_lcdfb0_data;
936 static struct resource atmel_lcdfb0_resource[] = {
940 .flags = IORESOURCE_MEM,
944 /* Placeholder for pre-allocated fb memory */
950 DEFINE_DEV_DATA(atmel_lcdfb, 0);
951 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
952 static struct clk atmel_lcdfb0_pixclk = {
954 .dev = &atmel_lcdfb0_device.dev,
956 .get_rate = genclk_get_rate,
957 .set_rate = genclk_set_rate,
958 .set_parent = genclk_set_parent,
962 struct platform_device *__init
963 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
964 unsigned long fbmem_start, unsigned long fbmem_len)
966 struct platform_device *pdev;
967 struct atmel_lcdfb_info *info;
968 struct fb_monspecs *monspecs;
969 struct fb_videomode *modedb;
970 unsigned int modedb_size;
973 * Do a deep copy of the fb data, monspecs and modedb. Make
974 * sure all allocations are done before setting up the
977 monspecs = kmemdup(data->default_monspecs,
978 sizeof(struct fb_monspecs), GFP_KERNEL);
982 modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
983 modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
986 monspecs->modedb = modedb;
990 pdev = &atmel_lcdfb0_device;
991 select_peripheral(PC(19), PERIPH_A, 0); /* CC */
992 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
993 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
994 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
995 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
996 select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
997 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
998 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
999 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
1000 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
1001 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
1002 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
1003 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
1004 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
1005 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
1006 select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
1007 select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
1008 select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
1009 select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
1010 select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
1011 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
1012 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
1013 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
1014 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1015 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1016 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1017 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1018 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1019 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1020 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1021 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1023 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1024 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1028 goto err_invalid_id;
1032 pdev->resource[2].start = fbmem_start;
1033 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1034 pdev->resource[2].flags = IORESOURCE_MEM;
1037 info = pdev->dev.platform_data;
1038 memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1039 info->default_monspecs = monspecs;
1041 platform_device_register(pdev);
1051 /* --------------------------------------------------------------------
1053 * -------------------------------------------------------------------- */
1054 static struct clk gclk0 = {
1056 .mode = genclk_mode,
1057 .get_rate = genclk_get_rate,
1058 .set_rate = genclk_set_rate,
1059 .set_parent = genclk_set_parent,
1062 static struct clk gclk1 = {
1064 .mode = genclk_mode,
1065 .get_rate = genclk_get_rate,
1066 .set_rate = genclk_set_rate,
1067 .set_parent = genclk_set_parent,
1070 static struct clk gclk2 = {
1072 .mode = genclk_mode,
1073 .get_rate = genclk_get_rate,
1074 .set_rate = genclk_set_rate,
1075 .set_parent = genclk_set_parent,
1078 static struct clk gclk3 = {
1080 .mode = genclk_mode,
1081 .get_rate = genclk_get_rate,
1082 .set_rate = genclk_set_rate,
1083 .set_parent = genclk_set_parent,
1086 static struct clk gclk4 = {
1088 .mode = genclk_mode,
1089 .get_rate = genclk_get_rate,
1090 .set_rate = genclk_set_rate,
1091 .set_parent = genclk_set_parent,
1095 struct clk *at32_clock_list[] = {
1121 &atmel_usart0_usart,
1122 &atmel_usart1_usart,
1123 &atmel_usart2_usart,
1124 &atmel_usart3_usart,
1129 &atmel_spi0_spi_clk,
1130 &atmel_spi1_spi_clk,
1132 &atmel_lcdfb0_pixclk,
1139 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
1141 void __init at32_portmux_init(void)
1143 at32_init_pio(&pio0_device);
1144 at32_init_pio(&pio1_device);
1145 at32_init_pio(&pio2_device);
1146 at32_init_pio(&pio3_device);
1147 at32_init_pio(&pio4_device);
1150 void __init at32_clock_init(void)
1152 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
1155 if (pm_readl(MCCTRL) & PM_BIT(PLLSEL))
1160 if (pm_readl(PLL0) & PM_BIT(PLLOSC))
1161 pll0.parent = &osc1;
1162 if (pm_readl(PLL1) & PM_BIT(PLLOSC))
1163 pll1.parent = &osc1;
1165 genclk_init_parent(&gclk0);
1166 genclk_init_parent(&gclk1);
1167 genclk_init_parent(&gclk2);
1168 genclk_init_parent(&gclk3);
1169 genclk_init_parent(&gclk4);
1170 genclk_init_parent(&atmel_lcdfb0_pixclk);
1173 * Turn on all clocks that have at least one user already, and
1174 * turn off everything else. We only do this for module
1175 * clocks, and even though it isn't particularly pretty to
1176 * check the address of the mode function, it should do the
1179 for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
1180 struct clk *clk = at32_clock_list[i];
1182 if (clk->users == 0)
1185 if (clk->mode == &cpu_clk_mode)
1186 cpu_mask |= 1 << clk->index;
1187 else if (clk->mode == &hsb_clk_mode)
1188 hsb_mask |= 1 << clk->index;
1189 else if (clk->mode == &pba_clk_mode)
1190 pba_mask |= 1 << clk->index;
1191 else if (clk->mode == &pbb_clk_mode)
1192 pbb_mask |= 1 << clk->index;
1195 pm_writel(CPU_MASK, cpu_mask);
1196 pm_writel(HSB_MASK, hsb_mask);
1197 pm_writel(PBA_MASK, pba_mask);
1198 pm_writel(PBB_MASK, pbb_mask);