1 /* linux/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
3 * Copyright (c) 2006,2008,2009 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
7 * S3C24XX CPU Frequency scaling - IO timing for S3C2410/S3C2440/S3C2442
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/errno.h>
17 #include <linux/cpufreq.h>
21 #include <mach/regs-mem.h>
22 #include <mach/regs-clock.h>
24 #include <plat/cpu-freq-core.h>
26 #define print_ns(x) ((x) / 10), ((x) % 10)
29 * s3c2410_print_timing - print bank timing data for debug purposes
30 * @pfx: The prefix to put on the output
31 * @timings: The timing inforamtion to print.
33 static void s3c2410_print_timing(const char *pfx,
34 struct s3c_iotimings *timings)
36 struct s3c2410_iobank_timing *bt;
39 for (bank = 0; bank < MAX_BANKS; bank++) {
40 bt = timings->bank[bank].io_2410;
44 printk(KERN_DEBUG "%s %d: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, "
45 "Tcoh=%d.%d, Tcah=%d.%d\n", pfx, bank,
55 * bank_reg - convert bank number to pointer to the control register.
56 * @bank: The IO bank number.
58 static inline void __iomem *bank_reg(unsigned int bank)
60 return S3C2410_BANKCON0 + (bank << 2);
64 * bank_is_io - test whether bank is used for IO
65 * @bankcon: The bank control register.
67 * This is a simplistic test to see if any BANKCON[x] is not an IO
68 * bank. It currently does not take into account whether BWSCON has
69 * an illegal width-setting in it, or if the pin connected to nCS[x]
70 * is actually being handled as a chip-select.
72 static inline int bank_is_io(unsigned long bankcon)
74 return !(bankcon & S3C2410_BANKCON_SDRAM);
78 * to_div - convert cycle time to divisor
79 * @cyc: The cycle time, in 10ths of nanoseconds.
80 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
82 * Convert the given cycle time into the divisor to use to obtain it from
85 static inline unsigned int to_div(unsigned int cyc, unsigned int hclk_tns)
90 return DIV_ROUND_UP(cyc, hclk_tns);
94 * calc_0124 - calculate divisor control for divisors that do /0, /1. /2 and /4
95 * @cyc: The cycle time, in 10ths of nanoseconds.
96 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
97 * @v: Pointer to register to alter.
98 * @shift: The shift to get to the control bits.
100 * Calculate the divisor, and turn it into the correct control bits to
101 * set in the result, @v.
103 static unsigned int calc_0124(unsigned int cyc, unsigned long hclk_tns,
104 unsigned long *v, int shift)
106 unsigned int div = to_div(cyc, hclk_tns);
109 s3c_freq_iodbg("%s: cyc=%d, hclk=%lu, shift=%d => div %d\n",
110 __func__, cyc, hclk_tns, shift, div);
134 int calc_tacp(unsigned int cyc, unsigned long hclk, unsigned long *v)
136 /* Currently no support for Tacp calculations. */
141 * calc_tacc - calculate divisor control for tacc.
142 * @cyc: The cycle time, in 10ths of nanoseconds.
143 * @nwait_en: IS nWAIT enabled for this bank.
144 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
145 * @v: Pointer to register to alter.
147 * Calculate the divisor control for tACC, taking into account whether
148 * the bank has nWAIT enabled. The result is used to modify the value
151 static int calc_tacc(unsigned int cyc, int nwait_en,
152 unsigned long hclk_tns, unsigned long *v)
154 unsigned int div = to_div(cyc, hclk_tns);
157 s3c_freq_iodbg("%s: cyc=%u, nwait=%d, hclk=%lu => div=%u\n",
158 __func__, cyc, nwait_en, hclk_tns, div);
160 /* if nWait enabled on an bank, Tacc must be at-least 4 cycles. */
161 if (nwait_en && div < 4)
207 * s3c2410_calc_bank - calculate bank timing infromation
208 * @cfg: The configuration we need to calculate for.
209 * @bt: The bank timing information.
211 * Given the cycle timine for a bank @bt, calculate the new BANKCON
212 * setting for the @cfg timing. This updates the timing information
213 * ready for the cpu frequency change.
215 static int s3c2410_calc_bank(struct s3c_cpufreq_config *cfg,
216 struct s3c2410_iobank_timing *bt)
218 unsigned long hclk = cfg->freq.hclk_tns;
223 res &= (S3C2410_BANKCON_SDRAM | S3C2410_BANKCON_PMC16);
228 /* tacc: 1,2,3,4,6,7,10,14 (>4 for nwait) */
232 ret = calc_0124(bt->tacs, hclk, &res, S3C2410_BANKCON_Tacs_SHIFT);
233 ret |= calc_0124(bt->tcos, hclk, &res, S3C2410_BANKCON_Tcos_SHIFT);
234 ret |= calc_0124(bt->tcah, hclk, &res, S3C2410_BANKCON_Tcah_SHIFT);
235 ret |= calc_0124(bt->tcoh, hclk, &res, S3C2410_BANKCON_Tcoh_SHIFT);
240 ret |= calc_tacp(bt->tacp, hclk, &res);
241 ret |= calc_tacc(bt->tacc, bt->nwait_en, hclk, &res);
250 static unsigned int tacc_tab[] = {
262 * get_tacc - turn tACC value into cycle time
263 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
264 * @val: The bank timing register value, shifed down.
266 static unsigned int get_tacc(unsigned long hclk_tns,
270 return hclk_tns * tacc_tab[val];
274 * get_0124 - turn 0/1/2/4 divider into cycle time
275 * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
276 * @val: The bank timing register value, shifed down.
278 static unsigned int get_0124(unsigned long hclk_tns,
282 return hclk_tns * ((val == 3) ? 4 : val);
286 * s3c2410_iotiming_getbank - turn BANKCON into cycle time information
287 * @cfg: The frequency configuration
288 * @bt: The bank timing to fill in (uses cached BANKCON)
290 * Given the BANKCON setting in @bt and the current frequency settings
291 * in @cfg, update the cycle timing information.
293 void s3c2410_iotiming_getbank(struct s3c_cpufreq_config *cfg,
294 struct s3c2410_iobank_timing *bt)
296 unsigned long bankcon = bt->bankcon;
297 unsigned long hclk = cfg->freq.hclk_tns;
299 bt->tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT);
300 bt->tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT);
301 bt->tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT);
302 bt->tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT);
303 bt->tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT);
307 * s3c2410_iotiming_calc - Calculate bank timing for frequency change.
308 * @cfg: The frequency configuration
309 * @iot: The IO timing information to fill out.
311 * Calculate the new values for the banks in @iot based on the new
312 * frequency information in @cfg. This is then used by s3c2410_iotiming_set()
313 * to update the timing when necessary.
315 int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
316 struct s3c_iotimings *iot)
318 struct s3c2410_iobank_timing *bt;
319 unsigned long bankcon;
323 for (bank = 0; bank < MAX_BANKS; bank++) {
324 bankcon = __raw_readl(bank_reg(bank));
325 bt = iot->bank[bank].io_2410;
330 bt->bankcon = bankcon;
332 ret = s3c2410_calc_bank(cfg, bt);
334 printk(KERN_ERR "%s: cannot calculate bank %d io\n",
339 s3c_freq_iodbg("%s: bank %d: con=%08lx\n",
340 __func__, bank, bt->bankcon);
349 * s3c2410_iotiming_set - set the IO timings from the given setup.
350 * @cfg: The frequency configuration
351 * @iot: The IO timing information to use.
353 * Set all the currently used IO bank timing information generated
354 * by s3c2410_iotiming_calc() once the core has validated that all
355 * the new values are within permitted bounds.
357 void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
358 struct s3c_iotimings *iot)
360 struct s3c2410_iobank_timing *bt;
363 /* set the io timings from the specifier */
365 for (bank = 0; bank < MAX_BANKS; bank++) {
366 bt = iot->bank[bank].io_2410;
370 __raw_writel(bt->bankcon, bank_reg(bank));
375 * s3c2410_iotiming_get - Get the timing information from current registers.
376 * @cfg: The frequency configuration
377 * @timings: The IO timing information to fill out.
379 * Calculate the @timings timing information from the current frequency
380 * information in @cfg, and the new frequency configur
381 * through all the IO banks, reading the state and then updating @iot
384 * This is used at the moment on initialisation to get the current
385 * configuration so that boards do not have to carry their own setup
386 * if the timings are correct on initialisation.
389 int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
390 struct s3c_iotimings *timings)
392 struct s3c2410_iobank_timing *bt;
393 unsigned long bankcon;
394 unsigned long bwscon;
397 bwscon = __raw_readl(S3C2410_BWSCON);
399 /* look through all banks to see what is currently set. */
401 for (bank = 0; bank < MAX_BANKS; bank++) {
402 bankcon = __raw_readl(bank_reg(bank));
404 if (!bank_is_io(bankcon))
407 s3c_freq_iodbg("%s: bank %d: con %08lx\n",
408 __func__, bank, bankcon);
410 bt = kzalloc(sizeof(struct s3c2410_iobank_timing), GFP_KERNEL);
412 printk(KERN_ERR "%s: no memory for bank\n", __func__);
416 /* find out in nWait is enabled for bank. */
419 unsigned long tmp = S3C2410_BWSCON_GET(bwscon, bank);
420 if (tmp & S3C2410_BWSCON_WS)
424 timings->bank[bank].io_2410 = bt;
425 bt->bankcon = bankcon;
427 s3c2410_iotiming_getbank(cfg, bt);
430 s3c2410_print_timing("get", timings);