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   1 /* linux/arch/arm/plat-s3c24xx/dma.c
   2  *
   3  * Copyright (c) 2003-2005,2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 DMA core
   7  *
   8  * http://armlinux.simtec.co.uk/
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15
  16 #ifdef CONFIG_S3C2410_DMA_DEBUG
  17 #define DEBUG
  18 #endif
  19
  20 #include <linux/module.h>
  21 #include <linux/init.h>
  22 #include <linux/sched.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sysdev.h>
  26 #include <linux/slab.h>
  27 #include <linux/errno.h>
  28 #include <linux/delay.h>
  29 #include <linux/io.h>
  30
  31 #include <asm/system.h>
  32 #include <asm/irq.h>
  33 #include <mach/hardware.h>
  34 #include <mach/dma.h>
  35
  36 #include <mach/map.h>
  37
  38 #include <plat/dma.h>
  39
  40 /* io map for dma */
  41 static void __iomem *dma_base;
  42 static struct kmem_cache *dma_kmem;
  43
  44 static int dma_channels;
  45
  46 static struct s3c24xx_dma_selection dma_sel;
  47
  48 /* dma channel state information */
  49 struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
  50
  51 /* debugging functions */
  52
  53 #define BUF_MAGIC (0xcafebabe)
  54
  55 #define dmawarn(fmt...) printk(KERN_DEBUG fmt)
  56
  57 #define dma_regaddr(chan, reg) ((chan)->regs + (reg))
  58
  59 #if 1
  60 #define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
  61 #else
  62 static inline void
  63 dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val)
  64 {
  65         pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg);
  66         writel(val, dma_regaddr(chan, reg));
  67 }
  68 #endif
  69
  70 #define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
  71
  72 /* captured register state for debug */
  73
  74 struct s3c2410_dma_regstate {
  75         unsigned long         dcsrc;
  76         unsigned long         disrc;
  77         unsigned long         dstat;
  78         unsigned long         dcon;
  79         unsigned long         dmsktrig;
  80 };
  81
  82 #ifdef CONFIG_S3C2410_DMA_DEBUG
  83
  84 /* dmadbg_showregs
  85  *
  86  * simple debug routine to print the current state of the dma registers
  87 */
  88
  89 static void
  90 dmadbg_capture(struct s3c2410_dma_chan *chan, struct s3c2410_dma_regstate *regs)
  91 {
  92         regs->dcsrc    = dma_rdreg(chan, S3C2410_DMA_DCSRC);
  93         regs->disrc    = dma_rdreg(chan, S3C2410_DMA_DISRC);
  94         regs->dstat    = dma_rdreg(chan, S3C2410_DMA_DSTAT);
  95         regs->dcon     = dma_rdreg(chan, S3C2410_DMA_DCON);
  96         regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
  97 }
  98
  99 static void
 100 dmadbg_dumpregs(const char *fname, int line, struct s3c2410_dma_chan *chan,
 101                  struct s3c2410_dma_regstate *regs)
 102 {
 103         printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n",
 104                chan->number, fname, line,
 105                regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig,
 106                regs->dcon);
 107 }
 108
 109 static void
 110 dmadbg_showchan(const char *fname, int line, struct s3c2410_dma_chan *chan)
 111 {
 112         struct s3c2410_dma_regstate state;
 113
 114         dmadbg_capture(chan, &state);
 115
 116         printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n",
 117                chan->number, fname, line, chan->load_state,
 118                chan->curr, chan->next, chan->end);
 119
 120         dmadbg_dumpregs(fname, line, chan, &state);
 121 }
 122
 123 static void
 124 dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan)
 125 {
 126         struct s3c2410_dma_regstate state;
 127
 128         dmadbg_capture(chan, &state);
 129         dmadbg_dumpregs(fname, line, chan, &state);
 130 }
 131
 132 #define dbg_showregs(chan) dmadbg_showregs(__func__, __LINE__, (chan))
 133 #define dbg_showchan(chan) dmadbg_showchan(__func__, __LINE__, (chan))
 134 #else
 135 #define dbg_showregs(chan) do { } while(0)
 136 #define dbg_showchan(chan) do { } while(0)
 137 #endif /* CONFIG_S3C2410_DMA_DEBUG */
 138
 139 static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX];
 140
 141 /* lookup_dma_channel
 142  *
 143  * change the dma channel number given into a real dma channel id
 144 */
 145
 146 static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel)
 147 {
 148         if (channel & DMACH_LOW_LEVEL)
 149                 return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
 150         else
 151                 return dma_chan_map[channel];
 152 }
 153
 154 /* s3c2410_dma_stats_timeout
 155  *
 156  * Update DMA stats from timeout info
 157 */
 158
 159 static void
 160 s3c2410_dma_stats_timeout(struct s3c2410_dma_stats *stats, int val)
 161 {
 162         if (stats == NULL)
 163                 return;
 164
 165         if (val > stats->timeout_longest)
 166                 stats->timeout_longest = val;
 167         if (val < stats->timeout_shortest)
 168                 stats->timeout_shortest = val;
 169
 170         stats->timeout_avg += val;
 171 }
 172
 173 /* s3c2410_dma_waitforload
 174  *
 175  * wait for the DMA engine to load a buffer, and update the state accordingly
 176 */
 177
 178 static int
 179 s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
 180 {
 181         int timeout = chan->load_timeout;
 182         int took;
 183
 184         if (chan->load_state != S3C2410_DMALOAD_1LOADED) {
 185                 printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line);
 186                 return 0;
 187         }
 188
 189         if (chan->stats != NULL)
 190                 chan->stats->loads++;
 191
 192         while (--timeout > 0) {
 193                 if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) {
 194                         took = chan->load_timeout - timeout;
 195
 196                         s3c2410_dma_stats_timeout(chan->stats, took);
 197
 198                         switch (chan->load_state) {
 199                         case S3C2410_DMALOAD_1LOADED:
 200                                 chan->load_state = S3C2410_DMALOAD_1RUNNING;
 201                                 break;
 202
 203                         default:
 204                                 printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state);
 205                         }
 206
 207                         return 1;
 208                 }
 209         }
 210
 211         if (chan->stats != NULL) {
 212                 chan->stats->timeout_failed++;
 213         }
 214
 215         return 0;
 216 }
 217
 218
 219
 220 /* s3c2410_dma_loadbuffer
 221  *
 222  * load a buffer, and update the channel state
 223 */
 224
 225 static inline int
 226 s3c2410_dma_loadbuffer(struct s3c2410_dma_chan *chan,
 227                        struct s3c2410_dma_buf *buf)
 228 {
 229         unsigned long reload;
 230
 231         pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",
 232                  buf, (unsigned long)buf->data, buf->size);
 233
 234         if (buf == NULL) {
 235                 dmawarn("buffer is NULL\n");
 236                 return -EINVAL;
 237         }
 238
 239         /* check the state of the channel before we do anything */
 240
 241         if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
 242                 dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
 243         }
 244
 245         if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) {
 246                 dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
 247         }
 248
 249         /* it would seem sensible if we are the last buffer to not bother
 250          * with the auto-reload bit, so that the DMA engine will not try
 251          * and load another transfer after this one has finished...
 252          */
 253         if (chan->load_state == S3C2410_DMALOAD_NONE) {
 254                 pr_debug("load_state is none, checking for noreload (next=%p)\n",
 255                          buf->next);
 256                 reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0;
 257         } else {
 258                 //pr_debug("load_state is %d => autoreload\n", chan->load_state);
 259                 reload = S3C2410_DCON_AUTORELOAD;
 260         }
 261
 262         if ((buf->data & 0xf0000000) != 0x30000000) {
 263                 dmawarn("dmaload: buffer is %p\n", (void *)buf->data);
 264         }
 265
 266         writel(buf->data, chan->addr_reg);
 267
 268         dma_wrreg(chan, S3C2410_DMA_DCON,
 269                   chan->dcon | reload | (buf->size/chan->xfer_unit));
 270
 271         chan->next = buf->next;
 272
 273         /* update the state of the channel */
 274
 275         switch (chan->load_state) {
 276         case S3C2410_DMALOAD_NONE:
 277                 chan->load_state = S3C2410_DMALOAD_1LOADED;
 278                 break;
 279
 280         case S3C2410_DMALOAD_1RUNNING:
 281                 chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING;
 282                 break;
 283
 284         default:
 285                 dmawarn("dmaload: unknown state %d in loadbuffer\n",
 286                         chan->load_state);
 287                 break;
 288         }
 289
 290         return 0;
 291 }
 292
 293 /* s3c2410_dma_call_op
 294  *
 295  * small routine to call the op routine with the given op if it has been
 296  * registered
 297 */
 298
 299 static void
 300 s3c2410_dma_call_op(struct s3c2410_dma_chan *chan, enum s3c2410_chan_op op)
 301 {
 302         if (chan->op_fn != NULL) {
 303                 (chan->op_fn)(chan, op);
 304         }
 305 }
 306
 307 /* s3c2410_dma_buffdone
 308  *
 309  * small wrapper to check if callback routine needs to be called, and
 310  * if so, call it
 311 */
 312
 313 static inline void
 314 s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf,
 315                      enum s3c2410_dma_buffresult result)
 316 {
 317 #if 0
 318         pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n",
 319                  chan->callback_fn, buf, buf->id, buf->size, result);
 320 #endif
 321
 322         if (chan->callback_fn != NULL) {
 323                 (chan->callback_fn)(chan, buf->id, buf->size, result);
 324         }
 325 }
 326
 327 /* s3c2410_dma_start
 328  *
 329  * start a dma channel going
 330 */
 331
 332 static int s3c2410_dma_start(struct s3c2410_dma_chan *chan)
 333 {
 334         unsigned long tmp;
 335         unsigned long flags;
 336
 337         pr_debug("s3c2410_start_dma: channel=%d\n", chan->number);
 338
 339         local_irq_save(flags);
 340
 341         if (chan->state == S3C2410_DMA_RUNNING) {
 342                 pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state);
 343                 local_irq_restore(flags);
 344                 return 0;
 345         }
 346
 347         chan->state = S3C2410_DMA_RUNNING;
 348
 349         /* check wether there is anything to load, and if not, see
 350          * if we can find anything to load
 351          */
 352
 353         if (chan->load_state == S3C2410_DMALOAD_NONE) {
 354                 if (chan->next == NULL) {
 355                         printk(KERN_ERR "dma%d: channel has nothing loaded\n",
 356                                chan->number);
 357                         chan->state = S3C2410_DMA_IDLE;
 358                         local_irq_restore(flags);
 359                         return -EINVAL;
 360                 }
 361
 362                 s3c2410_dma_loadbuffer(chan, chan->next);
 363         }
 364
 365         dbg_showchan(chan);
 366
 367         /* enable the channel */
 368
 369         if (!chan->irq_enabled) {
 370                 enable_irq(chan->irq);
 371                 chan->irq_enabled = 1;
 372         }
 373
 374         /* start the channel going */
 375
 376         tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
 377         tmp &= ~S3C2410_DMASKTRIG_STOP;
 378         tmp |= S3C2410_DMASKTRIG_ON;
 379         dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
 380
 381         pr_debug("dma%d: %08lx to DMASKTRIG\n", chan->number, tmp);
 382
 383 #if 0
 384         /* the dma buffer loads should take care of clearing the AUTO
 385          * reloading feature */
 386         tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
 387         tmp &= ~S3C2410_DCON_NORELOAD;
 388         dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
 389 #endif
 390
 391         s3c2410_dma_call_op(chan, S3C2410_DMAOP_START);
 392
 393         dbg_showchan(chan);
 394
 395         /* if we've only loaded one buffer onto the channel, then chec
 396          * to see if we have another, and if so, try and load it so when
 397          * the first buffer is finished, the new one will be loaded onto
 398          * the channel */
 399
 400         if (chan->next != NULL) {
 401                 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
 402
 403                         if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
 404                                 pr_debug("%s: buff not yet loaded, no more todo\n",
 405                                          __func__);
 406                         } else {
 407                                 chan->load_state = S3C2410_DMALOAD_1RUNNING;
 408                                 s3c2410_dma_loadbuffer(chan, chan->next);
 409                         }
 410
 411                 } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
 412                         s3c2410_dma_loadbuffer(chan, chan->next);
 413                 }
 414         }
 415
 416
 417         local_irq_restore(flags);
 418
 419         return 0;
 420 }
 421
 422 /* s3c2410_dma_canload
 423  *
 424  * work out if we can queue another buffer into the DMA engine
 425 */
 426
 427 static int
 428 s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
 429 {
 430         if (chan->load_state == S3C2410_DMALOAD_NONE ||
 431             chan->load_state == S3C2410_DMALOAD_1RUNNING)
 432                 return 1;
 433
 434         return 0;
 435 }
 436
 437 /* s3c2410_dma_enqueue
 438  *
 439  * queue an given buffer for dma transfer.
 440  *
 441  * id         the device driver's id information for this buffer
 442  * data       the physical address of the buffer data
 443  * size       the size of the buffer in bytes
 444  *
 445  * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
 446  * is checked, and if set, the channel is started. If this flag isn't set,
 447  * then an error will be returned.
 448  *
 449  * It is possible to queue more than one DMA buffer onto a channel at
 450  * once, and the code will deal with the re-loading of the next buffer
 451  * when necessary.
 452 */
 453
 454 int s3c2410_dma_enqueue(unsigned int channel, void *id,
 455                         dma_addr_t data, int size)
 456 {
 457         struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
 458         struct s3c2410_dma_buf *buf;
 459         unsigned long flags;
 460
 461         if (chan == NULL)
 462                 return -EINVAL;
 463
 464         pr_debug("%s: id=%p, data=%08x, size=%d\n",
 465                  __func__, id, (unsigned int)data, size);
 466
 467         buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC);
 468         if (buf == NULL) {
 469                 pr_debug("%s: out of memory (%ld alloc)\n",
 470                          __func__, (long)sizeof(*buf));
 471                 return -ENOMEM;
 472         }
 473
 474         //pr_debug("%s: new buffer %p\n", __func__, buf);
 475         //dbg_showchan(chan);
 476
 477         buf->next  = NULL;
 478         buf->data  = buf->ptr = data;
 479         buf->size  = size;
 480         buf->id    = id;
 481         buf->magic = BUF_MAGIC;
 482
 483         local_irq_save(flags);
 484
 485         if (chan->curr == NULL) {
 486                 /* we've got nothing loaded... */
 487                 pr_debug("%s: buffer %p queued onto empty channel\n",
 488                          __func__, buf);
 489
 490                 chan->curr = buf;
 491                 chan->end  = buf;
 492                 chan->next = NULL;
 493         } else {
 494                 pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
 495                          chan->number, __func__, buf);
 496
 497                 if (chan->end == NULL)
 498                         pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
 499                                  chan->number, __func__, chan);
 500
 501                 chan->end->next = buf;
 502                 chan->end = buf;
 503         }
 504
 505         /* if necessary, update the next buffer field */
 506         if (chan->next == NULL)
 507                 chan->next = buf;
 508
 509         /* check to see if we can load a buffer */
 510         if (chan->state == S3C2410_DMA_RUNNING) {
 511                 if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) {
 512                         if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
 513                                 printk(KERN_ERR "dma%d: loadbuffer:"
 514                                        "timeout loading buffer\n",
 515                                        chan->number);
 516                                 dbg_showchan(chan);
 517                                 local_irq_restore(flags);
 518                                 return -EINVAL;
 519                         }
 520                 }
 521
 522                 while (s3c2410_dma_canload(chan) && chan->next != NULL) {
 523                         s3c2410_dma_loadbuffer(chan, chan->next);
 524                 }
 525         } else if (chan->state == S3C2410_DMA_IDLE) {
 526                 if (chan->flags & S3C2410_DMAF_AUTOSTART) {
 527                         s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
 528                                          S3C2410_DMAOP_START);
 529                 }
 530         }
 531
 532         local_irq_restore(flags);
 533         return 0;
 534 }
 535
 536 EXPORT_SYMBOL(s3c2410_dma_enqueue);
 537
 538 static inline void
 539 s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf)
 540 {
 541         int magicok = (buf->magic == BUF_MAGIC);
 542
 543         buf->magic = -1;
 544
 545         if (magicok) {
 546                 kmem_cache_free(dma_kmem, buf);
 547         } else {
 548                 printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf);
 549         }
 550 }
 551
 552 /* s3c2410_dma_lastxfer
 553  *
 554  * called when the system is out of buffers, to ensure that the channel
 555  * is prepared for shutdown.
 556 */
 557
 558 static inline void
 559 s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan)
 560 {
 561 #if 0
 562         pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n",
 563                  chan->number, chan->load_state);
 564 #endif
 565
 566         switch (chan->load_state) {
 567         case S3C2410_DMALOAD_NONE:
 568                 break;
 569
 570         case S3C2410_DMALOAD_1LOADED:
 571                 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
 572                                 /* flag error? */
 573                         printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
 574                                chan->number, __func__);
 575                         return;
 576                 }
 577                 break;
 578
 579         case S3C2410_DMALOAD_1LOADED_1RUNNING:
 580                 /* I belive in this case we do not have anything to do
 581                  * until the next buffer comes along, and we turn off the
 582                  * reload */
 583                 return;
 584
 585         default:
 586                 pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n",
 587                          chan->number, chan->load_state);
 588                 return;
 589
 590         }
 591
 592         /* hopefully this'll shut the damned thing up after the transfer... */
 593         dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD);
 594 }
 595
 596
 597 #define dmadbg2(x...)
 598
 599 static irqreturn_t
 600 s3c2410_dma_irq(int irq, void *devpw)
 601 {
 602         struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw;
 603         struct s3c2410_dma_buf  *buf;
 604
 605         buf = chan->curr;
 606
 607         dbg_showchan(chan);
 608
 609         /* modify the channel state */
 610
 611         switch (chan->load_state) {
 612         case S3C2410_DMALOAD_1RUNNING:
 613                 /* TODO - if we are running only one buffer, we probably
 614                  * want to reload here, and then worry about the buffer
 615                  * callback */
 616
 617                 chan->load_state = S3C2410_DMALOAD_NONE;
 618                 break;
 619
 620         case S3C2410_DMALOAD_1LOADED:
 621                 /* iirc, we should go back to NONE loaded here, we
 622                  * had a buffer, and it was never verified as being
 623                  * loaded.
 624                  */
 625
 626                 chan->load_state = S3C2410_DMALOAD_NONE;
 627                 break;
 628
 629         case S3C2410_DMALOAD_1LOADED_1RUNNING:
 630                 /* we'll worry about checking to see if another buffer is
 631                  * ready after we've called back the owner. This should
 632                  * ensure we do not wait around too long for the DMA
 633                  * engine to start the next transfer
 634                  */
 635
 636                 chan->load_state = S3C2410_DMALOAD_1LOADED;
 637                 break;
 638
 639         case S3C2410_DMALOAD_NONE:
 640                 printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n",
 641                        chan->number);
 642                 break;
 643
 644         default:
 645                 printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n",
 646                        chan->number, chan->load_state);
 647                 break;
 648         }
 649
 650         if (buf != NULL) {
 651                 /* update the chain to make sure that if we load any more
 652                  * buffers when we call the callback function, things should
 653                  * work properly */
 654
 655                 chan->curr = buf->next;
 656                 buf->next  = NULL;
 657
 658                 if (buf->magic != BUF_MAGIC) {
 659                         printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n",
 660                                chan->number, __func__, buf);
 661                         return IRQ_HANDLED;
 662                 }
 663
 664                 s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK);
 665
 666                 /* free resouces */
 667                 s3c2410_dma_freebuf(buf);
 668         } else {
 669         }
 670
 671         /* only reload if the channel is still running... our buffer done
 672          * routine may have altered the state by requesting the dma channel
 673          * to stop or shutdown... */
 674
 675         /* todo: check that when the channel is shut-down from inside this
 676          * function, we cope with unsetting reload, etc */
 677
 678         if (chan->next != NULL && chan->state != S3C2410_DMA_IDLE) {
 679                 unsigned long flags;
 680
 681                 switch (chan->load_state) {
 682                 case S3C2410_DMALOAD_1RUNNING:
 683                         /* don't need to do anything for this state */
 684                         break;
 685
 686                 case S3C2410_DMALOAD_NONE:
 687                         /* can load buffer immediately */
 688                         break;
 689
 690                 case S3C2410_DMALOAD_1LOADED:
 691                         if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
 692                                 /* flag error? */
 693                                 printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
 694                                        chan->number, __func__);
 695                                 return IRQ_HANDLED;
 696                         }
 697
 698                         break;
 699
 700                 case S3C2410_DMALOAD_1LOADED_1RUNNING:
 701                         goto no_load;
 702
 703                 default:
 704                         printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n",
 705                                chan->number, chan->load_state);
 706                         return IRQ_HANDLED;
 707                 }
 708
 709                 local_irq_save(flags);
 710                 s3c2410_dma_loadbuffer(chan, chan->next);
 711                 local_irq_restore(flags);
 712         } else {
 713                 s3c2410_dma_lastxfer(chan);
 714
 715                 /* see if we can stop this channel.. */
 716                 if (chan->load_state == S3C2410_DMALOAD_NONE) {
 717                         pr_debug("dma%d: end of transfer, stopping channel (%ld)\n",
 718                                  chan->number, jiffies);
 719                         s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
 720                                          S3C2410_DMAOP_STOP);
 721                 }
 722         }
 723
 724  no_load:
 725         return IRQ_HANDLED;
 726 }
 727
 728 static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel);
 729
 730 /* s3c2410_request_dma
 731  *
 732  * get control of an dma channel
 733 */
 734
 735 int s3c2410_dma_request(unsigned int channel,
 736                         struct s3c2410_dma_client *client,
 737                         void *dev)
 738 {
 739         struct s3c2410_dma_chan *chan;
 740         unsigned long flags;
 741         int err;
 742
 743         pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
 744                  channel, client->name, dev);
 745
 746         local_irq_save(flags);
 747
 748         chan = s3c2410_dma_map_channel(channel);
 749         if (chan == NULL) {
 750                 local_irq_restore(flags);
 751                 return -EBUSY;
 752         }
 753
 754         dbg_showchan(chan);
 755
 756         chan->client = client;
 757         chan->in_use = 1;
 758
 759         if (!chan->irq_claimed) {
 760                 pr_debug("dma%d: %s : requesting irq %d\n",
 761                          channel, __func__, chan->irq);
 762
 763                 chan->irq_claimed = 1;
 764                 local_irq_restore(flags);
 765
 766                 err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED,
 767                                   client->name, (void *)chan);
 768
 769                 local_irq_save(flags);
 770
 771                 if (err) {
 772                         chan->in_use = 0;
 773                         chan->irq_claimed = 0;
 774                         local_irq_restore(flags);
 775
 776                         printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n",
 777                                client->name, chan->irq, chan->number);
 778                         return err;
 779                 }
 780
 781                 chan->irq_enabled = 1;
 782         }
 783
 784         local_irq_restore(flags);
 785
 786         /* need to setup */
 787
 788         pr_debug("%s: channel initialised, %p\n", __func__, chan);
 789
 790         return chan->number | DMACH_LOW_LEVEL;
 791 }
 792
 793 EXPORT_SYMBOL(s3c2410_dma_request);
 794
 795 /* s3c2410_dma_free
 796  *
 797  * release the given channel back to the system, will stop and flush
 798  * any outstanding transfers, and ensure the channel is ready for the
 799  * next claimant.
 800  *
 801  * Note, although a warning is currently printed if the freeing client
 802  * info is not the same as the registrant's client info, the free is still
 803  * allowed to go through.
 804 */
 805
 806 int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
 807 {
 808         struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
 809         unsigned long flags;
 810
 811         if (chan == NULL)
 812                 return -EINVAL;
 813
 814         local_irq_save(flags);
 815
 816         if (chan->client != client) {
 817                 printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
 818                        channel, chan->client, client);
 819         }
 820
 821         /* sort out stopping and freeing the channel */
 822
 823         if (chan->state != S3C2410_DMA_IDLE) {
 824                 pr_debug("%s: need to stop dma channel %p\n",
 825                        __func__, chan);
 826
 827                 /* possibly flush the channel */
 828                 s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP);
 829         }
 830
 831         chan->client = NULL;
 832         chan->in_use = 0;
 833
 834         if (chan->irq_claimed)
 835                 free_irq(chan->irq, (void *)chan);
 836
 837         chan->irq_claimed = 0;
 838
 839         if (!(channel & DMACH_LOW_LEVEL))
 840                 dma_chan_map[channel] = NULL;
 841
 842         local_irq_restore(flags);
 843
 844         return 0;
 845 }
 846
 847 EXPORT_SYMBOL(s3c2410_dma_free);
 848
 849 static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan)
 850 {
 851         unsigned long flags;
 852         unsigned long tmp;
 853
 854         pr_debug("%s:\n", __func__);
 855
 856         dbg_showchan(chan);
 857
 858         local_irq_save(flags);
 859
 860         s3c2410_dma_call_op(chan,  S3C2410_DMAOP_STOP);
 861
 862         tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
 863         tmp |= S3C2410_DMASKTRIG_STOP;
 864         //tmp &= ~S3C2410_DMASKTRIG_ON;
 865         dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
 866
 867 #if 0
 868         /* should also clear interrupts, according to WinCE BSP */
 869         tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
 870         tmp |= S3C2410_DCON_NORELOAD;
 871         dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
 872 #endif
 873
 874         /* should stop do this, or should we wait for flush? */
 875         chan->state      = S3C2410_DMA_IDLE;
 876         chan->load_state = S3C2410_DMALOAD_NONE;
 877
 878         local_irq_restore(flags);
 879
 880         return 0;
 881 }
 882
 883 static void s3c2410_dma_waitforstop(struct s3c2410_dma_chan *chan)
 884 {
 885         unsigned long tmp;
 886         unsigned int timeout = 0x10000;
 887
 888         while (timeout-- > 0) {
 889                 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
 890
 891                 if (!(tmp & S3C2410_DMASKTRIG_ON))
 892                         return;
 893         }
 894
 895         pr_debug("dma%d: failed to stop?\n", chan->number);
 896 }
 897
 898
 899 /* s3c2410_dma_flush
 900  *
 901  * stop the channel, and remove all current and pending transfers
 902 */
 903
 904 static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan)
 905 {
 906         struct s3c2410_dma_buf *buf, *next;
 907         unsigned long flags;
 908
 909         pr_debug("%s: chan %p (%d)\n", __func__, chan, chan->number);
 910
 911         dbg_showchan(chan);
 912
 913         local_irq_save(flags);
 914
 915         if (chan->state != S3C2410_DMA_IDLE) {
 916                 pr_debug("%s: stopping channel...\n", __func__ );
 917                 s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
 918         }
 919
 920         buf = chan->curr;
 921         if (buf == NULL)
 922                 buf = chan->next;
 923
 924         chan->curr = chan->next = chan->end = NULL;
 925
 926         if (buf != NULL) {
 927                 for ( ; buf != NULL; buf = next) {
 928                         next = buf->next;
 929
 930                         pr_debug("%s: free buffer %p, next %p\n",
 931                                __func__, buf, buf->next);
 932
 933                         s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT);
 934                         s3c2410_dma_freebuf(buf);
 935                 }
 936         }
 937
 938         dbg_showregs(chan);
 939
 940         s3c2410_dma_waitforstop(chan);
 941
 942 #if 0
 943         /* should also clear interrupts, according to WinCE BSP */
 944         {
 945                 unsigned long tmp;
 946
 947                 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
 948                 tmp |= S3C2410_DCON_NORELOAD;
 949                 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
 950         }
 951 #endif
 952
 953         dbg_showregs(chan);
 954
 955         local_irq_restore(flags);
 956
 957         return 0;
 958 }
 959
 960 static int s3c2410_dma_started(struct s3c2410_dma_chan *chan)
 961 {
 962         unsigned long flags;
 963
 964         local_irq_save(flags);
 965
 966         dbg_showchan(chan);
 967
 968         /* if we've only loaded one buffer onto the channel, then chec
 969          * to see if we have another, and if so, try and load it so when
 970          * the first buffer is finished, the new one will be loaded onto
 971          * the channel */
 972
 973         if (chan->next != NULL) {
 974                 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
 975
 976                         if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
 977                                 pr_debug("%s: buff not yet loaded, no more todo\n",
 978                                          __func__);
 979                         } else {
 980                                 chan->load_state = S3C2410_DMALOAD_1RUNNING;
 981                                 s3c2410_dma_loadbuffer(chan, chan->next);
 982                         }
 983
 984                 } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
 985                         s3c2410_dma_loadbuffer(chan, chan->next);
 986                 }
 987         }
 988
 989
 990         local_irq_restore(flags);
 991
 992         return 0;
 993
 994 }
 995
 996 int
 997 s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
 998 {
 999         struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1000
1001         if (chan == NULL)
1002                 return -EINVAL;
1003
1004         switch (op) {
1005         case S3C2410_DMAOP_START:
1006                 return s3c2410_dma_start(chan);
1007
1008         case S3C2410_DMAOP_STOP:
1009                 return s3c2410_dma_dostop(chan);
1010
1011         case S3C2410_DMAOP_PAUSE:
1012         case S3C2410_DMAOP_RESUME:
1013                 return -ENOENT;
1014
1015         case S3C2410_DMAOP_FLUSH:
1016                 return s3c2410_dma_flush(chan);
1017
1018         case S3C2410_DMAOP_STARTED:
1019                 return s3c2410_dma_started(chan);
1020
1021         case S3C2410_DMAOP_TIMEOUT:
1022                 return 0;
1023
1024         }
1025
1026         return -ENOENT;      /* unknown, don't bother */
1027 }
1028
1029 EXPORT_SYMBOL(s3c2410_dma_ctrl);
1030
1031 /* DMA configuration for each channel
1032  *
1033  * DISRCC -> source of the DMA (AHB,APB)
1034  * DISRC  -> source address of the DMA
1035  * DIDSTC -> destination of the DMA (AHB,APD)
1036  * DIDST  -> destination address of the DMA
1037 */
1038
1039 /* s3c2410_dma_config
1040  *
1041  * xfersize:     size of unit in bytes (1,2,4)
1042  * dcon:         base value of the DCONx register
1043 */
1044
1045 int s3c2410_dma_config(unsigned int channel,
1046                        int xferunit,
1047                        int dcon)
1048 {
1049         struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1050
1051         pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
1052                  __func__, channel, xferunit, dcon);
1053
1054         if (chan == NULL)
1055                 return -EINVAL;
1056
1057         pr_debug("%s: Initial dcon is %08x\n", __func__, dcon);
1058
1059         dcon |= chan->dcon & dma_sel.dcon_mask;
1060
1061         pr_debug("%s: New dcon is %08x\n", __func__, dcon);
1062
1063         switch (xferunit) {
1064         case 1:
1065                 dcon |= S3C2410_DCON_BYTE;
1066                 break;
1067
1068         case 2:
1069                 dcon |= S3C2410_DCON_HALFWORD;
1070                 break;
1071
1072         case 4:
1073                 dcon |= S3C2410_DCON_WORD;
1074                 break;
1075
1076         default:
1077                 pr_debug("%s: bad transfer size %d\n", __func__, xferunit);
1078                 return -EINVAL;
1079         }
1080
1081         dcon |= S3C2410_DCON_HWTRIG;
1082         dcon |= S3C2410_DCON_INTREQ;
1083
1084         pr_debug("%s: dcon now %08x\n", __func__, dcon);
1085
1086         chan->dcon = dcon;
1087         chan->xfer_unit = xferunit;
1088
1089         return 0;
1090 }
1091
1092 EXPORT_SYMBOL(s3c2410_dma_config);
1093
1094 int s3c2410_dma_setflags(unsigned int channel, unsigned int flags)
1095 {
1096         struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1097
1098         if (chan == NULL)
1099                 return -EINVAL;
1100
1101         pr_debug("%s: chan=%p, flags=%08x\n", __func__, chan, flags);
1102
1103         chan->flags = flags;
1104
1105         return 0;
1106 }
1107
1108 EXPORT_SYMBOL(s3c2410_dma_setflags);
1109
1110
1111 /* do we need to protect the settings of the fields from
1112  * irq?
1113 */
1114
1115 int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
1116 {
1117         struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1118
1119         if (chan == NULL)
1120                 return -EINVAL;
1121
1122         pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
1123
1124         chan->op_fn = rtn;
1125
1126         return 0;
1127 }
1128
1129 EXPORT_SYMBOL(s3c2410_dma_set_opfn);
1130
1131 int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
1132 {
1133         struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1134
1135         if (chan == NULL)
1136                 return -EINVAL;
1137
1138         pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
1139
1140         chan->callback_fn = rtn;
1141
1142         return 0;
1143 }
1144
1145 EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
1146
1147 /* s3c2410_dma_devconfig
1148  *
1149  * configure the dma source/destination hardware type and address
1150  *
1151  * source:    S3C2410_DMASRC_HW: source is hardware
1152  *            S3C2410_DMASRC_MEM: source is memory
1153  *
1154  * hwcfg:     the value for xxxSTCn register,
1155  *            bit 0: 0=increment pointer, 1=leave pointer
1156  *            bit 1: 0=source is AHB, 1=source is APB
1157  *
1158  * devaddr:   physical address of the source
1159 */
1160
1161 int s3c2410_dma_devconfig(int channel,
1162                           enum s3c2410_dmasrc source,
1163                           int hwcfg,
1164                           unsigned long devaddr)
1165 {
1166         struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1167
1168         if (chan == NULL)
1169                 return -EINVAL;
1170
1171         pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n",
1172                  __func__, (int)source, hwcfg, devaddr);
1173
1174         chan->source = source;
1175         chan->dev_addr = devaddr;
1176         chan->hw_cfg = hwcfg;
1177
1178         switch (source) {
1179         case S3C2410_DMASRC_HW:
1180                 /* source is hardware */
1181                 pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n",
1182                          __func__, devaddr, hwcfg);
1183                 dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3);
1184                 dma_wrreg(chan, S3C2410_DMA_DISRC,  devaddr);
1185                 dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0));
1186
1187                 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST);
1188                 break;
1189
1190         case S3C2410_DMASRC_MEM:
1191                 /* source is memory */
1192                 pr_debug("%s: mem source, devaddr=%08lx, hwcfg=%d\n",
1193                          __func__, devaddr, hwcfg);
1194                 dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0));
1195                 dma_wrreg(chan, S3C2410_DMA_DIDST,  devaddr);
1196                 dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3);
1197
1198                 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC);
1199                 break;
1200
1201         default:
1202                 printk(KERN_ERR "dma%d: invalid source type (%d)\n",
1203                        channel, source);
1204
1205                 return -EINVAL;
1206         }
1207
1208         if (dma_sel.direction != NULL)
1209                 (dma_sel.direction)(chan, chan->map, source);
1210
1211         return 0;
1212 }
1213
1214 EXPORT_SYMBOL(s3c2410_dma_devconfig);
1215
1216 /* s3c2410_dma_getposition
1217  *
1218  * returns the current transfer points for the dma source and destination
1219 */
1220
1221 int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *dst)
1222 {
1223         struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1224
1225         if (chan == NULL)
1226                 return -EINVAL;
1227
1228         if (src != NULL)
1229                 *src = dma_rdreg(chan, S3C2410_DMA_DCSRC);
1230
1231         if (dst != NULL)
1232                 *dst = dma_rdreg(chan, S3C2410_DMA_DCDST);
1233
1234         return 0;
1235 }
1236
1237 EXPORT_SYMBOL(s3c2410_dma_getposition);
1238
1239 static struct s3c2410_dma_chan *to_dma_chan(struct sys_device *dev)
1240 {
1241         return container_of(dev, struct s3c2410_dma_chan, dev);
1242 }
1243
1244 /* system device class */
1245
1246 #ifdef CONFIG_PM
1247
1248 static int s3c2410_dma_suspend(struct sys_device *dev, pm_message_t state)
1249 {
1250         struct s3c2410_dma_chan *cp = to_dma_chan(dev);
1251
1252         printk(KERN_DEBUG "suspending dma channel %d\n", cp->number);
1253
1254         if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) {
1255                 /* the dma channel is still working, which is probably
1256                  * a bad thing to do over suspend/resume. We stop the
1257                  * channel and assume that the client is either going to
1258                  * retry after resume, or that it is broken.
1259                  */
1260
1261                 printk(KERN_INFO "dma: stopping channel %d due to suspend\n",
1262                        cp->number);
1263
1264                 s3c2410_dma_dostop(cp);
1265         }
1266
1267         return 0;
1268 }
1269
1270 static int s3c2410_dma_resume(struct sys_device *dev)
1271 {
1272         struct s3c2410_dma_chan *cp = to_dma_chan(dev);
1273         unsigned int no = cp->number | DMACH_LOW_LEVEL;
1274
1275         /* restore channel's hardware configuration */
1276
1277         if (!cp->in_use)
1278                 return 0;
1279
1280         printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);
1281
1282         s3c2410_dma_config(no, cp->xfer_unit, cp->dcon);
1283         s3c2410_dma_devconfig(no, cp->source, cp->hw_cfg, cp->dev_addr);
1284
1285         /* re-select the dma source for this channel */
1286
1287         if (cp->map != NULL)
1288                 dma_sel.select(cp, cp->map);
1289
1290         return 0;
1291 }
1292
1293 #else
1294 #define s3c2410_dma_suspend NULL
1295 #define s3c2410_dma_resume  NULL
1296 #endif /* CONFIG_PM */
1297
1298 struct sysdev_class dma_sysclass = {
1299         .name           = "s3c24xx-dma",
1300         .suspend        = s3c2410_dma_suspend,
1301         .resume         = s3c2410_dma_resume,
1302 };
1303
1304 /* kmem cache implementation */
1305
1306 static void s3c2410_dma_cache_ctor(void *p)
1307 {
1308         memset(p, 0, sizeof(struct s3c2410_dma_buf));
1309 }
1310
1311 /* initialisation code */
1312
1313 static int __init s3c24xx_dma_sysclass_init(void)
1314 {
1315         int ret = sysdev_class_register(&dma_sysclass);
1316
1317         if (ret != 0)
1318                 printk(KERN_ERR "dma sysclass registration failed\n");
1319
1320         return ret;
1321 }
1322
1323 core_initcall(s3c24xx_dma_sysclass_init);
1324
1325 static int __init s3c24xx_dma_sysdev_register(void)
1326 {
1327         struct s3c2410_dma_chan *cp = s3c2410_chans;
1328         int channel, ret;
1329
1330         for (channel = 0; channel < dma_channels; cp++, channel++) {
1331                 cp->dev.cls = &dma_sysclass;
1332                 cp->dev.id  = channel;
1333                 ret = sysdev_register(&cp->dev);
1334
1335                 if (ret) {
1336                         printk(KERN_ERR "error registering dev for dma %d\n",
1337                                channel);
1338                         return ret;
1339                 }
1340         }
1341
1342         return 0;
1343 }
1344
1345 late_initcall(s3c24xx_dma_sysdev_register);
1346
1347 int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq,
1348                             unsigned int stride)
1349 {
1350         struct s3c2410_dma_chan *cp;
1351         int channel;
1352         int ret;
1353
1354         printk("S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics\n");
1355
1356         dma_channels = channels;
1357
1358         dma_base = ioremap(S3C24XX_PA_DMA, stride * channels);
1359         if (dma_base == NULL) {
1360                 printk(KERN_ERR "dma failed to remap register block\n");
1361                 return -ENOMEM;
1362         }
1363
1364         dma_kmem = kmem_cache_create("dma_desc",
1365                                      sizeof(struct s3c2410_dma_buf), 0,
1366                                      SLAB_HWCACHE_ALIGN,
1367                                      s3c2410_dma_cache_ctor);
1368
1369         if (dma_kmem == NULL) {
1370                 printk(KERN_ERR "dma failed to make kmem cache\n");
1371                 ret = -ENOMEM;
1372                 goto err;
1373         }
1374
1375         for (channel = 0; channel < channels;  channel++) {
1376                 cp = &s3c2410_chans[channel];
1377
1378                 memset(cp, 0, sizeof(struct s3c2410_dma_chan));
1379
1380                 /* dma channel irqs are in order.. */
1381                 cp->number = channel;
1382                 cp->irq    = channel + irq;
1383                 cp->regs   = dma_base + (channel * stride);
1384
1385                 /* point current stats somewhere */
1386                 cp->stats  = &cp->stats_store;
1387                 cp->stats_store.timeout_shortest = LONG_MAX;
1388
1389                 /* basic channel configuration */
1390
1391                 cp->load_timeout = 1<<18;
1392
1393                 printk("DMA channel %d at %p, irq %d\n",
1394                        cp->number, cp->regs, cp->irq);
1395         }
1396
1397         return 0;
1398
1399  err:
1400         kmem_cache_destroy(dma_kmem);
1401         iounmap(dma_base);
1402         dma_base = NULL;
1403         return ret;
1404 }
1405
1406 int __init s3c2410_dma_init(void)
1407 {
1408         return s3c24xx_dma_init(4, IRQ_DMA0, 0x40);
1409 }
1410
1411 static inline int is_channel_valid(unsigned int channel)
1412 {
1413         return (channel & DMA_CH_VALID);
1414 }
1415
1416 static struct s3c24xx_dma_order *dma_order;
1417
1418
1419 /* s3c2410_dma_map_channel()
1420  *
1421  * turn the virtual channel number into a real, and un-used hardware
1422  * channel.
1423  *
1424  * first, try the dma ordering given to us by either the relevant
1425  * dma code, or the board. Then just find the first usable free
1426  * channel
1427 */
1428
1429 static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
1430 {
1431         struct s3c24xx_dma_order_ch *ord = NULL;
1432         struct s3c24xx_dma_map *ch_map;
1433         struct s3c2410_dma_chan *dmach;
1434         int ch;
1435
1436         if (dma_sel.map == NULL || channel > dma_sel.map_size)
1437                 return NULL;
1438
1439         ch_map = dma_sel.map + channel;
1440
1441         /* first, try the board mapping */
1442
1443         if (dma_order) {
1444                 ord = &dma_order->channels[channel];
1445
1446                 for (ch = 0; ch < dma_channels; ch++) {
1447                         if (!is_channel_valid(ord->list[ch]))
1448                                 continue;
1449
1450                         if (s3c2410_chans[ord->list[ch]].in_use == 0) {
1451                                 ch = ord->list[ch] & ~DMA_CH_VALID;
1452                                 goto found;
1453                         }
1454                 }
1455
1456                 if (ord->flags & DMA_CH_NEVER)
1457                         return NULL;
1458         }
1459
1460         /* second, search the channel map for first free */
1461
1462         for (ch = 0; ch < dma_channels; ch++) {
1463                 if (!is_channel_valid(ch_map->channels[ch]))
1464                         continue;
1465
1466                 if (s3c2410_chans[ch].in_use == 0) {
1467                         printk("mapped channel %d to %d\n", channel, ch);
1468                         break;
1469                 }
1470         }
1471
1472         if (ch >= dma_channels)
1473                 return NULL;
1474
1475         /* update our channel mapping */
1476
1477  found:
1478         dmach = &s3c2410_chans[ch];
1479         dmach->map = ch_map;
1480         dma_chan_map[channel] = dmach;
1481
1482         /* select the channel */
1483
1484         (dma_sel.select)(dmach, ch_map);
1485
1486         return dmach;
1487 }
1488
1489 static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map *map, int ch)
1490 {
1491         return 0;
1492 }
1493
1494 int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel)
1495 {
1496         struct s3c24xx_dma_map *nmap;
1497         size_t map_sz = sizeof(*nmap) * sel->map_size;
1498         int ptr;
1499
1500         nmap = kmalloc(map_sz, GFP_KERNEL);
1501         if (nmap == NULL)
1502                 return -ENOMEM;
1503
1504         memcpy(nmap, sel->map, map_sz);
1505         memcpy(&dma_sel, sel, sizeof(*sel));
1506
1507         dma_sel.map = nmap;
1508
1509         for (ptr = 0; ptr < sel->map_size; ptr++)
1510                 s3c24xx_dma_check_entry(nmap+ptr, ptr);
1511
1512         return 0;
1513 }
1514
1515 int __init s3c24xx_dma_order_set(struct s3c24xx_dma_order *ord)
1516 {
1517         struct s3c24xx_dma_order *nord = dma_order;
1518
1519         if (nord == NULL)
1520                 nord = kmalloc(sizeof(struct s3c24xx_dma_order), GFP_KERNEL);
1521
1522         if (nord == NULL) {
1523                 printk(KERN_ERR "no memory to store dma channel order\n");
1524                 return -ENOMEM;
1525         }
1526
1527         dma_order = nord;
1528         memcpy(nord, ord, sizeof(struct s3c24xx_dma_order));
1529         return 0;
1530 }