1 /* linux/arch/arm/plat-s3c24xx/cpu.c
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Ben Dooks <ben@simtec.co.uk>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/interrupt.h>
28 #include <linux/ioport.h>
29 #include <linux/serial_core.h>
30 #include <linux/platform_device.h>
32 #include <asm/hardware.h>
35 #include <asm/delay.h>
37 #include <asm/mach/arch.h>
38 #include <asm/mach/map.h>
40 #include <asm/arch/regs-gpio.h>
41 #include <asm/arch/regs-serial.h>
43 #include <asm/plat-s3c24xx/cpu.h>
44 #include <asm/plat-s3c24xx/devs.h>
45 #include <asm/plat-s3c24xx/clock.h>
46 #include <asm/plat-s3c24xx/s3c2400.h>
47 #include <asm/plat-s3c24xx/s3c2410.h>
48 #include <asm/plat-s3c24xx/s3c2412.h>
50 #include <asm/plat-s3c24xx/s3c2440.h>
51 #include <asm/plat-s3c24xx/s3c2442.h>
52 #include <asm/plat-s3c24xx/s3c2443.h>
57 void (*map_io)(struct map_desc *mach_desc, int size);
58 void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
59 void (*init_clocks)(int xtal);
64 /* table of supported CPUs */
66 static const char name_s3c2400[] = "S3C2400";
67 static const char name_s3c2410[] = "S3C2410";
68 static const char name_s3c2412[] = "S3C2412";
69 static const char name_s3c2440[] = "S3C2440";
70 static const char name_s3c2442[] = "S3C2442";
71 static const char name_s3c2443[] = "S3C2443";
72 static const char name_s3c2410a[] = "S3C2410A";
73 static const char name_s3c2440a[] = "S3C2440A";
75 static struct cpu_table cpu_ids[] __initdata = {
79 .map_io = s3c2410_map_io,
80 .init_clocks = s3c2410_init_clocks,
81 .init_uarts = s3c2410_init_uarts,
88 .map_io = s3c2410_map_io,
89 .init_clocks = s3c2410_init_clocks,
90 .init_uarts = s3c2410_init_uarts,
97 .map_io = s3c244x_map_io,
98 .init_clocks = s3c244x_init_clocks,
99 .init_uarts = s3c244x_init_uarts,
100 .init = s3c2440_init,
104 .idcode = 0x32440001,
105 .idmask = 0xffffffff,
106 .map_io = s3c244x_map_io,
107 .init_clocks = s3c244x_init_clocks,
108 .init_uarts = s3c244x_init_uarts,
109 .init = s3c2440_init,
110 .name = name_s3c2440a
113 .idcode = 0x32440aaa,
114 .idmask = 0xffffffff,
115 .map_io = s3c244x_map_io,
116 .init_clocks = s3c244x_init_clocks,
117 .init_uarts = s3c244x_init_uarts,
118 .init = s3c2442_init,
122 .idcode = 0x32412001,
123 .idmask = 0xffffffff,
124 .map_io = s3c2412_map_io,
125 .init_clocks = s3c2412_init_clocks,
126 .init_uarts = s3c2412_init_uarts,
127 .init = s3c2412_init,
128 .name = name_s3c2412,
130 { /* a newer version of the s3c2412 */
131 .idcode = 0x32412003,
132 .idmask = 0xffffffff,
133 .map_io = s3c2412_map_io,
134 .init_clocks = s3c2412_init_clocks,
135 .init_uarts = s3c2412_init_uarts,
136 .init = s3c2412_init,
137 .name = name_s3c2412,
140 .idcode = 0x32443001,
141 .idmask = 0xffffffff,
142 .map_io = s3c2443_map_io,
143 .init_clocks = s3c2443_init_clocks,
144 .init_uarts = s3c2443_init_uarts,
145 .init = s3c2443_init,
146 .name = name_s3c2443,
149 .idcode = 0x0, /* S3C2400 doesn't have an idcode */
150 .idmask = 0xffffffff,
151 .map_io = s3c2400_map_io,
152 .init_clocks = s3c2400_init_clocks,
153 .init_uarts = s3c2400_init_uarts,
154 .init = s3c2400_init,
159 /* minimal IO mapping */
161 static struct map_desc s3c_iodesc[] __initdata = {
169 static struct cpu_table *
170 s3c_lookup_cpu(unsigned long idcode)
172 struct cpu_table *tab;
176 for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) {
177 if ((idcode & tab->idmask) == tab->idcode)
184 /* board information */
186 static struct s3c24xx_board *board;
188 void s3c24xx_set_board(struct s3c24xx_board *b)
193 /* cpu information */
195 static struct cpu_table *cpu;
197 static unsigned long s3c24xx_read_idcode_v5(void)
199 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
200 return __raw_readl(S3C2412_GSTATUS1);
202 return 1UL; /* don't look like an 2400 */
206 static unsigned long s3c24xx_read_idcode_v4(void)
208 #ifndef CONFIG_CPU_S3C2400
209 return __raw_readl(S3C2410_GSTATUS1);
215 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
217 unsigned long idcode = 0x0;
219 /* initialise the io descriptors we need for initialisation */
220 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
222 if (cpu_architecture() >= CPU_ARCH_ARMv5) {
223 idcode = s3c24xx_read_idcode_v5();
225 idcode = s3c24xx_read_idcode_v4();
228 cpu = s3c_lookup_cpu(idcode);
231 printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
232 panic("Unknown S3C24XX CPU");
235 printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
237 if (cpu->map_io == NULL || cpu->init == NULL) {
238 printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
239 panic("Unsupported S3C24XX CPU");
242 (cpu->map_io)(mach_desc, size);
245 /* s3c24xx_init_clocks
247 * Initialise the clock subsystem and associated information from the
248 * given master crystal value.
250 * xtal = 0 -> use default PLL crystal value (normally 12MHz)
251 * != 0 -> PLL crystal value in Hz
254 void __init s3c24xx_init_clocks(int xtal)
260 panic("s3c24xx_init_clocks: no cpu setup?\n");
262 if (cpu->init_clocks == NULL)
263 panic("s3c24xx_init_clocks: cpu has no clock init\n");
265 (cpu->init_clocks)(xtal);
268 /* uart management */
270 static int nr_uarts __initdata = 0;
272 static struct s3c2410_uartcfg uart_cfgs[3];
274 /* s3c24xx_init_uartdevs
276 * copy the specified platform data and configuration into our central
277 * set of devices, before the data is thrown away after the init process.
279 * This also fills in the array passed to the serial driver for the
280 * early initialisation of the console.
283 void __init s3c24xx_init_uartdevs(char *name,
284 struct s3c24xx_uart_resources *res,
285 struct s3c2410_uartcfg *cfg, int no)
287 struct platform_device *platdev;
288 struct s3c2410_uartcfg *cfgptr = uart_cfgs;
289 struct s3c24xx_uart_resources *resp;
292 memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
294 for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
295 platdev = s3c24xx_uart_src[cfgptr->hwport];
297 resp = res + cfgptr->hwport;
299 s3c24xx_uart_devs[uart] = platdev;
301 platdev->name = name;
302 platdev->resource = resp->resources;
303 platdev->num_resources = resp->nr_resources;
305 platdev->dev.platform_data = cfgptr;
311 void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
316 if (cpu->init_uarts == NULL) {
317 printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
319 (cpu->init_uarts)(cfg, no);
322 static int __init s3c_arch_init(void)
326 // do the correct init for cpu
329 panic("s3c_arch_init: NULL cpu\n");
335 ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
340 struct platform_device **ptr = board->devices;
343 for (i = 0; i < board->devices_count; i++, ptr++) {
344 ret = platform_device_register(*ptr);
347 printk(KERN_ERR "s3c24xx: failed to add board device %s (%d) @%p\n", (*ptr)->name, ret, *ptr);
351 /* mask any error, we may not need all these board
359 arch_initcall(s3c_arch_init);