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   1 /*
   2  * linux/arch/arm/plat-omap/sram.c
   3  *
   4  * OMAP SRAM detection and management
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Copyright (C) 2009 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16 #undef DEBUG
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/tlb.h>
  24 #include <asm/cacheflush.h>
  25
  26 #include <asm/mach/map.h>
  27
  28 #include <plat/sram.h>
  29 #include <plat/board.h>
  30 #include <plat/cpu.h>
  31 #include <plat/vram.h>
  32
  33 #include <plat/control.h>
  34
  35 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  36 # include "../mach-omap2/prm.h"
  37 # include "../mach-omap2/cm.h"
  38 # include "../mach-omap2/sdrc.h"
  39 #endif
  40
  41 #define OMAP1_SRAM_PA           0x20000000
  42 #define OMAP1_SRAM_VA           VMALLOC_END
  43 #define OMAP2_SRAM_PA           0x40200000
  44 #define OMAP2_SRAM_PUB_PA       0x4020f800
  45 #define OMAP2_SRAM_VA           0xfe400000
  46 #define OMAP2_SRAM_PUB_VA       (OMAP2_SRAM_VA + 0x800)
  47 #define OMAP3_SRAM_PA           0x40200000
  48 #define OMAP3_SRAM_VA           0xfe400000
  49 #define OMAP3_SRAM_PUB_PA       0x40208000
  50 #define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
  51 #define OMAP4_SRAM_PA           0x40200000              /*0x402f0000*/
  52 #define OMAP4_SRAM_VA           0xfe400000              /*0xfe4f0000*/
  53
  54 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
  55 #define SRAM_BOOTLOADER_SZ      0x00
  56 #else
  57 #define SRAM_BOOTLOADER_SZ      0x80
  58 #endif
  59
  60 #define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
  61 #define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
  62 #define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
  63
  64 #define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
  65 #define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
  66 #define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
  67 #define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
  68 #define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
  69 #define OMAP34XX_VA_CONTROL_STAT        OMAP2_L4_IO_ADDRESS(0x480022F0)
  70
  71 #define GP_DEVICE               0x300
  72
  73 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
  74
  75 static unsigned long omap_sram_start;
  76 static unsigned long omap_sram_base;
  77 static unsigned long omap_sram_size;
  78 static unsigned long omap_sram_ceil;
  79
  80 extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
  81                                          unsigned long sram_vstart,
  82                                          unsigned long sram_size,
  83                                          unsigned long pstart_avail,
  84                                          unsigned long size_avail);
  85
  86 /*
  87  * Depending on the target RAMFS firewall setup, the public usable amount of
  88  * SRAM varies.  The default accessible size for all device types is 2k. A GP
  89  * device allows ARM11 but not other initiators for full size. This
  90  * functionality seems ok until some nice security API happens.
  91  */
  92 static int is_sram_locked(void)
  93 {
  94         int type = 0;
  95
  96         if (cpu_is_omap44xx())
  97                 /* Not yet supported */
  98                 return 0;
  99
 100         if (cpu_is_omap242x())
 101                 type = omap_rev() & OMAP2_DEVICETYPE_MASK;
 102
 103         if (type == GP_DEVICE) {
 104                 /* RAMFW: R/W access to all initiators for all qualifier sets */
 105                 if (cpu_is_omap242x()) {
 106                         __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
 107                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
 108                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
 109                 }
 110                 if (cpu_is_omap34xx()) {
 111                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
 112                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
 113                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
 114                         __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
 115                         __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
 116                 }
 117                 return 0;
 118         } else
 119                 return 1; /* assume locked with no PPA or security driver */
 120 }
 121
 122 /*
 123  * The amount of SRAM depends on the core type.
 124  * Note that we cannot try to test for SRAM here because writes
 125  * to secure SRAM will hang the system. Also the SRAM is not
 126  * yet mapped at this point.
 127  */
 128 void __init omap_detect_sram(void)
 129 {
 130         unsigned long reserved;
 131
 132         if (cpu_class_is_omap2()) {
 133                 if (is_sram_locked()) {
 134                         if (cpu_is_omap34xx()) {
 135                                 omap_sram_base = OMAP3_SRAM_PUB_VA;
 136                                 omap_sram_start = OMAP3_SRAM_PUB_PA;
 137                                 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
 138                                     (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
 139                                         omap_sram_size = 0x7000; /* 28K */
 140                                 } else {
 141                                         omap_sram_size = 0x8000; /* 32K */
 142                                 }
 143                         } else {
 144                                 omap_sram_base = OMAP2_SRAM_PUB_VA;
 145                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
 146                                 omap_sram_size = 0x800; /* 2K */
 147                         }
 148                 } else {
 149                         if (cpu_is_omap34xx()) {
 150                                 omap_sram_base = OMAP3_SRAM_VA;
 151                                 omap_sram_start = OMAP3_SRAM_PA;
 152                                 omap_sram_size = 0x10000; /* 64K */
 153                         } else if (cpu_is_omap44xx()) {
 154                                 omap_sram_base = OMAP4_SRAM_VA;
 155                                 omap_sram_start = OMAP4_SRAM_PA;
 156                                 omap_sram_size = 0x8000; /* 32K */
 157                         } else {
 158                                 omap_sram_base = OMAP2_SRAM_VA;
 159                                 omap_sram_start = OMAP2_SRAM_PA;
 160                                 if (cpu_is_omap242x())
 161                                         omap_sram_size = 0xa0000; /* 640K */
 162                                 else if (cpu_is_omap243x())
 163                                         omap_sram_size = 0x10000; /* 64K */
 164                         }
 165                 }
 166         } else {
 167                 omap_sram_base = OMAP1_SRAM_VA;
 168                 omap_sram_start = OMAP1_SRAM_PA;
 169
 170                 if (cpu_is_omap7xx())
 171                         omap_sram_size = 0x32000;       /* 200K */
 172                 else if (cpu_is_omap15xx())
 173                         omap_sram_size = 0x30000;       /* 192K */
 174                 else if (cpu_is_omap1610() || cpu_is_omap1621() ||
 175                      cpu_is_omap1710())
 176                         omap_sram_size = 0x4000;        /* 16K */
 177                 else if (cpu_is_omap1611())
 178                         omap_sram_size = 0x3e800;       /* 250K */
 179                 else {
 180                         printk(KERN_ERR "Could not detect SRAM size\n");
 181                         omap_sram_size = 0x4000;
 182                 }
 183         }
 184         reserved = omapfb_reserve_sram(omap_sram_start, omap_sram_base,
 185                                        omap_sram_size,
 186                                        omap_sram_start + SRAM_BOOTLOADER_SZ,
 187                                        omap_sram_size - SRAM_BOOTLOADER_SZ);
 188         omap_sram_size -= reserved;
 189
 190         reserved = omap_vram_reserve_sram(omap_sram_start, omap_sram_base,
 191                         omap_sram_size,
 192                         omap_sram_start + SRAM_BOOTLOADER_SZ,
 193                         omap_sram_size - SRAM_BOOTLOADER_SZ);
 194         omap_sram_size -= reserved;
 195
 196         omap_sram_ceil = omap_sram_base + omap_sram_size;
 197 }
 198
 199 static struct map_desc omap_sram_io_desc[] __initdata = {
 200         {       /* .length gets filled in at runtime */
 201                 .virtual        = OMAP1_SRAM_VA,
 202                 .pfn            = __phys_to_pfn(OMAP1_SRAM_PA),
 203                 .type           = MT_MEMORY
 204         }
 205 };
 206
 207 /*
 208  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 209  */
 210 void __init omap_map_sram(void)
 211 {
 212         unsigned long base;
 213
 214         if (omap_sram_size == 0)
 215                 return;
 216
 217         if (cpu_is_omap24xx()) {
 218                 omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
 219
 220                 base = OMAP2_SRAM_PA;
 221                 base = ROUND_DOWN(base, PAGE_SIZE);
 222                 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 223         }
 224
 225         if (cpu_is_omap34xx()) {
 226                 omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
 227                 base = OMAP3_SRAM_PA;
 228                 base = ROUND_DOWN(base, PAGE_SIZE);
 229                 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 230
 231                 /*
 232                  * SRAM must be marked as non-cached on OMAP3 since the
 233                  * CORE DPLL M2 divider change code (in SRAM) runs with the
 234                  * SDRAM controller disabled, and if it is marked cached,
 235                  * the ARM may attempt to write cache lines back to SDRAM
 236                  * which will cause the system to hang.
 237                  */
 238                 omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
 239         }
 240
 241         if (cpu_is_omap44xx()) {
 242                 omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA;
 243                 base = OMAP4_SRAM_PA;
 244                 base = ROUND_DOWN(base, PAGE_SIZE);
 245                 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 246         }
 247         omap_sram_io_desc[0].length = 1024 * 1024;      /* Use section desc */
 248         iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
 249
 250         printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
 251         __pfn_to_phys(omap_sram_io_desc[0].pfn),
 252         omap_sram_io_desc[0].virtual,
 253                omap_sram_io_desc[0].length);
 254
 255         /*
 256          * Normally devicemaps_init() would flush caches and tlb after
 257          * mdesc->map_io(), but since we're called from map_io(), we
 258          * must do it here.
 259          */
 260         local_flush_tlb_all();
 261         flush_cache_all();
 262
 263         /*
 264          * Looks like we need to preserve some bootloader code at the
 265          * beginning of SRAM for jumping to flash for reboot to work...
 266          */
 267         memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
 268                omap_sram_size - SRAM_BOOTLOADER_SZ);
 269 }
 270
 271 void * omap_sram_push(void * start, unsigned long size)
 272 {
 273         if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
 274                 printk(KERN_ERR "Not enough space in SRAM\n");
 275                 return NULL;
 276         }
 277
 278         omap_sram_ceil -= size;
 279         omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
 280         memcpy((void *)omap_sram_ceil, start, size);
 281         flush_icache_range((unsigned long)omap_sram_ceil,
 282                 (unsigned long)(omap_sram_ceil + size));
 283
 284         return (void *)omap_sram_ceil;
 285 }
 286
 287 #ifdef CONFIG_ARCH_OMAP1
 288
 289 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
 290
 291 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
 292 {
 293         BUG_ON(!_omap_sram_reprogram_clock);
 294         _omap_sram_reprogram_clock(dpllctl, ckctl);
 295 }
 296
 297 int __init omap1_sram_init(void)
 298 {
 299         _omap_sram_reprogram_clock =
 300                         omap_sram_push(omap1_sram_reprogram_clock,
 301                                         omap1_sram_reprogram_clock_sz);
 302
 303         return 0;
 304 }
 305
 306 #else
 307 #define omap1_sram_init()       do {} while (0)
 308 #endif
 309
 310 #if defined(CONFIG_ARCH_OMAP2)
 311
 312 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 313                               u32 base_cs, u32 force_unlock);
 314
 315 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 316                    u32 base_cs, u32 force_unlock)
 317 {
 318         BUG_ON(!_omap2_sram_ddr_init);
 319         _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
 320                              base_cs, force_unlock);
 321 }
 322
 323 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
 324                                           u32 mem_type);
 325
 326 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
 327 {
 328         BUG_ON(!_omap2_sram_reprogram_sdrc);
 329         _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
 330 }
 331
 332 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 333
 334 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 335 {
 336         BUG_ON(!_omap2_set_prcm);
 337         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
 338 }
 339 #endif
 340
 341 #ifdef CONFIG_ARCH_OMAP2420
 342 int __init omap242x_sram_init(void)
 343 {
 344         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
 345                                         omap242x_sram_ddr_init_sz);
 346
 347         _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
 348                                             omap242x_sram_reprogram_sdrc_sz);
 349
 350         _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
 351                                          omap242x_sram_set_prcm_sz);
 352
 353         return 0;
 354 }
 355 #else
 356 static inline int omap242x_sram_init(void)
 357 {
 358         return 0;
 359 }
 360 #endif
 361
 362 #ifdef CONFIG_ARCH_OMAP2430
 363 int __init omap243x_sram_init(void)
 364 {
 365         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
 366                                         omap243x_sram_ddr_init_sz);
 367
 368         _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
 369                                             omap243x_sram_reprogram_sdrc_sz);
 370
 371         _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
 372                                          omap243x_sram_set_prcm_sz);
 373
 374         return 0;
 375 }
 376 #else
 377 static inline int omap243x_sram_init(void)
 378 {
 379         return 0;
 380 }
 381 #endif
 382
 383 #ifdef CONFIG_ARCH_OMAP3
 384
 385 static u32 (*_omap3_sram_configure_core_dpll)(
 386                         u32 m2, u32 unlock_dll, u32 f, u32 inc,
 387                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 388                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 389                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 390                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 391
 392 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
 393                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 394                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 395                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 396                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
 397 {
 398         BUG_ON(!_omap3_sram_configure_core_dpll);
 399         return _omap3_sram_configure_core_dpll(
 400                         m2, unlock_dll, f, inc,
 401                         sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
 402                         sdrc_actim_ctrl_b_0, sdrc_mr_0,
 403                         sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
 404                         sdrc_actim_ctrl_b_1, sdrc_mr_1);
 405 }
 406
 407 #ifdef CONFIG_PM
 408 void omap3_sram_restore_context(void)
 409 {
 410         omap_sram_ceil = omap_sram_base + omap_sram_size;
 411
 412         _omap3_sram_configure_core_dpll =
 413                 omap_sram_push(omap3_sram_configure_core_dpll,
 414                                omap3_sram_configure_core_dpll_sz);
 415         omap_push_sram_idle();
 416 }
 417 #endif /* CONFIG_PM */
 418
 419 int __init omap34xx_sram_init(void)
 420 {
 421         _omap3_sram_configure_core_dpll =
 422                 omap_sram_push(omap3_sram_configure_core_dpll,
 423                                omap3_sram_configure_core_dpll_sz);
 424         omap_push_sram_idle();
 425         return 0;
 426 }
 427 #else
 428 static inline int omap34xx_sram_init(void)
 429 {
 430         return 0;
 431 }
 432 #endif
 433
 434 int __init omap_sram_init(void)
 435 {
 436         omap_detect_sram();
 437         omap_map_sram();
 438
 439         if (!(cpu_class_is_omap2()))
 440                 omap1_sram_init();
 441         else if (cpu_is_omap242x())
 442                 omap242x_sram_init();
 443         else if (cpu_is_omap2430())
 444                 omap243x_sram_init();
 445         else if (cpu_is_omap34xx())
 446                 omap34xx_sram_init();
 447         else if (cpu_is_omap44xx())
 448                 omap34xx_sram_init(); /* FIXME: */
 449
 450         return 0;
 451 }