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   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/wait.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24 #include <linux/delay.h>
  25 #include <linux/io.h>
  26
  27 #include <mach/dma.h>
  28 #include <mach/mcbsp.h>
  29
  30 struct omap_mcbsp **mcbsp_ptr;
  31 int omap_mcbsp_count;
  32
  33 void omap_mcbsp_write(void __iomem *io_base, u16 reg, u32 val)
  34 {
  35         if (cpu_class_is_omap1() || cpu_is_omap2420())
  36                 __raw_writew((u16)val, io_base + reg);
  37         else
  38                 __raw_writel(val, io_base + reg);
  39 }
  40
  41 int omap_mcbsp_read(void __iomem *io_base, u16 reg)
  42 {
  43         if (cpu_class_is_omap1() || cpu_is_omap2420())
  44                 return __raw_readw(io_base + reg);
  45         else
  46                 return __raw_readl(io_base + reg);
  47 }
  48
  49 #define OMAP_MCBSP_READ(base, reg) \
  50                         omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg)
  51 #define OMAP_MCBSP_WRITE(base, reg, val) \
  52                         omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val)
  53
  54 #define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
  55 #define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
  56
  57 static void omap_mcbsp_dump_reg(u8 id)
  58 {
  59         struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
  60
  61         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  62         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
  63                         OMAP_MCBSP_READ(mcbsp->io_base, DRR2));
  64         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
  65                         OMAP_MCBSP_READ(mcbsp->io_base, DRR1));
  66         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
  67                         OMAP_MCBSP_READ(mcbsp->io_base, DXR2));
  68         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
  69                         OMAP_MCBSP_READ(mcbsp->io_base, DXR1));
  70         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
  71                         OMAP_MCBSP_READ(mcbsp->io_base, SPCR2));
  72         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
  73                         OMAP_MCBSP_READ(mcbsp->io_base, SPCR1));
  74         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
  75                         OMAP_MCBSP_READ(mcbsp->io_base, RCR2));
  76         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
  77                         OMAP_MCBSP_READ(mcbsp->io_base, RCR1));
  78         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
  79                         OMAP_MCBSP_READ(mcbsp->io_base, XCR2));
  80         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
  81                         OMAP_MCBSP_READ(mcbsp->io_base, XCR1));
  82         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
  83                         OMAP_MCBSP_READ(mcbsp->io_base, SRGR2));
  84         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
  85                         OMAP_MCBSP_READ(mcbsp->io_base, SRGR1));
  86         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
  87                         OMAP_MCBSP_READ(mcbsp->io_base, PCR0));
  88         dev_dbg(mcbsp->dev, "***********************\n");
  89 }
  90
  91 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
  92 {
  93         struct omap_mcbsp *mcbsp_tx = dev_id;
  94         u16 irqst_spcr2;
  95
  96         irqst_spcr2 = OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2);
  97         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
  98
  99         if (irqst_spcr2 & XSYNC_ERR) {
 100                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
 101                         irqst_spcr2);
 102                 /* Writing zero to XSYNC_ERR clears the IRQ */
 103                 OMAP_MCBSP_WRITE(mcbsp_tx->io_base, SPCR2,
 104                         irqst_spcr2 & ~(XSYNC_ERR));
 105         } else {
 106                 complete(&mcbsp_tx->tx_irq_completion);
 107         }
 108
 109         return IRQ_HANDLED;
 110 }
 111
 112 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 113 {
 114         struct omap_mcbsp *mcbsp_rx = dev_id;
 115         u16 irqst_spcr1;
 116
 117         irqst_spcr1 = OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR1);
 118         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 119
 120         if (irqst_spcr1 & RSYNC_ERR) {
 121                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
 122                         irqst_spcr1);
 123                 /* Writing zero to RSYNC_ERR clears the IRQ */
 124                 OMAP_MCBSP_WRITE(mcbsp_rx->io_base, SPCR1,
 125                         irqst_spcr1 & ~(RSYNC_ERR));
 126         } else {
 127                 complete(&mcbsp_rx->tx_irq_completion);
 128         }
 129
 130         return IRQ_HANDLED;
 131 }
 132
 133 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 134 {
 135         struct omap_mcbsp *mcbsp_dma_tx = data;
 136
 137         dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
 138                 OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
 139
 140         /* We can free the channels */
 141         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
 142         mcbsp_dma_tx->dma_tx_lch = -1;
 143
 144         complete(&mcbsp_dma_tx->tx_dma_completion);
 145 }
 146
 147 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 148 {
 149         struct omap_mcbsp *mcbsp_dma_rx = data;
 150
 151         dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
 152                 OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
 153
 154         /* We can free the channels */
 155         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
 156         mcbsp_dma_rx->dma_rx_lch = -1;
 157
 158         complete(&mcbsp_dma_rx->rx_dma_completion);
 159 }
 160
 161 /*
 162  * omap_mcbsp_config simply write a config to the
 163  * appropriate McBSP.
 164  * You either call this function or set the McBSP registers
 165  * by yourself before calling omap_mcbsp_start().
 166  */
 167 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 168 {
 169         struct omap_mcbsp *mcbsp;
 170         void __iomem *io_base;
 171
 172         if (!omap_mcbsp_check_valid_id(id)) {
 173                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 174                 return;
 175         }
 176         mcbsp = id_to_mcbsp_ptr(id);
 177
 178         io_base = mcbsp->io_base;
 179         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 180                         mcbsp->id, mcbsp->phys_base);
 181
 182         /* We write the given config */
 183         OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
 184         OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
 185         OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
 186         OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
 187         OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
 188         OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
 189         OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
 190         OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
 191         OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
 192         OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
 193         OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
 194         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 195                 OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
 196                 OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
 197         }
 198 }
 199 EXPORT_SYMBOL(omap_mcbsp_config);
 200
 201 #ifdef CONFIG_ARCH_OMAP34XX
 202 /*
 203  * omap_mcbsp_set_tx_threshold configures how to deal
 204  * with transmit threshold. the threshold value and handler can be
 205  * configure in here.
 206  */
 207 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 208 {
 209         struct omap_mcbsp *mcbsp;
 210         void __iomem *io_base;
 211
 212         if (!cpu_is_omap34xx())
 213                 return;
 214
 215         if (!omap_mcbsp_check_valid_id(id)) {
 216                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 217                 return;
 218         }
 219         mcbsp = id_to_mcbsp_ptr(id);
 220         io_base = mcbsp->io_base;
 221
 222         OMAP_MCBSP_WRITE(io_base, THRSH2, threshold);
 223 }
 224 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
 225
 226 /*
 227  * omap_mcbsp_set_rx_threshold configures how to deal
 228  * with receive threshold. the threshold value and handler can be
 229  * configure in here.
 230  */
 231 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 232 {
 233         struct omap_mcbsp *mcbsp;
 234         void __iomem *io_base;
 235
 236         if (!cpu_is_omap34xx())
 237                 return;
 238
 239         if (!omap_mcbsp_check_valid_id(id)) {
 240                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 241                 return;
 242         }
 243         mcbsp = id_to_mcbsp_ptr(id);
 244         io_base = mcbsp->io_base;
 245
 246         OMAP_MCBSP_WRITE(io_base, THRSH1, threshold);
 247 }
 248 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
 249
 250 /*
 251  * omap_mcbsp_get_max_tx_thres just return the current configured
 252  * maximum threshold for transmission
 253  */
 254 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
 255 {
 256         struct omap_mcbsp *mcbsp;
 257
 258         if (!omap_mcbsp_check_valid_id(id)) {
 259                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 260                 return -ENODEV;
 261         }
 262         mcbsp = id_to_mcbsp_ptr(id);
 263
 264         return mcbsp->max_tx_thres;
 265 }
 266 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
 267
 268 /*
 269  * omap_mcbsp_get_max_rx_thres just return the current configured
 270  * maximum threshold for reception
 271  */
 272 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
 273 {
 274         struct omap_mcbsp *mcbsp;
 275
 276         if (!omap_mcbsp_check_valid_id(id)) {
 277                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 278                 return -ENODEV;
 279         }
 280         mcbsp = id_to_mcbsp_ptr(id);
 281
 282         return mcbsp->max_rx_thres;
 283 }
 284 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
 285 #endif
 286
 287 /*
 288  * We can choose between IRQ based or polled IO.
 289  * This needs to be called before omap_mcbsp_request().
 290  */
 291 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 292 {
 293         struct omap_mcbsp *mcbsp;
 294
 295         if (!omap_mcbsp_check_valid_id(id)) {
 296                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 297                 return -ENODEV;
 298         }
 299         mcbsp = id_to_mcbsp_ptr(id);
 300
 301         spin_lock(&mcbsp->lock);
 302
 303         if (!mcbsp->free) {
 304                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 305                         mcbsp->id);
 306                 spin_unlock(&mcbsp->lock);
 307                 return -EINVAL;
 308         }
 309
 310         mcbsp->io_type = io_type;
 311
 312         spin_unlock(&mcbsp->lock);
 313
 314         return 0;
 315 }
 316 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
 317
 318 int omap_mcbsp_request(unsigned int id)
 319 {
 320         struct omap_mcbsp *mcbsp;
 321         int err;
 322
 323         if (!omap_mcbsp_check_valid_id(id)) {
 324                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 325                 return -ENODEV;
 326         }
 327         mcbsp = id_to_mcbsp_ptr(id);
 328
 329         spin_lock(&mcbsp->lock);
 330         if (!mcbsp->free) {
 331                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 332                         mcbsp->id);
 333                 spin_unlock(&mcbsp->lock);
 334                 return -EBUSY;
 335         }
 336
 337         mcbsp->free = 0;
 338         spin_unlock(&mcbsp->lock);
 339
 340         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 341                 mcbsp->pdata->ops->request(id);
 342
 343         clk_enable(mcbsp->iclk);
 344         clk_enable(mcbsp->fclk);
 345
 346         /*
 347          * Make sure that transmitter, receiver and sample-rate generator are
 348          * not running before activating IRQs.
 349          */
 350         OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR1, 0);
 351         OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR2, 0);
 352
 353         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 354                 /* We need to get IRQs here */
 355                 init_completion(&mcbsp->tx_irq_completion);
 356                 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
 357                                         0, "McBSP", (void *)mcbsp);
 358                 if (err != 0) {
 359                         dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
 360                                         "for McBSP%d\n", mcbsp->tx_irq,
 361                                         mcbsp->id);
 362                         return err;
 363                 }
 364
 365                 init_completion(&mcbsp->rx_irq_completion);
 366                 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
 367                                         0, "McBSP", (void *)mcbsp);
 368                 if (err != 0) {
 369                         dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
 370                                         "for McBSP%d\n", mcbsp->rx_irq,
 371                                         mcbsp->id);
 372                         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 373                         return err;
 374                 }
 375         }
 376
 377         return 0;
 378 }
 379 EXPORT_SYMBOL(omap_mcbsp_request);
 380
 381 void omap_mcbsp_free(unsigned int id)
 382 {
 383         struct omap_mcbsp *mcbsp;
 384
 385         if (!omap_mcbsp_check_valid_id(id)) {
 386                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 387                 return;
 388         }
 389         mcbsp = id_to_mcbsp_ptr(id);
 390
 391         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 392                 mcbsp->pdata->ops->free(id);
 393
 394         clk_disable(mcbsp->fclk);
 395         clk_disable(mcbsp->iclk);
 396
 397         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 398                 /* Free IRQs */
 399                 free_irq(mcbsp->rx_irq, (void *)mcbsp);
 400                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
 401         }
 402
 403         spin_lock(&mcbsp->lock);
 404         if (mcbsp->free) {
 405                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n",
 406                         mcbsp->id);
 407                 spin_unlock(&mcbsp->lock);
 408                 return;
 409         }
 410
 411         mcbsp->free = 1;
 412         spin_unlock(&mcbsp->lock);
 413 }
 414 EXPORT_SYMBOL(omap_mcbsp_free);
 415
 416 /*
 417  * Here we start the McBSP, by enabling transmitter, receiver or both.
 418  * If no transmitter or receiver is active prior calling, then sample-rate
 419  * generator and frame sync are started.
 420  */
 421 void omap_mcbsp_start(unsigned int id, int tx, int rx)
 422 {
 423         struct omap_mcbsp *mcbsp;
 424         void __iomem *io_base;
 425         int idle;
 426         u16 w;
 427
 428         if (!omap_mcbsp_check_valid_id(id)) {
 429                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 430                 return;
 431         }
 432         mcbsp = id_to_mcbsp_ptr(id);
 433         io_base = mcbsp->io_base;
 434
 435         mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
 436         mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
 437
 438         idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
 439                   OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
 440
 441         if (idle) {
 442                 /* Start the sample generator */
 443                 w = OMAP_MCBSP_READ(io_base, SPCR2);
 444                 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
 445         }
 446
 447         /* Enable transmitter and receiver */
 448         w = OMAP_MCBSP_READ(io_base, SPCR2);
 449         OMAP_MCBSP_WRITE(io_base, SPCR2, w | (tx & 1));
 450
 451         w = OMAP_MCBSP_READ(io_base, SPCR1);
 452         OMAP_MCBSP_WRITE(io_base, SPCR1, w | (rx & 1));
 453
 454         /*
 455          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
 456          * REVISIT: 100us may give enough time for two CLKSRG, however
 457          * due to some unknown PM related, clock gating etc. reason it
 458          * is now at 500us.
 459          */
 460         udelay(500);
 461
 462         if (idle) {
 463                 /* Start frame sync */
 464                 w = OMAP_MCBSP_READ(io_base, SPCR2);
 465                 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
 466         }
 467
 468         /* Dump McBSP Regs */
 469         omap_mcbsp_dump_reg(id);
 470 }
 471 EXPORT_SYMBOL(omap_mcbsp_start);
 472
 473 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 474 {
 475         struct omap_mcbsp *mcbsp;
 476         void __iomem *io_base;
 477         int idle;
 478         u16 w;
 479
 480         if (!omap_mcbsp_check_valid_id(id)) {
 481                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 482                 return;
 483         }
 484
 485         mcbsp = id_to_mcbsp_ptr(id);
 486         io_base = mcbsp->io_base;
 487
 488         /* Reset transmitter */
 489         w = OMAP_MCBSP_READ(io_base, SPCR2);
 490         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(tx & 1));
 491
 492         /* Reset receiver */
 493         w = OMAP_MCBSP_READ(io_base, SPCR1);
 494         OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(rx & 1));
 495
 496         idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
 497                   OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
 498
 499         if (idle) {
 500                 /* Reset the sample rate generator */
 501                 w = OMAP_MCBSP_READ(io_base, SPCR2);
 502                 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
 503         }
 504 }
 505 EXPORT_SYMBOL(omap_mcbsp_stop);
 506
 507 void omap_mcbsp_xmit_enable(unsigned int id, u8 enable)
 508 {
 509         struct omap_mcbsp *mcbsp;
 510         void __iomem *io_base;
 511         u16 w;
 512
 513         if (!(cpu_is_omap2430() || cpu_is_omap34xx()))
 514                 return;
 515
 516         if (!omap_mcbsp_check_valid_id(id)) {
 517                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 518                 return;
 519         }
 520
 521         mcbsp = id_to_mcbsp_ptr(id);
 522         io_base = mcbsp->io_base;
 523
 524         w = OMAP_MCBSP_READ(io_base, XCCR);
 525
 526         if (enable)
 527                 OMAP_MCBSP_WRITE(io_base, XCCR, w & ~(XDISABLE));
 528         else
 529                 OMAP_MCBSP_WRITE(io_base, XCCR, w | XDISABLE);
 530 }
 531 EXPORT_SYMBOL(omap_mcbsp_xmit_enable);
 532
 533 void omap_mcbsp_recv_enable(unsigned int id, u8 enable)
 534 {
 535         struct omap_mcbsp *mcbsp;
 536         void __iomem *io_base;
 537         u16 w;
 538
 539         if (!(cpu_is_omap2430() || cpu_is_omap34xx()))
 540                 return;
 541
 542         if (!omap_mcbsp_check_valid_id(id)) {
 543                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 544                 return;
 545         }
 546
 547         mcbsp = id_to_mcbsp_ptr(id);
 548         io_base = mcbsp->io_base;
 549
 550         w = OMAP_MCBSP_READ(io_base, RCCR);
 551
 552         if (enable)
 553                 OMAP_MCBSP_WRITE(io_base, RCCR, w & ~(RDISABLE));
 554         else
 555                 OMAP_MCBSP_WRITE(io_base, RCCR, w | RDISABLE);
 556 }
 557 EXPORT_SYMBOL(omap_mcbsp_recv_enable);
 558
 559 /* polled mcbsp i/o operations */
 560 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 561 {
 562         struct omap_mcbsp *mcbsp;
 563         void __iomem *base;
 564
 565         if (!omap_mcbsp_check_valid_id(id)) {
 566                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 567                 return -ENODEV;
 568         }
 569
 570         mcbsp = id_to_mcbsp_ptr(id);
 571         base = mcbsp->io_base;
 572
 573         writew(buf, base + OMAP_MCBSP_REG_DXR1);
 574         /* if frame sync error - clear the error */
 575         if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
 576                 /* clear error */
 577                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
 578                        base + OMAP_MCBSP_REG_SPCR2);
 579                 /* resend */
 580                 return -1;
 581         } else {
 582                 /* wait for transmit confirmation */
 583                 int attemps = 0;
 584                 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
 585                         if (attemps++ > 1000) {
 586                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
 587                                        (~XRST),
 588                                        base + OMAP_MCBSP_REG_SPCR2);
 589                                 udelay(10);
 590                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
 591                                        (XRST),
 592                                        base + OMAP_MCBSP_REG_SPCR2);
 593                                 udelay(10);
 594                                 dev_err(mcbsp->dev, "Could not write to"
 595                                         " McBSP%d Register\n", mcbsp->id);
 596                                 return -2;
 597                         }
 598                 }
 599         }
 600
 601         return 0;
 602 }
 603 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
 604
 605 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
 606 {
 607         struct omap_mcbsp *mcbsp;
 608         void __iomem *base;
 609
 610         if (!omap_mcbsp_check_valid_id(id)) {
 611                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 612                 return -ENODEV;
 613         }
 614         mcbsp = id_to_mcbsp_ptr(id);
 615
 616         base = mcbsp->io_base;
 617         /* if frame sync error - clear the error */
 618         if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
 619                 /* clear error */
 620                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
 621                        base + OMAP_MCBSP_REG_SPCR1);
 622                 /* resend */
 623                 return -1;
 624         } else {
 625                 /* wait for recieve confirmation */
 626                 int attemps = 0;
 627                 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
 628                         if (attemps++ > 1000) {
 629                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
 630                                        (~RRST),
 631                                        base + OMAP_MCBSP_REG_SPCR1);
 632                                 udelay(10);
 633                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
 634                                        (RRST),
 635                                        base + OMAP_MCBSP_REG_SPCR1);
 636                                 udelay(10);
 637                                 dev_err(mcbsp->dev, "Could not read from"
 638                                         " McBSP%d Register\n", mcbsp->id);
 639                                 return -2;
 640                         }
 641                 }
 642         }
 643         *buf = readw(base + OMAP_MCBSP_REG_DRR1);
 644
 645         return 0;
 646 }
 647 EXPORT_SYMBOL(omap_mcbsp_pollread);
 648
 649 /*
 650  * IRQ based word transmission.
 651  */
 652 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
 653 {
 654         struct omap_mcbsp *mcbsp;
 655         void __iomem *io_base;
 656         omap_mcbsp_word_length word_length;
 657
 658         if (!omap_mcbsp_check_valid_id(id)) {
 659                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 660                 return;
 661         }
 662
 663         mcbsp = id_to_mcbsp_ptr(id);
 664         io_base = mcbsp->io_base;
 665         word_length = mcbsp->tx_word_length;
 666
 667         wait_for_completion(&mcbsp->tx_irq_completion);
 668
 669         if (word_length > OMAP_MCBSP_WORD_16)
 670                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 671         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 672 }
 673 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
 674
 675 u32 omap_mcbsp_recv_word(unsigned int id)
 676 {
 677         struct omap_mcbsp *mcbsp;
 678         void __iomem *io_base;
 679         u16 word_lsb, word_msb = 0;
 680         omap_mcbsp_word_length word_length;
 681
 682         if (!omap_mcbsp_check_valid_id(id)) {
 683                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 684                 return -ENODEV;
 685         }
 686         mcbsp = id_to_mcbsp_ptr(id);
 687
 688         word_length = mcbsp->rx_word_length;
 689         io_base = mcbsp->io_base;
 690
 691         wait_for_completion(&mcbsp->rx_irq_completion);
 692
 693         if (word_length > OMAP_MCBSP_WORD_16)
 694                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 695         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 696
 697         return (word_lsb | (word_msb << 16));
 698 }
 699 EXPORT_SYMBOL(omap_mcbsp_recv_word);
 700
 701 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 702 {
 703         struct omap_mcbsp *mcbsp;
 704         void __iomem *io_base;
 705         omap_mcbsp_word_length tx_word_length;
 706         omap_mcbsp_word_length rx_word_length;
 707         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 708
 709         if (!omap_mcbsp_check_valid_id(id)) {
 710                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 711                 return -ENODEV;
 712         }
 713         mcbsp = id_to_mcbsp_ptr(id);
 714         io_base = mcbsp->io_base;
 715         tx_word_length = mcbsp->tx_word_length;
 716         rx_word_length = mcbsp->rx_word_length;
 717
 718         if (tx_word_length != rx_word_length)
 719                 return -EINVAL;
 720
 721         /* First we wait for the transmitter to be ready */
 722         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 723         while (!(spcr2 & XRDY)) {
 724                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 725                 if (attempts++ > 1000) {
 726                         /* We must reset the transmitter */
 727                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 728                         udelay(10);
 729                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 730                         udelay(10);
 731                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
 732                                 "ready\n", mcbsp->id);
 733                         return -EAGAIN;
 734                 }
 735         }
 736
 737         /* Now we can push the data */
 738         if (tx_word_length > OMAP_MCBSP_WORD_16)
 739                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 740         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 741
 742         /* We wait for the receiver to be ready */
 743         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 744         while (!(spcr1 & RRDY)) {
 745                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 746                 if (attempts++ > 1000) {
 747                         /* We must reset the receiver */
 748                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 749                         udelay(10);
 750                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 751                         udelay(10);
 752                         dev_err(mcbsp->dev, "McBSP%d receiver not "
 753                                 "ready\n", mcbsp->id);
 754                         return -EAGAIN;
 755                 }
 756         }
 757
 758         /* Receiver is ready, let's read the dummy data */
 759         if (rx_word_length > OMAP_MCBSP_WORD_16)
 760                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 761         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 762
 763         return 0;
 764 }
 765 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
 766
 767 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
 768 {
 769         struct omap_mcbsp *mcbsp;
 770         u32 clock_word = 0;
 771         void __iomem *io_base;
 772         omap_mcbsp_word_length tx_word_length;
 773         omap_mcbsp_word_length rx_word_length;
 774         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 775
 776         if (!omap_mcbsp_check_valid_id(id)) {
 777                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 778                 return -ENODEV;
 779         }
 780
 781         mcbsp = id_to_mcbsp_ptr(id);
 782         io_base = mcbsp->io_base;
 783
 784         tx_word_length = mcbsp->tx_word_length;
 785         rx_word_length = mcbsp->rx_word_length;
 786
 787         if (tx_word_length != rx_word_length)
 788                 return -EINVAL;
 789
 790         /* First we wait for the transmitter to be ready */
 791         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 792         while (!(spcr2 & XRDY)) {
 793                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 794                 if (attempts++ > 1000) {
 795                         /* We must reset the transmitter */
 796                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 797                         udelay(10);
 798                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 799                         udelay(10);
 800                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
 801                                 "ready\n", mcbsp->id);
 802                         return -EAGAIN;
 803                 }
 804         }
 805
 806         /* We first need to enable the bus clock */
 807         if (tx_word_length > OMAP_MCBSP_WORD_16)
 808                 OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
 809         OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
 810
 811         /* We wait for the receiver to be ready */
 812         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 813         while (!(spcr1 & RRDY)) {
 814                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 815                 if (attempts++ > 1000) {
 816                         /* We must reset the receiver */
 817                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 818                         udelay(10);
 819                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 820                         udelay(10);
 821                         dev_err(mcbsp->dev, "McBSP%d receiver not "
 822                                 "ready\n", mcbsp->id);
 823                         return -EAGAIN;
 824                 }
 825         }
 826
 827         /* Receiver is ready, there is something for us */
 828         if (rx_word_length > OMAP_MCBSP_WORD_16)
 829                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 830         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 831
 832         word[0] = (word_lsb | (word_msb << 16));
 833
 834         return 0;
 835 }
 836 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
 837
 838 /*
 839  * Simple DMA based buffer rx/tx routines.
 840  * Nothing fancy, just a single buffer tx/rx through DMA.
 841  * The DMA resources are released once the transfer is done.
 842  * For anything fancier, you should use your own customized DMA
 843  * routines and callbacks.
 844  */
 845 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
 846                                 unsigned int length)
 847 {
 848         struct omap_mcbsp *mcbsp;
 849         int dma_tx_ch;
 850         int src_port = 0;
 851         int dest_port = 0;
 852         int sync_dev = 0;
 853
 854         if (!omap_mcbsp_check_valid_id(id)) {
 855                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 856                 return -ENODEV;
 857         }
 858         mcbsp = id_to_mcbsp_ptr(id);
 859
 860         if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
 861                                 omap_mcbsp_tx_dma_callback,
 862                                 mcbsp,
 863                                 &dma_tx_ch)) {
 864                 dev_err(mcbsp->dev, " Unable to request DMA channel for "
 865                                 "McBSP%d TX. Trying IRQ based TX\n",
 866                                 mcbsp->id);
 867                 return -EAGAIN;
 868         }
 869         mcbsp->dma_tx_lch = dma_tx_ch;
 870
 871         dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
 872                 dma_tx_ch);
 873
 874         init_completion(&mcbsp->tx_dma_completion);
 875
 876         if (cpu_class_is_omap1()) {
 877                 src_port = OMAP_DMA_PORT_TIPB;
 878                 dest_port = OMAP_DMA_PORT_EMIFF;
 879         }
 880         if (cpu_class_is_omap2())
 881                 sync_dev = mcbsp->dma_tx_sync;
 882
 883         omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
 884                                      OMAP_DMA_DATA_TYPE_S16,
 885                                      length >> 1, 1,
 886                                      OMAP_DMA_SYNC_ELEMENT,
 887          sync_dev, 0);
 888
 889         omap_set_dma_dest_params(mcbsp->dma_tx_lch,
 890                                  src_port,
 891                                  OMAP_DMA_AMODE_CONSTANT,
 892                                  mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
 893                                  0, 0);
 894
 895         omap_set_dma_src_params(mcbsp->dma_tx_lch,
 896                                 dest_port,
 897                                 OMAP_DMA_AMODE_POST_INC,
 898                                 buffer,
 899                                 0, 0);
 900
 901         omap_start_dma(mcbsp->dma_tx_lch);
 902         wait_for_completion(&mcbsp->tx_dma_completion);
 903
 904         return 0;
 905 }
 906 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
 907
 908 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
 909                                 unsigned int length)
 910 {
 911         struct omap_mcbsp *mcbsp;
 912         int dma_rx_ch;
 913         int src_port = 0;
 914         int dest_port = 0;
 915         int sync_dev = 0;
 916
 917         if (!omap_mcbsp_check_valid_id(id)) {
 918                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 919                 return -ENODEV;
 920         }
 921         mcbsp = id_to_mcbsp_ptr(id);
 922
 923         if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
 924                                 omap_mcbsp_rx_dma_callback,
 925                                 mcbsp,
 926                                 &dma_rx_ch)) {
 927                 dev_err(mcbsp->dev, "Unable to request DMA channel for "
 928                                 "McBSP%d RX. Trying IRQ based RX\n",
 929                                 mcbsp->id);
 930                 return -EAGAIN;
 931         }
 932         mcbsp->dma_rx_lch = dma_rx_ch;
 933
 934         dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
 935                 dma_rx_ch);
 936
 937         init_completion(&mcbsp->rx_dma_completion);
 938
 939         if (cpu_class_is_omap1()) {
 940                 src_port = OMAP_DMA_PORT_TIPB;
 941                 dest_port = OMAP_DMA_PORT_EMIFF;
 942         }
 943         if (cpu_class_is_omap2())
 944                 sync_dev = mcbsp->dma_rx_sync;
 945
 946         omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
 947                                         OMAP_DMA_DATA_TYPE_S16,
 948                                         length >> 1, 1,
 949                                         OMAP_DMA_SYNC_ELEMENT,
 950                                         sync_dev, 0);
 951
 952         omap_set_dma_src_params(mcbsp->dma_rx_lch,
 953                                 src_port,
 954                                 OMAP_DMA_AMODE_CONSTANT,
 955                                 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
 956                                 0, 0);
 957
 958         omap_set_dma_dest_params(mcbsp->dma_rx_lch,
 959                                         dest_port,
 960                                         OMAP_DMA_AMODE_POST_INC,
 961                                         buffer,
 962                                         0, 0);
 963
 964         omap_start_dma(mcbsp->dma_rx_lch);
 965         wait_for_completion(&mcbsp->rx_dma_completion);
 966
 967         return 0;
 968 }
 969 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
 970
 971 /*
 972  * SPI wrapper.
 973  * Since SPI setup is much simpler than the generic McBSP one,
 974  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
 975  * Once this is done, you can call omap_mcbsp_start().
 976  */
 977 void omap_mcbsp_set_spi_mode(unsigned int id,
 978                                 const struct omap_mcbsp_spi_cfg *spi_cfg)
 979 {
 980         struct omap_mcbsp *mcbsp;
 981         struct omap_mcbsp_reg_cfg mcbsp_cfg;
 982
 983         if (!omap_mcbsp_check_valid_id(id)) {
 984                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 985                 return;
 986         }
 987         mcbsp = id_to_mcbsp_ptr(id);
 988
 989         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
 990
 991         /* SPI has only one frame */
 992         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
 993         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
 994
 995         /* Clock stop mode */
 996         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
 997                 mcbsp_cfg.spcr1 |= (1 << 12);
 998         else
 999                 mcbsp_cfg.spcr1 |= (3 << 11);
1000
1001         /* Set clock parities */
1002         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1003                 mcbsp_cfg.pcr0 |= CLKRP;
1004         else
1005                 mcbsp_cfg.pcr0 &= ~CLKRP;
1006
1007         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1008                 mcbsp_cfg.pcr0 &= ~CLKXP;
1009         else
1010                 mcbsp_cfg.pcr0 |= CLKXP;
1011
1012         /* Set SCLKME to 0 and CLKSM to 1 */
1013         mcbsp_cfg.pcr0 &= ~SCLKME;
1014         mcbsp_cfg.srgr2 |= CLKSM;
1015
1016         /* Set FSXP */
1017         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1018                 mcbsp_cfg.pcr0 &= ~FSXP;
1019         else
1020                 mcbsp_cfg.pcr0 |= FSXP;
1021
1022         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1023                 mcbsp_cfg.pcr0 |= CLKXM;
1024                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1025                 mcbsp_cfg.pcr0 |= FSXM;
1026                 mcbsp_cfg.srgr2 &= ~FSGM;
1027                 mcbsp_cfg.xcr2 |= XDATDLY(1);
1028                 mcbsp_cfg.rcr2 |= RDATDLY(1);
1029         } else {
1030                 mcbsp_cfg.pcr0 &= ~CLKXM;
1031                 mcbsp_cfg.srgr1 |= CLKGDV(1);
1032                 mcbsp_cfg.pcr0 &= ~FSXM;
1033                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1034                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1035         }
1036
1037         mcbsp_cfg.xcr2 &= ~XPHASE;
1038         mcbsp_cfg.rcr2 &= ~RPHASE;
1039
1040         omap_mcbsp_config(id, &mcbsp_cfg);
1041 }
1042 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1043
1044 #ifdef CONFIG_ARCH_OMAP34XX
1045 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
1046 #define valid_threshold(m, val)         ((val) <= max_thres(m))
1047 #define THRESHOLD_PROP_BUILDER(prop)                                    \
1048 static ssize_t prop##_show(struct device *dev,                          \
1049                         struct device_attribute *attr, char *buf)       \
1050 {                                                                       \
1051         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1052                                                                         \
1053         return sprintf(buf, "%u\n", mcbsp->prop);                       \
1054 }                                                                       \
1055                                                                         \
1056 static ssize_t prop##_store(struct device *dev,                         \
1057                                 struct device_attribute *attr,          \
1058                                 const char *buf, size_t size)           \
1059 {                                                                       \
1060         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1061         unsigned long val;                                              \
1062         int status;                                                     \
1063                                                                         \
1064         status = strict_strtoul(buf, 0, &val);                          \
1065         if (status)                                                     \
1066                 return status;                                          \
1067                                                                         \
1068         if (!valid_threshold(mcbsp, val))                               \
1069                 return -EDOM;                                           \
1070                                                                         \
1071         mcbsp->prop = val;                                              \
1072         return size;                                                    \
1073 }                                                                       \
1074                                                                         \
1075 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1076
1077 THRESHOLD_PROP_BUILDER(max_tx_thres);
1078 THRESHOLD_PROP_BUILDER(max_rx_thres);
1079
1080 static const struct attribute *threshold_attrs[] = {
1081         &dev_attr_max_tx_thres.attr,
1082         &dev_attr_max_rx_thres.attr,
1083         NULL,
1084 };
1085
1086 static const struct attribute_group threshold_attr_group = {
1087         .attrs = (struct attribute **)threshold_attrs,
1088 };
1089
1090 static inline int __devinit omap_thres_add(struct device *dev)
1091 {
1092         return sysfs_create_group(&dev->kobj, &threshold_attr_group);
1093 }
1094
1095 static inline void __devexit omap_thres_remove(struct device *dev)
1096 {
1097         sysfs_remove_group(&dev->kobj, &threshold_attr_group);
1098 }
1099
1100 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1101 {
1102         if (cpu_is_omap34xx()) {
1103                 mcbsp->max_tx_thres = max_thres(mcbsp);
1104                 mcbsp->max_rx_thres = max_thres(mcbsp);
1105                 if (omap_thres_add(mcbsp->dev))
1106                         dev_warn(mcbsp->dev,
1107                                 "Unable to create threshold controls\n");
1108         } else {
1109                 mcbsp->max_tx_thres = -EINVAL;
1110                 mcbsp->max_rx_thres = -EINVAL;
1111         }
1112 }
1113
1114 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1115 {
1116         if (cpu_is_omap34xx())
1117                 omap_thres_remove(mcbsp->dev);
1118 }
1119 #else
1120 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1121 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1122 #endif /* CONFIG_ARCH_OMAP34XX */
1123
1124 /*
1125  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1126  * 730 has only 2 McBSP, and both of them are MPU peripherals.
1127  */
1128 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1129 {
1130         struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1131         struct omap_mcbsp *mcbsp;
1132         int id = pdev->id - 1;
1133         int ret = 0;
1134
1135         if (!pdata) {
1136                 dev_err(&pdev->dev, "McBSP device initialized without"
1137                                 "platform data\n");
1138                 ret = -EINVAL;
1139                 goto exit;
1140         }
1141
1142         dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1143
1144         if (id >= omap_mcbsp_count) {
1145                 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1146                 ret = -EINVAL;
1147                 goto exit;
1148         }
1149
1150         mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1151         if (!mcbsp) {
1152                 ret = -ENOMEM;
1153                 goto exit;
1154         }
1155
1156         spin_lock_init(&mcbsp->lock);
1157         mcbsp->id = id + 1;
1158         mcbsp->free = 1;
1159         mcbsp->dma_tx_lch = -1;
1160         mcbsp->dma_rx_lch = -1;
1161
1162         mcbsp->phys_base = pdata->phys_base;
1163         mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1164         if (!mcbsp->io_base) {
1165                 ret = -ENOMEM;
1166                 goto err_ioremap;
1167         }
1168
1169         /* Default I/O is IRQ based */
1170         mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1171         mcbsp->tx_irq = pdata->tx_irq;
1172         mcbsp->rx_irq = pdata->rx_irq;
1173         mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1174         mcbsp->dma_tx_sync = pdata->dma_tx_sync;
1175
1176         mcbsp->iclk = clk_get(&pdev->dev, "ick");
1177         if (IS_ERR(mcbsp->iclk)) {
1178                 ret = PTR_ERR(mcbsp->iclk);
1179                 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1180                 goto err_iclk;
1181         }
1182
1183         mcbsp->fclk = clk_get(&pdev->dev, "fck");
1184         if (IS_ERR(mcbsp->fclk)) {
1185                 ret = PTR_ERR(mcbsp->fclk);
1186                 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1187                 goto err_fclk;
1188         }
1189
1190         mcbsp->pdata = pdata;
1191         mcbsp->dev = &pdev->dev;
1192         mcbsp_ptr[id] = mcbsp;
1193         platform_set_drvdata(pdev, mcbsp);
1194
1195         /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1196         omap34xx_device_init(mcbsp);
1197
1198         return 0;
1199
1200 err_fclk:
1201         clk_put(mcbsp->iclk);
1202 err_iclk:
1203         iounmap(mcbsp->io_base);
1204 err_ioremap:
1205         kfree(mcbsp);
1206 exit:
1207         return ret;
1208 }
1209
1210 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1211 {
1212         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1213
1214         platform_set_drvdata(pdev, NULL);
1215         if (mcbsp) {
1216
1217                 if (mcbsp->pdata && mcbsp->pdata->ops &&
1218                                 mcbsp->pdata->ops->free)
1219                         mcbsp->pdata->ops->free(mcbsp->id);
1220
1221                 omap34xx_device_exit(mcbsp);
1222
1223                 clk_disable(mcbsp->fclk);
1224                 clk_disable(mcbsp->iclk);
1225                 clk_put(mcbsp->fclk);
1226                 clk_put(mcbsp->iclk);
1227
1228                 iounmap(mcbsp->io_base);
1229
1230                 mcbsp->fclk = NULL;
1231                 mcbsp->iclk = NULL;
1232                 mcbsp->free = 0;
1233                 mcbsp->dev = NULL;
1234         }
1235
1236         return 0;
1237 }
1238
1239 static struct platform_driver omap_mcbsp_driver = {
1240         .probe          = omap_mcbsp_probe,
1241         .remove         = __devexit_p(omap_mcbsp_remove),
1242         .driver         = {
1243                 .name   = "omap-mcbsp",
1244         },
1245 };
1246
1247 int __init omap_mcbsp_init(void)
1248 {
1249         /* Register the McBSP driver */
1250         return platform_driver_register(&omap_mcbsp_driver);
1251 }