2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
25 #include <mach/hardware.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
32 * OMAP1510 GPIO registers
34 #define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
35 #define OMAP1510_GPIO_DATA_INPUT 0x00
36 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
37 #define OMAP1510_GPIO_DIR_CONTROL 0x08
38 #define OMAP1510_GPIO_INT_CONTROL 0x0c
39 #define OMAP1510_GPIO_INT_MASK 0x10
40 #define OMAP1510_GPIO_INT_STATUS 0x14
41 #define OMAP1510_GPIO_PIN_CONTROL 0x18
43 #define OMAP1510_IH_GPIO_BASE 64
46 * OMAP1610 specific GPIO registers
48 #define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
49 #define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
50 #define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
51 #define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
52 #define OMAP1610_GPIO_REVISION 0x0000
53 #define OMAP1610_GPIO_SYSCONFIG 0x0010
54 #define OMAP1610_GPIO_SYSSTATUS 0x0014
55 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
56 #define OMAP1610_GPIO_IRQENABLE1 0x001c
57 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
58 #define OMAP1610_GPIO_DATAIN 0x002c
59 #define OMAP1610_GPIO_DATAOUT 0x0030
60 #define OMAP1610_GPIO_DIRECTION 0x0034
61 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
64 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
65 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
67 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
68 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
71 * OMAP730 specific GPIO registers
73 #define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
74 #define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
75 #define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
76 #define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
77 #define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
78 #define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
79 #define OMAP730_GPIO_DATA_INPUT 0x00
80 #define OMAP730_GPIO_DATA_OUTPUT 0x04
81 #define OMAP730_GPIO_DIR_CONTROL 0x08
82 #define OMAP730_GPIO_INT_CONTROL 0x0c
83 #define OMAP730_GPIO_INT_MASK 0x10
84 #define OMAP730_GPIO_INT_STATUS 0x14
87 * OMAP850 specific GPIO registers
89 #define OMAP850_GPIO1_BASE IO_ADDRESS(0xfffbc000)
90 #define OMAP850_GPIO2_BASE IO_ADDRESS(0xfffbc800)
91 #define OMAP850_GPIO3_BASE IO_ADDRESS(0xfffbd000)
92 #define OMAP850_GPIO4_BASE IO_ADDRESS(0xfffbd800)
93 #define OMAP850_GPIO5_BASE IO_ADDRESS(0xfffbe000)
94 #define OMAP850_GPIO6_BASE IO_ADDRESS(0xfffbe800)
95 #define OMAP850_GPIO_DATA_INPUT 0x00
96 #define OMAP850_GPIO_DATA_OUTPUT 0x04
97 #define OMAP850_GPIO_DIR_CONTROL 0x08
98 #define OMAP850_GPIO_INT_CONTROL 0x0c
99 #define OMAP850_GPIO_INT_MASK 0x10
100 #define OMAP850_GPIO_INT_STATUS 0x14
103 * omap24xx specific GPIO registers
105 #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
106 #define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
107 #define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
108 #define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
110 #define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
111 #define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
112 #define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
113 #define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
114 #define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
116 #define OMAP24XX_GPIO_REVISION 0x0000
117 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
118 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
119 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
120 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
121 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
122 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
123 #define OMAP24XX_GPIO_WAKE_EN 0x0020
124 #define OMAP24XX_GPIO_CTRL 0x0030
125 #define OMAP24XX_GPIO_OE 0x0034
126 #define OMAP24XX_GPIO_DATAIN 0x0038
127 #define OMAP24XX_GPIO_DATAOUT 0x003c
128 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
129 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
130 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
131 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
132 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
133 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
134 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
135 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
136 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
137 #define OMAP24XX_GPIO_SETWKUENA 0x0084
138 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
139 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
142 * omap34xx specific GPIO registers
145 #define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
146 #define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
147 #define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
148 #define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
149 #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
150 #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
153 * OMAP44XX specific GPIO registers
155 #define OMAP44XX_GPIO1_BASE IO_ADDRESS(0x4a310000)
156 #define OMAP44XX_GPIO2_BASE IO_ADDRESS(0x48055000)
157 #define OMAP44XX_GPIO3_BASE IO_ADDRESS(0x48057000)
158 #define OMAP44XX_GPIO4_BASE IO_ADDRESS(0x48059000)
159 #define OMAP44XX_GPIO5_BASE IO_ADDRESS(0x4805B000)
160 #define OMAP44XX_GPIO6_BASE IO_ADDRESS(0x4805D000)
162 #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
167 u16 virtual_irq_start;
169 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
170 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
174 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
175 defined(CONFIG_ARCH_OMAP4)
176 u32 non_wakeup_gpios;
177 u32 enabled_non_wakeup_gpios;
180 u32 saved_fallingdetect;
181 u32 saved_risingdetect;
185 struct gpio_chip chip;
189 #define METHOD_MPUIO 0
190 #define METHOD_GPIO_1510 1
191 #define METHOD_GPIO_1610 2
192 #define METHOD_GPIO_730 3
193 #define METHOD_GPIO_850 4
194 #define METHOD_GPIO_24XX 5
196 #ifdef CONFIG_ARCH_OMAP16XX
197 static struct gpio_bank gpio_bank_1610[5] = {
198 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
199 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
200 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
201 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
202 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
206 #ifdef CONFIG_ARCH_OMAP15XX
207 static struct gpio_bank gpio_bank_1510[2] = {
208 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
209 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
213 #ifdef CONFIG_ARCH_OMAP730
214 static struct gpio_bank gpio_bank_730[7] = {
215 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
216 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
217 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
218 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
219 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
220 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
221 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
225 #ifdef CONFIG_ARCH_OMAP850
226 static struct gpio_bank gpio_bank_850[7] = {
227 { OMAP_MPUIO_BASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
228 { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 },
229 { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 },
230 { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 },
231 { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_850 },
232 { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_850 },
233 { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_850 },
238 #ifdef CONFIG_ARCH_OMAP24XX
240 static struct gpio_bank gpio_bank_242x[4] = {
241 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
242 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
243 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
244 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
247 static struct gpio_bank gpio_bank_243x[5] = {
248 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
249 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
250 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
251 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
252 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
257 #ifdef CONFIG_ARCH_OMAP34XX
258 static struct gpio_bank gpio_bank_34xx[6] = {
259 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
260 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
261 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
262 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
263 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
264 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
269 #ifdef CONFIG_ARCH_OMAP4
270 static struct gpio_bank gpio_bank_44xx[6] = {
271 { OMAP44XX_GPIO1_BASE, INT_44XX_GPIO_BANK1, IH_GPIO_BASE, \
273 { OMAP44XX_GPIO2_BASE, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32, \
275 { OMAP44XX_GPIO3_BASE, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64, \
277 { OMAP44XX_GPIO4_BASE, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96, \
279 { OMAP44XX_GPIO5_BASE, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, \
281 { OMAP44XX_GPIO6_BASE, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, \
287 static struct gpio_bank *gpio_bank;
288 static int gpio_bank_count;
290 static inline struct gpio_bank *get_gpio_bank(int gpio)
292 if (cpu_is_omap15xx()) {
293 if (OMAP_GPIO_IS_MPUIO(gpio))
294 return &gpio_bank[0];
295 return &gpio_bank[1];
297 if (cpu_is_omap16xx()) {
298 if (OMAP_GPIO_IS_MPUIO(gpio))
299 return &gpio_bank[0];
300 return &gpio_bank[1 + (gpio >> 4)];
302 if (cpu_is_omap7xx()) {
303 if (OMAP_GPIO_IS_MPUIO(gpio))
304 return &gpio_bank[0];
305 return &gpio_bank[1 + (gpio >> 5)];
307 if (cpu_is_omap24xx())
308 return &gpio_bank[gpio >> 5];
309 if (cpu_is_omap34xx() || cpu_is_omap44xx())
310 return &gpio_bank[gpio >> 5];
315 static inline int get_gpio_index(int gpio)
317 if (cpu_is_omap7xx())
319 if (cpu_is_omap24xx())
321 if (cpu_is_omap34xx() || cpu_is_omap44xx())
326 static inline int gpio_valid(int gpio)
330 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
331 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
335 if (cpu_is_omap15xx() && gpio < 16)
337 if ((cpu_is_omap16xx()) && gpio < 64)
339 if (cpu_is_omap7xx() && gpio < 192)
341 if (cpu_is_omap24xx() && gpio < 128)
343 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
348 static int check_gpio(int gpio)
350 if (unlikely(gpio_valid(gpio)) < 0) {
351 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
358 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
360 void __iomem *reg = bank->base;
363 switch (bank->method) {
364 #ifdef CONFIG_ARCH_OMAP1
366 reg += OMAP_MPUIO_IO_CNTL;
369 #ifdef CONFIG_ARCH_OMAP15XX
370 case METHOD_GPIO_1510:
371 reg += OMAP1510_GPIO_DIR_CONTROL;
374 #ifdef CONFIG_ARCH_OMAP16XX
375 case METHOD_GPIO_1610:
376 reg += OMAP1610_GPIO_DIRECTION;
379 #ifdef CONFIG_ARCH_OMAP730
380 case METHOD_GPIO_730:
381 reg += OMAP730_GPIO_DIR_CONTROL;
384 #ifdef CONFIG_ARCH_OMAP850
385 case METHOD_GPIO_850:
386 reg += OMAP850_GPIO_DIR_CONTROL;
389 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
390 defined(CONFIG_ARCH_OMAP4)
391 case METHOD_GPIO_24XX:
392 reg += OMAP24XX_GPIO_OE;
399 l = __raw_readl(reg);
404 __raw_writel(l, reg);
407 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
409 void __iomem *reg = bank->base;
412 switch (bank->method) {
413 #ifdef CONFIG_ARCH_OMAP1
415 reg += OMAP_MPUIO_OUTPUT;
416 l = __raw_readl(reg);
423 #ifdef CONFIG_ARCH_OMAP15XX
424 case METHOD_GPIO_1510:
425 reg += OMAP1510_GPIO_DATA_OUTPUT;
426 l = __raw_readl(reg);
433 #ifdef CONFIG_ARCH_OMAP16XX
434 case METHOD_GPIO_1610:
436 reg += OMAP1610_GPIO_SET_DATAOUT;
438 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
442 #ifdef CONFIG_ARCH_OMAP730
443 case METHOD_GPIO_730:
444 reg += OMAP730_GPIO_DATA_OUTPUT;
445 l = __raw_readl(reg);
452 #ifdef CONFIG_ARCH_OMAP850
453 case METHOD_GPIO_850:
454 reg += OMAP850_GPIO_DATA_OUTPUT;
455 l = __raw_readl(reg);
462 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
463 defined(CONFIG_ARCH_OMAP4)
464 case METHOD_GPIO_24XX:
466 reg += OMAP24XX_GPIO_SETDATAOUT;
468 reg += OMAP24XX_GPIO_CLEARDATAOUT;
476 __raw_writel(l, reg);
479 static int __omap_get_gpio_datain(int gpio)
481 struct gpio_bank *bank;
484 if (check_gpio(gpio) < 0)
486 bank = get_gpio_bank(gpio);
488 switch (bank->method) {
489 #ifdef CONFIG_ARCH_OMAP1
491 reg += OMAP_MPUIO_INPUT_LATCH;
494 #ifdef CONFIG_ARCH_OMAP15XX
495 case METHOD_GPIO_1510:
496 reg += OMAP1510_GPIO_DATA_INPUT;
499 #ifdef CONFIG_ARCH_OMAP16XX
500 case METHOD_GPIO_1610:
501 reg += OMAP1610_GPIO_DATAIN;
504 #ifdef CONFIG_ARCH_OMAP730
505 case METHOD_GPIO_730:
506 reg += OMAP730_GPIO_DATA_INPUT;
509 #ifdef CONFIG_ARCH_OMAP850
510 case METHOD_GPIO_850:
511 reg += OMAP850_GPIO_DATA_INPUT;
514 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
515 defined(CONFIG_ARCH_OMAP4)
516 case METHOD_GPIO_24XX:
517 reg += OMAP24XX_GPIO_DATAIN;
523 return (__raw_readl(reg)
524 & (1 << get_gpio_index(gpio))) != 0;
527 #define MOD_REG_BIT(reg, bit_mask, set) \
529 int l = __raw_readl(base + reg); \
530 if (set) l |= bit_mask; \
531 else l &= ~bit_mask; \
532 __raw_writel(l, base + reg); \
535 void omap_set_gpio_debounce(int gpio, int enable)
537 struct gpio_bank *bank;
540 u32 val, l = 1 << get_gpio_index(gpio);
542 if (cpu_class_is_omap1())
545 bank = get_gpio_bank(gpio);
547 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
549 spin_lock_irqsave(&bank->lock, flags);
550 val = __raw_readl(reg);
552 if (enable && !(val & l))
554 else if (!enable && (val & l))
559 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
561 clk_enable(bank->dbck);
563 clk_disable(bank->dbck);
566 __raw_writel(val, reg);
568 spin_unlock_irqrestore(&bank->lock, flags);
570 EXPORT_SYMBOL(omap_set_gpio_debounce);
572 void omap_set_gpio_debounce_time(int gpio, int enc_time)
574 struct gpio_bank *bank;
577 if (cpu_class_is_omap1())
580 bank = get_gpio_bank(gpio);
584 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
585 __raw_writel(enc_time, reg);
587 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
589 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
590 defined(CONFIG_ARCH_OMAP4)
591 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
594 void __iomem *base = bank->base;
595 u32 gpio_bit = 1 << gpio;
597 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
598 trigger & IRQ_TYPE_LEVEL_LOW);
599 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
600 trigger & IRQ_TYPE_LEVEL_HIGH);
601 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
602 trigger & IRQ_TYPE_EDGE_RISING);
603 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
604 trigger & IRQ_TYPE_EDGE_FALLING);
606 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
608 __raw_writel(1 << gpio, bank->base
609 + OMAP24XX_GPIO_SETWKUENA);
611 __raw_writel(1 << gpio, bank->base
612 + OMAP24XX_GPIO_CLEARWKUENA);
615 bank->enabled_non_wakeup_gpios |= gpio_bit;
617 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
621 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
622 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
626 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
628 void __iomem *reg = bank->base;
631 switch (bank->method) {
632 #ifdef CONFIG_ARCH_OMAP1
634 reg += OMAP_MPUIO_GPIO_INT_EDGE;
635 l = __raw_readl(reg);
636 if (trigger & IRQ_TYPE_EDGE_RISING)
638 else if (trigger & IRQ_TYPE_EDGE_FALLING)
644 #ifdef CONFIG_ARCH_OMAP15XX
645 case METHOD_GPIO_1510:
646 reg += OMAP1510_GPIO_INT_CONTROL;
647 l = __raw_readl(reg);
648 if (trigger & IRQ_TYPE_EDGE_RISING)
650 else if (trigger & IRQ_TYPE_EDGE_FALLING)
656 #ifdef CONFIG_ARCH_OMAP16XX
657 case METHOD_GPIO_1610:
659 reg += OMAP1610_GPIO_EDGE_CTRL2;
661 reg += OMAP1610_GPIO_EDGE_CTRL1;
663 l = __raw_readl(reg);
664 l &= ~(3 << (gpio << 1));
665 if (trigger & IRQ_TYPE_EDGE_RISING)
666 l |= 2 << (gpio << 1);
667 if (trigger & IRQ_TYPE_EDGE_FALLING)
668 l |= 1 << (gpio << 1);
670 /* Enable wake-up during idle for dynamic tick */
671 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
673 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
676 #ifdef CONFIG_ARCH_OMAP730
677 case METHOD_GPIO_730:
678 reg += OMAP730_GPIO_INT_CONTROL;
679 l = __raw_readl(reg);
680 if (trigger & IRQ_TYPE_EDGE_RISING)
682 else if (trigger & IRQ_TYPE_EDGE_FALLING)
688 #ifdef CONFIG_ARCH_OMAP850
689 case METHOD_GPIO_850:
690 reg += OMAP850_GPIO_INT_CONTROL;
691 l = __raw_readl(reg);
692 if (trigger & IRQ_TYPE_EDGE_RISING)
694 else if (trigger & IRQ_TYPE_EDGE_FALLING)
700 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
701 defined(CONFIG_ARCH_OMAP4)
702 case METHOD_GPIO_24XX:
703 set_24xx_gpio_triggering(bank, gpio, trigger);
709 __raw_writel(l, reg);
715 static int gpio_irq_type(unsigned irq, unsigned type)
717 struct gpio_bank *bank;
722 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
723 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
725 gpio = irq - IH_GPIO_BASE;
727 if (check_gpio(gpio) < 0)
730 if (type & ~IRQ_TYPE_SENSE_MASK)
733 /* OMAP1 allows only only edge triggering */
734 if (!cpu_class_is_omap2()
735 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
738 bank = get_irq_chip_data(irq);
739 spin_lock_irqsave(&bank->lock, flags);
740 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
742 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
743 irq_desc[irq].status |= type;
745 spin_unlock_irqrestore(&bank->lock, flags);
747 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
748 __set_irq_handler_unlocked(irq, handle_level_irq);
749 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
750 __set_irq_handler_unlocked(irq, handle_edge_irq);
755 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
757 void __iomem *reg = bank->base;
759 switch (bank->method) {
760 #ifdef CONFIG_ARCH_OMAP1
762 /* MPUIO irqstatus is reset by reading the status register,
763 * so do nothing here */
766 #ifdef CONFIG_ARCH_OMAP15XX
767 case METHOD_GPIO_1510:
768 reg += OMAP1510_GPIO_INT_STATUS;
771 #ifdef CONFIG_ARCH_OMAP16XX
772 case METHOD_GPIO_1610:
773 reg += OMAP1610_GPIO_IRQSTATUS1;
776 #ifdef CONFIG_ARCH_OMAP730
777 case METHOD_GPIO_730:
778 reg += OMAP730_GPIO_INT_STATUS;
781 #ifdef CONFIG_ARCH_OMAP850
782 case METHOD_GPIO_850:
783 reg += OMAP850_GPIO_INT_STATUS;
786 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
787 defined(CONFIG_ARCH_OMAP4)
788 case METHOD_GPIO_24XX:
789 reg += OMAP24XX_GPIO_IRQSTATUS1;
796 __raw_writel(gpio_mask, reg);
798 /* Workaround for clearing DSP GPIO interrupts to allow retention */
799 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
800 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
801 if (cpu_is_omap24xx() || cpu_is_omap34xx())
802 __raw_writel(gpio_mask, reg);
804 /* Flush posted write for the irq status to avoid spurious interrupts */
809 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
811 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
814 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
816 void __iomem *reg = bank->base;
821 switch (bank->method) {
822 #ifdef CONFIG_ARCH_OMAP1
824 reg += OMAP_MPUIO_GPIO_MASKIT;
829 #ifdef CONFIG_ARCH_OMAP15XX
830 case METHOD_GPIO_1510:
831 reg += OMAP1510_GPIO_INT_MASK;
836 #ifdef CONFIG_ARCH_OMAP16XX
837 case METHOD_GPIO_1610:
838 reg += OMAP1610_GPIO_IRQENABLE1;
842 #ifdef CONFIG_ARCH_OMAP730
843 case METHOD_GPIO_730:
844 reg += OMAP730_GPIO_INT_MASK;
849 #ifdef CONFIG_ARCH_OMAP850
850 case METHOD_GPIO_850:
851 reg += OMAP850_GPIO_INT_MASK;
856 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
857 defined(CONFIG_ARCH_OMAP4)
858 case METHOD_GPIO_24XX:
859 reg += OMAP24XX_GPIO_IRQENABLE1;
868 l = __raw_readl(reg);
875 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
877 void __iomem *reg = bank->base;
880 switch (bank->method) {
881 #ifdef CONFIG_ARCH_OMAP1
883 reg += OMAP_MPUIO_GPIO_MASKIT;
884 l = __raw_readl(reg);
891 #ifdef CONFIG_ARCH_OMAP15XX
892 case METHOD_GPIO_1510:
893 reg += OMAP1510_GPIO_INT_MASK;
894 l = __raw_readl(reg);
901 #ifdef CONFIG_ARCH_OMAP16XX
902 case METHOD_GPIO_1610:
904 reg += OMAP1610_GPIO_SET_IRQENABLE1;
906 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
910 #ifdef CONFIG_ARCH_OMAP730
911 case METHOD_GPIO_730:
912 reg += OMAP730_GPIO_INT_MASK;
913 l = __raw_readl(reg);
920 #ifdef CONFIG_ARCH_OMAP850
921 case METHOD_GPIO_850:
922 reg += OMAP850_GPIO_INT_MASK;
923 l = __raw_readl(reg);
930 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
931 defined(CONFIG_ARCH_OMAP4)
932 case METHOD_GPIO_24XX:
934 reg += OMAP24XX_GPIO_SETIRQENABLE1;
936 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
944 __raw_writel(l, reg);
947 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
949 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
953 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
954 * 1510 does not seem to have a wake-up register. If JTAG is connected
955 * to the target, system will wake up always on GPIO events. While
956 * system is running all registered GPIO interrupts need to have wake-up
957 * enabled. When system is suspended, only selected GPIO interrupts need
958 * to have wake-up enabled.
960 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
964 switch (bank->method) {
965 #ifdef CONFIG_ARCH_OMAP16XX
967 case METHOD_GPIO_1610:
968 spin_lock_irqsave(&bank->lock, flags);
970 bank->suspend_wakeup |= (1 << gpio);
972 bank->suspend_wakeup &= ~(1 << gpio);
973 spin_unlock_irqrestore(&bank->lock, flags);
976 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
977 defined(CONFIG_ARCH_OMAP4)
978 case METHOD_GPIO_24XX:
979 if (bank->non_wakeup_gpios & (1 << gpio)) {
980 printk(KERN_ERR "Unable to modify wakeup on "
981 "non-wakeup GPIO%d\n",
982 (bank - gpio_bank) * 32 + gpio);
985 spin_lock_irqsave(&bank->lock, flags);
987 bank->suspend_wakeup |= (1 << gpio);
989 bank->suspend_wakeup &= ~(1 << gpio);
990 spin_unlock_irqrestore(&bank->lock, flags);
994 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1000 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1002 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1003 _set_gpio_irqenable(bank, gpio, 0);
1004 _clear_gpio_irqstatus(bank, gpio);
1005 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1008 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1009 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1011 unsigned int gpio = irq - IH_GPIO_BASE;
1012 struct gpio_bank *bank;
1015 if (check_gpio(gpio) < 0)
1017 bank = get_irq_chip_data(irq);
1018 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1023 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1025 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1026 unsigned long flags;
1028 spin_lock_irqsave(&bank->lock, flags);
1030 /* Set trigger to none. You need to enable the desired trigger with
1031 * request_irq() or set_irq_type().
1033 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1035 #ifdef CONFIG_ARCH_OMAP15XX
1036 if (bank->method == METHOD_GPIO_1510) {
1039 /* Claim the pin for MPU */
1040 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1041 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1044 spin_unlock_irqrestore(&bank->lock, flags);
1049 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1051 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1052 unsigned long flags;
1054 spin_lock_irqsave(&bank->lock, flags);
1055 #ifdef CONFIG_ARCH_OMAP16XX
1056 if (bank->method == METHOD_GPIO_1610) {
1057 /* Disable wake-up during idle for dynamic tick */
1058 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1059 __raw_writel(1 << offset, reg);
1062 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1063 defined(CONFIG_ARCH_OMAP4)
1064 if (bank->method == METHOD_GPIO_24XX) {
1065 /* Disable wake-up during idle for dynamic tick */
1066 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1067 __raw_writel(1 << offset, reg);
1070 _reset_gpio(bank, bank->chip.base + offset);
1071 spin_unlock_irqrestore(&bank->lock, flags);
1075 * We need to unmask the GPIO bank interrupt as soon as possible to
1076 * avoid missing GPIO interrupts for other lines in the bank.
1077 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1078 * in the bank to avoid missing nested interrupts for a GPIO line.
1079 * If we wait to unmask individual GPIO lines in the bank after the
1080 * line's interrupt handler has been run, we may miss some nested
1083 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1085 void __iomem *isr_reg = NULL;
1087 unsigned int gpio_irq;
1088 struct gpio_bank *bank;
1092 desc->chip->ack(irq);
1094 bank = get_irq_data(irq);
1095 #ifdef CONFIG_ARCH_OMAP1
1096 if (bank->method == METHOD_MPUIO)
1097 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1099 #ifdef CONFIG_ARCH_OMAP15XX
1100 if (bank->method == METHOD_GPIO_1510)
1101 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1103 #if defined(CONFIG_ARCH_OMAP16XX)
1104 if (bank->method == METHOD_GPIO_1610)
1105 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1107 #ifdef CONFIG_ARCH_OMAP730
1108 if (bank->method == METHOD_GPIO_730)
1109 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1111 #ifdef CONFIG_ARCH_OMAP850
1112 if (bank->method == METHOD_GPIO_850)
1113 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
1115 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1116 defined(CONFIG_ARCH_OMAP4)
1117 if (bank->method == METHOD_GPIO_24XX)
1118 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1121 u32 isr_saved, level_mask = 0;
1124 enabled = _get_gpio_irqbank_mask(bank);
1125 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1127 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1130 if (cpu_class_is_omap2()) {
1131 level_mask = bank->level_mask & enabled;
1134 /* clear edge sensitive interrupts before handler(s) are
1135 called so that we don't miss any interrupt occurred while
1137 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1138 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1139 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1141 /* if there is only edge sensitive GPIO pin interrupts
1142 configured, we could unmask GPIO bank interrupt immediately */
1143 if (!level_mask && !unmasked) {
1145 desc->chip->unmask(irq);
1153 gpio_irq = bank->virtual_irq_start;
1154 for (; isr != 0; isr >>= 1, gpio_irq++) {
1158 generic_handle_irq(gpio_irq);
1161 /* if bank has any level sensitive GPIO pin interrupt
1162 configured, we must unmask the bank interrupt only after
1163 handler(s) are executed in order to avoid spurious bank
1166 desc->chip->unmask(irq);
1170 static void gpio_irq_shutdown(unsigned int irq)
1172 unsigned int gpio = irq - IH_GPIO_BASE;
1173 struct gpio_bank *bank = get_irq_chip_data(irq);
1175 _reset_gpio(bank, gpio);
1178 static void gpio_ack_irq(unsigned int irq)
1180 unsigned int gpio = irq - IH_GPIO_BASE;
1181 struct gpio_bank *bank = get_irq_chip_data(irq);
1183 _clear_gpio_irqstatus(bank, gpio);
1186 static void gpio_mask_irq(unsigned int irq)
1188 unsigned int gpio = irq - IH_GPIO_BASE;
1189 struct gpio_bank *bank = get_irq_chip_data(irq);
1191 _set_gpio_irqenable(bank, gpio, 0);
1192 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1195 static void gpio_unmask_irq(unsigned int irq)
1197 unsigned int gpio = irq - IH_GPIO_BASE;
1198 struct gpio_bank *bank = get_irq_chip_data(irq);
1199 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1200 struct irq_desc *desc = irq_to_desc(irq);
1201 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1204 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1206 /* For level-triggered GPIOs, the clearing must be done after
1207 * the HW source is cleared, thus after the handler has run */
1208 if (bank->level_mask & irq_mask) {
1209 _set_gpio_irqenable(bank, gpio, 0);
1210 _clear_gpio_irqstatus(bank, gpio);
1213 _set_gpio_irqenable(bank, gpio, 1);
1216 static struct irq_chip gpio_irq_chip = {
1218 .shutdown = gpio_irq_shutdown,
1219 .ack = gpio_ack_irq,
1220 .mask = gpio_mask_irq,
1221 .unmask = gpio_unmask_irq,
1222 .set_type = gpio_irq_type,
1223 .set_wake = gpio_wake_enable,
1226 /*---------------------------------------------------------------------*/
1228 #ifdef CONFIG_ARCH_OMAP1
1230 /* MPUIO uses the always-on 32k clock */
1232 static void mpuio_ack_irq(unsigned int irq)
1234 /* The ISR is reset automatically, so do nothing here. */
1237 static void mpuio_mask_irq(unsigned int irq)
1239 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1240 struct gpio_bank *bank = get_irq_chip_data(irq);
1242 _set_gpio_irqenable(bank, gpio, 0);
1245 static void mpuio_unmask_irq(unsigned int irq)
1247 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1248 struct gpio_bank *bank = get_irq_chip_data(irq);
1250 _set_gpio_irqenable(bank, gpio, 1);
1253 static struct irq_chip mpuio_irq_chip = {
1255 .ack = mpuio_ack_irq,
1256 .mask = mpuio_mask_irq,
1257 .unmask = mpuio_unmask_irq,
1258 .set_type = gpio_irq_type,
1259 #ifdef CONFIG_ARCH_OMAP16XX
1260 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1261 .set_wake = gpio_wake_enable,
1266 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1269 #ifdef CONFIG_ARCH_OMAP16XX
1271 #include <linux/platform_device.h>
1273 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1275 struct gpio_bank *bank = platform_get_drvdata(pdev);
1276 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1277 unsigned long flags;
1279 spin_lock_irqsave(&bank->lock, flags);
1280 bank->saved_wakeup = __raw_readl(mask_reg);
1281 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1282 spin_unlock_irqrestore(&bank->lock, flags);
1287 static int omap_mpuio_resume_early(struct platform_device *pdev)
1289 struct gpio_bank *bank = platform_get_drvdata(pdev);
1290 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1291 unsigned long flags;
1293 spin_lock_irqsave(&bank->lock, flags);
1294 __raw_writel(bank->saved_wakeup, mask_reg);
1295 spin_unlock_irqrestore(&bank->lock, flags);
1300 /* use platform_driver for this, now that there's no longer any
1301 * point to sys_device (other than not disturbing old code).
1303 static struct platform_driver omap_mpuio_driver = {
1304 .suspend_late = omap_mpuio_suspend_late,
1305 .resume_early = omap_mpuio_resume_early,
1311 static struct platform_device omap_mpuio_device = {
1315 .driver = &omap_mpuio_driver.driver,
1317 /* could list the /proc/iomem resources */
1320 static inline void mpuio_init(void)
1322 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1324 if (platform_driver_register(&omap_mpuio_driver) == 0)
1325 (void) platform_device_register(&omap_mpuio_device);
1329 static inline void mpuio_init(void) {}
1334 extern struct irq_chip mpuio_irq_chip;
1336 #define bank_is_mpuio(bank) 0
1337 static inline void mpuio_init(void) {}
1341 /*---------------------------------------------------------------------*/
1343 /* REVISIT these are stupid implementations! replace by ones that
1344 * don't switch on METHOD_* and which mostly avoid spinlocks
1347 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1349 struct gpio_bank *bank;
1350 unsigned long flags;
1352 bank = container_of(chip, struct gpio_bank, chip);
1353 spin_lock_irqsave(&bank->lock, flags);
1354 _set_gpio_direction(bank, offset, 1);
1355 spin_unlock_irqrestore(&bank->lock, flags);
1359 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1361 return __omap_get_gpio_datain(chip->base + offset);
1364 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1366 struct gpio_bank *bank;
1367 unsigned long flags;
1369 bank = container_of(chip, struct gpio_bank, chip);
1370 spin_lock_irqsave(&bank->lock, flags);
1371 _set_gpio_dataout(bank, offset, value);
1372 _set_gpio_direction(bank, offset, 0);
1373 spin_unlock_irqrestore(&bank->lock, flags);
1377 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1379 struct gpio_bank *bank;
1380 unsigned long flags;
1382 bank = container_of(chip, struct gpio_bank, chip);
1383 spin_lock_irqsave(&bank->lock, flags);
1384 _set_gpio_dataout(bank, offset, value);
1385 spin_unlock_irqrestore(&bank->lock, flags);
1388 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1390 struct gpio_bank *bank;
1392 bank = container_of(chip, struct gpio_bank, chip);
1393 return bank->virtual_irq_start + offset;
1396 /*---------------------------------------------------------------------*/
1398 static int initialized;
1399 #if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4))
1400 static struct clk * gpio_ick;
1403 #if defined(CONFIG_ARCH_OMAP2)
1404 static struct clk * gpio_fck;
1407 #if defined(CONFIG_ARCH_OMAP2430)
1408 static struct clk * gpio5_ick;
1409 static struct clk * gpio5_fck;
1412 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1413 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1416 /* This lock class tells lockdep that GPIO irqs are in a different
1417 * category than their parents, so it won't report false recursion.
1419 static struct lock_class_key gpio_lock_class;
1421 static int __init _omap_gpio_init(void)
1425 struct gpio_bank *bank;
1430 #if defined(CONFIG_ARCH_OMAP1)
1431 if (cpu_is_omap15xx()) {
1432 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1433 if (IS_ERR(gpio_ick))
1434 printk("Could not get arm_gpio_ck\n");
1436 clk_enable(gpio_ick);
1439 #if defined(CONFIG_ARCH_OMAP2)
1440 if (cpu_class_is_omap2()) {
1441 gpio_ick = clk_get(NULL, "gpios_ick");
1442 if (IS_ERR(gpio_ick))
1443 printk("Could not get gpios_ick\n");
1445 clk_enable(gpio_ick);
1446 gpio_fck = clk_get(NULL, "gpios_fck");
1447 if (IS_ERR(gpio_fck))
1448 printk("Could not get gpios_fck\n");
1450 clk_enable(gpio_fck);
1453 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1455 #if defined(CONFIG_ARCH_OMAP2430)
1456 if (cpu_is_omap2430()) {
1457 gpio5_ick = clk_get(NULL, "gpio5_ick");
1458 if (IS_ERR(gpio5_ick))
1459 printk("Could not get gpio5_ick\n");
1461 clk_enable(gpio5_ick);
1462 gpio5_fck = clk_get(NULL, "gpio5_fck");
1463 if (IS_ERR(gpio5_fck))
1464 printk("Could not get gpio5_fck\n");
1466 clk_enable(gpio5_fck);
1472 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1473 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1474 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1475 sprintf(clk_name, "gpio%d_ick", i + 1);
1476 gpio_iclks[i] = clk_get(NULL, clk_name);
1477 if (IS_ERR(gpio_iclks[i]))
1478 printk(KERN_ERR "Could not get %s\n", clk_name);
1480 clk_enable(gpio_iclks[i]);
1486 #ifdef CONFIG_ARCH_OMAP15XX
1487 if (cpu_is_omap15xx()) {
1488 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1489 gpio_bank_count = 2;
1490 gpio_bank = gpio_bank_1510;
1493 #if defined(CONFIG_ARCH_OMAP16XX)
1494 if (cpu_is_omap16xx()) {
1497 gpio_bank_count = 5;
1498 gpio_bank = gpio_bank_1610;
1499 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1500 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1501 (rev >> 4) & 0x0f, rev & 0x0f);
1504 #ifdef CONFIG_ARCH_OMAP730
1505 if (cpu_is_omap730()) {
1506 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1507 gpio_bank_count = 7;
1508 gpio_bank = gpio_bank_730;
1511 #ifdef CONFIG_ARCH_OMAP850
1512 if (cpu_is_omap850()) {
1513 printk(KERN_INFO "OMAP850 GPIO hardware\n");
1514 gpio_bank_count = 7;
1515 gpio_bank = gpio_bank_850;
1519 #ifdef CONFIG_ARCH_OMAP24XX
1520 if (cpu_is_omap242x()) {
1523 gpio_bank_count = 4;
1524 gpio_bank = gpio_bank_242x;
1525 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1526 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1527 (rev >> 4) & 0x0f, rev & 0x0f);
1529 if (cpu_is_omap243x()) {
1532 gpio_bank_count = 5;
1533 gpio_bank = gpio_bank_243x;
1534 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1535 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1536 (rev >> 4) & 0x0f, rev & 0x0f);
1539 #ifdef CONFIG_ARCH_OMAP34XX
1540 if (cpu_is_omap34xx()) {
1543 gpio_bank_count = OMAP34XX_NR_GPIOS;
1544 gpio_bank = gpio_bank_34xx;
1545 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1546 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1547 (rev >> 4) & 0x0f, rev & 0x0f);
1550 #ifdef CONFIG_ARCH_OMAP4
1551 if (cpu_is_omap44xx()) {
1554 gpio_bank_count = OMAP34XX_NR_GPIOS;
1555 gpio_bank = gpio_bank_44xx;
1556 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1557 printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
1558 (rev >> 4) & 0x0f, rev & 0x0f);
1561 for (i = 0; i < gpio_bank_count; i++) {
1562 int j, gpio_count = 16;
1564 bank = &gpio_bank[i];
1565 spin_lock_init(&bank->lock);
1566 if (bank_is_mpuio(bank))
1567 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1568 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1569 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1570 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1572 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1573 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1574 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1575 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1577 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) {
1578 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1579 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1581 gpio_count = 32; /* 730 has 32-bit GPIOs */
1584 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1585 defined(CONFIG_ARCH_OMAP4)
1586 if (bank->method == METHOD_GPIO_24XX) {
1587 static const u32 non_wakeup_gpios[] = {
1588 0xe203ffc0, 0x08700040
1591 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1592 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1593 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1594 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
1596 /* Initialize interface clock ungated, module enabled */
1597 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1598 if (i < ARRAY_SIZE(non_wakeup_gpios))
1599 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1604 /* REVISIT eventually switch from OMAP-specific gpio structs
1605 * over to the generic ones
1607 bank->chip.request = omap_gpio_request;
1608 bank->chip.free = omap_gpio_free;
1609 bank->chip.direction_input = gpio_input;
1610 bank->chip.get = gpio_get;
1611 bank->chip.direction_output = gpio_output;
1612 bank->chip.set = gpio_set;
1613 bank->chip.to_irq = gpio_2irq;
1614 if (bank_is_mpuio(bank)) {
1615 bank->chip.label = "mpuio";
1616 #ifdef CONFIG_ARCH_OMAP16XX
1617 bank->chip.dev = &omap_mpuio_device.dev;
1619 bank->chip.base = OMAP_MPUIO(0);
1621 bank->chip.label = "gpio";
1622 bank->chip.base = gpio;
1625 bank->chip.ngpio = gpio_count;
1627 gpiochip_add(&bank->chip);
1629 for (j = bank->virtual_irq_start;
1630 j < bank->virtual_irq_start + gpio_count; j++) {
1631 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1632 set_irq_chip_data(j, bank);
1633 if (bank_is_mpuio(bank))
1634 set_irq_chip(j, &mpuio_irq_chip);
1636 set_irq_chip(j, &gpio_irq_chip);
1637 set_irq_handler(j, handle_simple_irq);
1638 set_irq_flags(j, IRQF_VALID);
1640 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1641 set_irq_data(bank->irq, bank);
1643 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1644 sprintf(clk_name, "gpio%d_dbck", i + 1);
1645 bank->dbck = clk_get(NULL, clk_name);
1646 if (IS_ERR(bank->dbck))
1647 printk(KERN_ERR "Could not get %s\n", clk_name);
1651 /* Enable system clock for GPIO module.
1652 * The CAM_CLK_CTRL *is* really the right place. */
1653 if (cpu_is_omap16xx())
1654 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1656 /* Enable autoidle for the OCP interface */
1657 if (cpu_is_omap24xx())
1658 omap_writel(1 << 0, 0x48019010);
1659 if (cpu_is_omap34xx())
1660 omap_writel(1 << 0, 0x48306814);
1665 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1666 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
1667 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1671 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1674 for (i = 0; i < gpio_bank_count; i++) {
1675 struct gpio_bank *bank = &gpio_bank[i];
1676 void __iomem *wake_status;
1677 void __iomem *wake_clear;
1678 void __iomem *wake_set;
1679 unsigned long flags;
1681 switch (bank->method) {
1682 #ifdef CONFIG_ARCH_OMAP16XX
1683 case METHOD_GPIO_1610:
1684 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1685 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1686 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1689 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1690 defined(CONFIG_ARCH_OMAP4)
1691 case METHOD_GPIO_24XX:
1692 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1693 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1694 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1701 spin_lock_irqsave(&bank->lock, flags);
1702 bank->saved_wakeup = __raw_readl(wake_status);
1703 __raw_writel(0xffffffff, wake_clear);
1704 __raw_writel(bank->suspend_wakeup, wake_set);
1705 spin_unlock_irqrestore(&bank->lock, flags);
1711 static int omap_gpio_resume(struct sys_device *dev)
1715 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1718 for (i = 0; i < gpio_bank_count; i++) {
1719 struct gpio_bank *bank = &gpio_bank[i];
1720 void __iomem *wake_clear;
1721 void __iomem *wake_set;
1722 unsigned long flags;
1724 switch (bank->method) {
1725 #ifdef CONFIG_ARCH_OMAP16XX
1726 case METHOD_GPIO_1610:
1727 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1728 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1731 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1732 defined(CONFIG_ARCH_OMAP4)
1733 case METHOD_GPIO_24XX:
1734 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1735 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1742 spin_lock_irqsave(&bank->lock, flags);
1743 __raw_writel(0xffffffff, wake_clear);
1744 __raw_writel(bank->saved_wakeup, wake_set);
1745 spin_unlock_irqrestore(&bank->lock, flags);
1751 static struct sysdev_class omap_gpio_sysclass = {
1753 .suspend = omap_gpio_suspend,
1754 .resume = omap_gpio_resume,
1757 static struct sys_device omap_gpio_device = {
1759 .cls = &omap_gpio_sysclass,
1764 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1765 defined(CONFIG_ARCH_OMAP4)
1767 static int workaround_enabled;
1769 void omap2_gpio_prepare_for_retention(void)
1773 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1774 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1775 for (i = 0; i < gpio_bank_count; i++) {
1776 struct gpio_bank *bank = &gpio_bank[i];
1779 if (!(bank->enabled_non_wakeup_gpios))
1781 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1782 defined(CONFIG_ARCH_OMAP4)
1783 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1784 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1785 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1787 bank->saved_fallingdetect = l1;
1788 bank->saved_risingdetect = l2;
1789 l1 &= ~bank->enabled_non_wakeup_gpios;
1790 l2 &= ~bank->enabled_non_wakeup_gpios;
1791 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1792 defined(CONFIG_ARCH_OMAP4)
1793 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1794 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1799 workaround_enabled = 0;
1802 workaround_enabled = 1;
1805 void omap2_gpio_resume_after_retention(void)
1809 if (!workaround_enabled)
1811 for (i = 0; i < gpio_bank_count; i++) {
1812 struct gpio_bank *bank = &gpio_bank[i];
1815 if (!(bank->enabled_non_wakeup_gpios))
1817 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1818 defined(CONFIG_ARCH_OMAP4)
1819 __raw_writel(bank->saved_fallingdetect,
1820 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1821 __raw_writel(bank->saved_risingdetect,
1822 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1824 /* Check if any of the non-wakeup interrupt GPIOs have changed
1825 * state. If so, generate an IRQ by software. This is
1826 * horribly racy, but it's the best we can do to work around
1827 * this silicon bug. */
1828 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1829 defined(CONFIG_ARCH_OMAP4)
1830 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1832 l ^= bank->saved_datain;
1833 l &= bank->non_wakeup_gpios;
1836 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1837 defined(CONFIG_ARCH_OMAP4)
1838 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1839 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1840 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1841 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1842 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1843 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1853 * This may get called early from board specific init
1854 * for boards that have interrupts routed via FPGA.
1856 int __init omap_gpio_init(void)
1859 return _omap_gpio_init();
1864 static int __init omap_gpio_sysinit(void)
1869 ret = _omap_gpio_init();
1873 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1874 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
1875 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1877 ret = sysdev_class_register(&omap_gpio_sysclass);
1879 ret = sysdev_register(&omap_gpio_device);
1887 arch_initcall(omap_gpio_sysinit);
1890 #ifdef CONFIG_DEBUG_FS
1892 #include <linux/debugfs.h>
1893 #include <linux/seq_file.h>
1895 static int gpio_is_input(struct gpio_bank *bank, int mask)
1897 void __iomem *reg = bank->base;
1899 switch (bank->method) {
1901 reg += OMAP_MPUIO_IO_CNTL;
1903 case METHOD_GPIO_1510:
1904 reg += OMAP1510_GPIO_DIR_CONTROL;
1906 case METHOD_GPIO_1610:
1907 reg += OMAP1610_GPIO_DIRECTION;
1909 case METHOD_GPIO_730:
1910 reg += OMAP730_GPIO_DIR_CONTROL;
1912 case METHOD_GPIO_850:
1913 reg += OMAP850_GPIO_DIR_CONTROL;
1915 case METHOD_GPIO_24XX:
1916 reg += OMAP24XX_GPIO_OE;
1919 return __raw_readl(reg) & mask;
1923 static int dbg_gpio_show(struct seq_file *s, void *unused)
1925 unsigned i, j, gpio;
1927 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1928 struct gpio_bank *bank = gpio_bank + i;
1929 unsigned bankwidth = 16;
1932 if (bank_is_mpuio(bank))
1933 gpio = OMAP_MPUIO(0);
1934 else if (cpu_class_is_omap2() || cpu_is_omap730() ||
1938 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1939 unsigned irq, value, is_in, irqstat;
1942 label = gpiochip_is_requested(&bank->chip, j);
1946 irq = bank->virtual_irq_start + j;
1947 value = gpio_get_value(gpio);
1948 is_in = gpio_is_input(bank, mask);
1950 if (bank_is_mpuio(bank))
1951 seq_printf(s, "MPUIO %2d ", j);
1953 seq_printf(s, "GPIO %3d ", gpio);
1954 seq_printf(s, "(%-20.20s): %s %s",
1956 is_in ? "in " : "out",
1957 value ? "hi" : "lo");
1959 /* FIXME for at least omap2, show pullup/pulldown state */
1961 irqstat = irq_desc[irq].status;
1962 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1963 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
1964 if (is_in && ((bank->suspend_wakeup & mask)
1965 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1966 char *trigger = NULL;
1968 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1969 case IRQ_TYPE_EDGE_FALLING:
1970 trigger = "falling";
1972 case IRQ_TYPE_EDGE_RISING:
1975 case IRQ_TYPE_EDGE_BOTH:
1976 trigger = "bothedge";
1978 case IRQ_TYPE_LEVEL_LOW:
1981 case IRQ_TYPE_LEVEL_HIGH:
1988 seq_printf(s, ", irq-%d %-8s%s",
1990 (bank->suspend_wakeup & mask)
1994 seq_printf(s, "\n");
1997 if (bank_is_mpuio(bank)) {
1998 seq_printf(s, "\n");
2005 static int dbg_gpio_open(struct inode *inode, struct file *file)
2007 return single_open(file, dbg_gpio_show, &inode->i_private);
2010 static const struct file_operations debug_fops = {
2011 .open = dbg_gpio_open,
2013 .llseek = seq_lseek,
2014 .release = single_release,
2017 static int __init omap_gpio_debuginit(void)
2019 (void) debugfs_create_file("omap_gpio", S_IRUGO,
2020 NULL, NULL, &debug_fops);
2023 late_initcall(omap_gpio_debuginit);