2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
22 #include <mach/hardware.h>
24 #include <mach/irqs.h>
25 #include <mach/gpio.h>
26 #include <asm/mach/irq.h>
29 * OMAP1510 GPIO registers
31 #define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
32 #define OMAP1510_GPIO_DATA_INPUT 0x00
33 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
34 #define OMAP1510_GPIO_DIR_CONTROL 0x08
35 #define OMAP1510_GPIO_INT_CONTROL 0x0c
36 #define OMAP1510_GPIO_INT_MASK 0x10
37 #define OMAP1510_GPIO_INT_STATUS 0x14
38 #define OMAP1510_GPIO_PIN_CONTROL 0x18
40 #define OMAP1510_IH_GPIO_BASE 64
43 * OMAP1610 specific GPIO registers
45 #define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
46 #define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
47 #define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
48 #define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
49 #define OMAP1610_GPIO_REVISION 0x0000
50 #define OMAP1610_GPIO_SYSCONFIG 0x0010
51 #define OMAP1610_GPIO_SYSSTATUS 0x0014
52 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
53 #define OMAP1610_GPIO_IRQENABLE1 0x001c
54 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
55 #define OMAP1610_GPIO_DATAIN 0x002c
56 #define OMAP1610_GPIO_DATAOUT 0x0030
57 #define OMAP1610_GPIO_DIRECTION 0x0034
58 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
61 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
62 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
64 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
65 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
68 * OMAP730 specific GPIO registers
70 #define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
71 #define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
72 #define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
73 #define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
74 #define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
75 #define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
76 #define OMAP730_GPIO_DATA_INPUT 0x00
77 #define OMAP730_GPIO_DATA_OUTPUT 0x04
78 #define OMAP730_GPIO_DIR_CONTROL 0x08
79 #define OMAP730_GPIO_INT_CONTROL 0x0c
80 #define OMAP730_GPIO_INT_MASK 0x10
81 #define OMAP730_GPIO_INT_STATUS 0x14
84 * omap24xx specific GPIO registers
86 #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
87 #define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
88 #define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
89 #define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
91 #define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
92 #define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
93 #define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
94 #define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
95 #define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
97 #define OMAP24XX_GPIO_REVISION 0x0000
98 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
99 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
100 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
101 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
102 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
103 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
104 #define OMAP24XX_GPIO_WAKE_EN 0x0020
105 #define OMAP24XX_GPIO_CTRL 0x0030
106 #define OMAP24XX_GPIO_OE 0x0034
107 #define OMAP24XX_GPIO_DATAIN 0x0038
108 #define OMAP24XX_GPIO_DATAOUT 0x003c
109 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
110 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
112 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
113 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
114 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
115 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
116 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
117 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
118 #define OMAP24XX_GPIO_SETWKUENA 0x0084
119 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
120 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
123 * omap34xx specific GPIO registers
126 #define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
127 #define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
128 #define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
129 #define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
130 #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
131 #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
133 #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
138 u16 virtual_irq_start;
140 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
144 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
145 u32 non_wakeup_gpios;
146 u32 enabled_non_wakeup_gpios;
149 u32 saved_fallingdetect;
150 u32 saved_risingdetect;
154 struct gpio_chip chip;
158 #define METHOD_MPUIO 0
159 #define METHOD_GPIO_1510 1
160 #define METHOD_GPIO_1610 2
161 #define METHOD_GPIO_730 3
162 #define METHOD_GPIO_24XX 4
164 #ifdef CONFIG_ARCH_OMAP16XX
165 static struct gpio_bank gpio_bank_1610[5] = {
166 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
167 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
168 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
169 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
170 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
174 #ifdef CONFIG_ARCH_OMAP15XX
175 static struct gpio_bank gpio_bank_1510[2] = {
176 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
177 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
181 #ifdef CONFIG_ARCH_OMAP730
182 static struct gpio_bank gpio_bank_730[7] = {
183 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
184 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
185 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
186 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
187 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
188 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
189 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
193 #ifdef CONFIG_ARCH_OMAP24XX
195 static struct gpio_bank gpio_bank_242x[4] = {
196 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
197 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
198 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
199 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
202 static struct gpio_bank gpio_bank_243x[5] = {
203 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
205 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
206 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
207 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
212 #ifdef CONFIG_ARCH_OMAP34XX
213 static struct gpio_bank gpio_bank_34xx[6] = {
214 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
217 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
218 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
219 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
224 static struct gpio_bank *gpio_bank;
225 static int gpio_bank_count;
227 static inline struct gpio_bank *get_gpio_bank(int gpio)
229 if (cpu_is_omap15xx()) {
230 if (OMAP_GPIO_IS_MPUIO(gpio))
231 return &gpio_bank[0];
232 return &gpio_bank[1];
234 if (cpu_is_omap16xx()) {
235 if (OMAP_GPIO_IS_MPUIO(gpio))
236 return &gpio_bank[0];
237 return &gpio_bank[1 + (gpio >> 4)];
239 if (cpu_is_omap730()) {
240 if (OMAP_GPIO_IS_MPUIO(gpio))
241 return &gpio_bank[0];
242 return &gpio_bank[1 + (gpio >> 5)];
244 if (cpu_is_omap24xx())
245 return &gpio_bank[gpio >> 5];
246 if (cpu_is_omap34xx())
247 return &gpio_bank[gpio >> 5];
250 static inline int get_gpio_index(int gpio)
252 if (cpu_is_omap730())
254 if (cpu_is_omap24xx())
256 if (cpu_is_omap34xx())
261 static inline int gpio_valid(int gpio)
265 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
266 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
270 if (cpu_is_omap15xx() && gpio < 16)
272 if ((cpu_is_omap16xx()) && gpio < 64)
274 if (cpu_is_omap730() && gpio < 192)
276 if (cpu_is_omap24xx() && gpio < 128)
278 if (cpu_is_omap34xx() && gpio < 160)
283 static int check_gpio(int gpio)
285 if (unlikely(gpio_valid(gpio)) < 0) {
286 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
293 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
295 void __iomem *reg = bank->base;
298 switch (bank->method) {
299 #ifdef CONFIG_ARCH_OMAP1
301 reg += OMAP_MPUIO_IO_CNTL;
304 #ifdef CONFIG_ARCH_OMAP15XX
305 case METHOD_GPIO_1510:
306 reg += OMAP1510_GPIO_DIR_CONTROL;
309 #ifdef CONFIG_ARCH_OMAP16XX
310 case METHOD_GPIO_1610:
311 reg += OMAP1610_GPIO_DIRECTION;
314 #ifdef CONFIG_ARCH_OMAP730
315 case METHOD_GPIO_730:
316 reg += OMAP730_GPIO_DIR_CONTROL;
319 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
320 case METHOD_GPIO_24XX:
321 reg += OMAP24XX_GPIO_OE;
328 l = __raw_readl(reg);
333 __raw_writel(l, reg);
336 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
338 void __iomem *reg = bank->base;
341 switch (bank->method) {
342 #ifdef CONFIG_ARCH_OMAP1
344 reg += OMAP_MPUIO_OUTPUT;
345 l = __raw_readl(reg);
352 #ifdef CONFIG_ARCH_OMAP15XX
353 case METHOD_GPIO_1510:
354 reg += OMAP1510_GPIO_DATA_OUTPUT;
355 l = __raw_readl(reg);
362 #ifdef CONFIG_ARCH_OMAP16XX
363 case METHOD_GPIO_1610:
365 reg += OMAP1610_GPIO_SET_DATAOUT;
367 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
371 #ifdef CONFIG_ARCH_OMAP730
372 case METHOD_GPIO_730:
373 reg += OMAP730_GPIO_DATA_OUTPUT;
374 l = __raw_readl(reg);
381 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
382 case METHOD_GPIO_24XX:
384 reg += OMAP24XX_GPIO_SETDATAOUT;
386 reg += OMAP24XX_GPIO_CLEARDATAOUT;
394 __raw_writel(l, reg);
397 static int __omap_get_gpio_datain(int gpio)
399 struct gpio_bank *bank;
402 if (check_gpio(gpio) < 0)
404 bank = get_gpio_bank(gpio);
406 switch (bank->method) {
407 #ifdef CONFIG_ARCH_OMAP1
409 reg += OMAP_MPUIO_INPUT_LATCH;
412 #ifdef CONFIG_ARCH_OMAP15XX
413 case METHOD_GPIO_1510:
414 reg += OMAP1510_GPIO_DATA_INPUT;
417 #ifdef CONFIG_ARCH_OMAP16XX
418 case METHOD_GPIO_1610:
419 reg += OMAP1610_GPIO_DATAIN;
422 #ifdef CONFIG_ARCH_OMAP730
423 case METHOD_GPIO_730:
424 reg += OMAP730_GPIO_DATA_INPUT;
427 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
428 case METHOD_GPIO_24XX:
429 reg += OMAP24XX_GPIO_DATAIN;
435 return (__raw_readl(reg)
436 & (1 << get_gpio_index(gpio))) != 0;
439 #define MOD_REG_BIT(reg, bit_mask, set) \
441 int l = __raw_readl(base + reg); \
442 if (set) l |= bit_mask; \
443 else l &= ~bit_mask; \
444 __raw_writel(l, base + reg); \
447 void omap_set_gpio_debounce(int gpio, int enable)
449 struct gpio_bank *bank;
451 u32 val, l = 1 << get_gpio_index(gpio);
453 if (cpu_class_is_omap1())
456 bank = get_gpio_bank(gpio);
459 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
460 val = __raw_readl(reg);
462 if (enable && !(val & l))
464 else if (!enable && val & l)
469 if (cpu_is_omap34xx())
470 enable ? clk_enable(bank->dbck) : clk_disable(bank->dbck);
472 __raw_writel(val, reg);
474 EXPORT_SYMBOL(omap_set_gpio_debounce);
476 void omap_set_gpio_debounce_time(int gpio, int enc_time)
478 struct gpio_bank *bank;
481 if (cpu_class_is_omap1())
484 bank = get_gpio_bank(gpio);
488 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
489 __raw_writel(enc_time, reg);
491 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
493 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
494 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
497 void __iomem *base = bank->base;
498 u32 gpio_bit = 1 << gpio;
500 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
501 trigger & IRQ_TYPE_LEVEL_LOW);
502 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
503 trigger & IRQ_TYPE_LEVEL_HIGH);
504 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
505 trigger & IRQ_TYPE_EDGE_RISING);
506 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
507 trigger & IRQ_TYPE_EDGE_FALLING);
509 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
511 __raw_writel(1 << gpio, bank->base
512 + OMAP24XX_GPIO_SETWKUENA);
514 __raw_writel(1 << gpio, bank->base
515 + OMAP24XX_GPIO_CLEARWKUENA);
518 bank->enabled_non_wakeup_gpios |= gpio_bit;
520 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
524 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
525 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
529 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
531 void __iomem *reg = bank->base;
534 switch (bank->method) {
535 #ifdef CONFIG_ARCH_OMAP1
537 reg += OMAP_MPUIO_GPIO_INT_EDGE;
538 l = __raw_readl(reg);
539 if (trigger & IRQ_TYPE_EDGE_RISING)
541 else if (trigger & IRQ_TYPE_EDGE_FALLING)
547 #ifdef CONFIG_ARCH_OMAP15XX
548 case METHOD_GPIO_1510:
549 reg += OMAP1510_GPIO_INT_CONTROL;
550 l = __raw_readl(reg);
551 if (trigger & IRQ_TYPE_EDGE_RISING)
553 else if (trigger & IRQ_TYPE_EDGE_FALLING)
559 #ifdef CONFIG_ARCH_OMAP16XX
560 case METHOD_GPIO_1610:
562 reg += OMAP1610_GPIO_EDGE_CTRL2;
564 reg += OMAP1610_GPIO_EDGE_CTRL1;
566 l = __raw_readl(reg);
567 l &= ~(3 << (gpio << 1));
568 if (trigger & IRQ_TYPE_EDGE_RISING)
569 l |= 2 << (gpio << 1);
570 if (trigger & IRQ_TYPE_EDGE_FALLING)
571 l |= 1 << (gpio << 1);
573 /* Enable wake-up during idle for dynamic tick */
574 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
576 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
579 #ifdef CONFIG_ARCH_OMAP730
580 case METHOD_GPIO_730:
581 reg += OMAP730_GPIO_INT_CONTROL;
582 l = __raw_readl(reg);
583 if (trigger & IRQ_TYPE_EDGE_RISING)
585 else if (trigger & IRQ_TYPE_EDGE_FALLING)
591 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
592 case METHOD_GPIO_24XX:
593 set_24xx_gpio_triggering(bank, gpio, trigger);
599 __raw_writel(l, reg);
605 static int gpio_irq_type(unsigned irq, unsigned type)
607 struct gpio_bank *bank;
612 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
613 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
615 gpio = irq - IH_GPIO_BASE;
617 if (check_gpio(gpio) < 0)
620 if (type & ~IRQ_TYPE_SENSE_MASK)
623 /* OMAP1 allows only only edge triggering */
624 if (!cpu_class_is_omap2()
625 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
628 bank = get_irq_chip_data(irq);
629 spin_lock_irqsave(&bank->lock, flags);
630 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
632 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
633 irq_desc[irq].status |= type;
635 spin_unlock_irqrestore(&bank->lock, flags);
637 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
638 __set_irq_handler_unlocked(irq, handle_level_irq);
639 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
640 __set_irq_handler_unlocked(irq, handle_edge_irq);
645 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
647 void __iomem *reg = bank->base;
649 switch (bank->method) {
650 #ifdef CONFIG_ARCH_OMAP1
652 /* MPUIO irqstatus is reset by reading the status register,
653 * so do nothing here */
656 #ifdef CONFIG_ARCH_OMAP15XX
657 case METHOD_GPIO_1510:
658 reg += OMAP1510_GPIO_INT_STATUS;
661 #ifdef CONFIG_ARCH_OMAP16XX
662 case METHOD_GPIO_1610:
663 reg += OMAP1610_GPIO_IRQSTATUS1;
666 #ifdef CONFIG_ARCH_OMAP730
667 case METHOD_GPIO_730:
668 reg += OMAP730_GPIO_INT_STATUS;
671 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
672 case METHOD_GPIO_24XX:
673 reg += OMAP24XX_GPIO_IRQSTATUS1;
680 __raw_writel(gpio_mask, reg);
682 /* Workaround for clearing DSP GPIO interrupts to allow retention */
683 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
684 if (cpu_is_omap24xx() || cpu_is_omap34xx())
685 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
689 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
691 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
694 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
696 void __iomem *reg = bank->base;
701 switch (bank->method) {
702 #ifdef CONFIG_ARCH_OMAP1
704 reg += OMAP_MPUIO_GPIO_MASKIT;
709 #ifdef CONFIG_ARCH_OMAP15XX
710 case METHOD_GPIO_1510:
711 reg += OMAP1510_GPIO_INT_MASK;
716 #ifdef CONFIG_ARCH_OMAP16XX
717 case METHOD_GPIO_1610:
718 reg += OMAP1610_GPIO_IRQENABLE1;
722 #ifdef CONFIG_ARCH_OMAP730
723 case METHOD_GPIO_730:
724 reg += OMAP730_GPIO_INT_MASK;
729 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
730 case METHOD_GPIO_24XX:
731 reg += OMAP24XX_GPIO_IRQENABLE1;
740 l = __raw_readl(reg);
747 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
749 void __iomem *reg = bank->base;
752 switch (bank->method) {
753 #ifdef CONFIG_ARCH_OMAP1
755 reg += OMAP_MPUIO_GPIO_MASKIT;
756 l = __raw_readl(reg);
763 #ifdef CONFIG_ARCH_OMAP15XX
764 case METHOD_GPIO_1510:
765 reg += OMAP1510_GPIO_INT_MASK;
766 l = __raw_readl(reg);
773 #ifdef CONFIG_ARCH_OMAP16XX
774 case METHOD_GPIO_1610:
776 reg += OMAP1610_GPIO_SET_IRQENABLE1;
778 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
782 #ifdef CONFIG_ARCH_OMAP730
783 case METHOD_GPIO_730:
784 reg += OMAP730_GPIO_INT_MASK;
785 l = __raw_readl(reg);
792 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
793 case METHOD_GPIO_24XX:
795 reg += OMAP24XX_GPIO_SETIRQENABLE1;
797 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
805 __raw_writel(l, reg);
808 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
810 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
814 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
815 * 1510 does not seem to have a wake-up register. If JTAG is connected
816 * to the target, system will wake up always on GPIO events. While
817 * system is running all registered GPIO interrupts need to have wake-up
818 * enabled. When system is suspended, only selected GPIO interrupts need
819 * to have wake-up enabled.
821 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
825 switch (bank->method) {
826 #ifdef CONFIG_ARCH_OMAP16XX
828 case METHOD_GPIO_1610:
829 spin_lock_irqsave(&bank->lock, flags);
831 bank->suspend_wakeup |= (1 << gpio);
832 enable_irq_wake(bank->irq);
834 disable_irq_wake(bank->irq);
835 bank->suspend_wakeup &= ~(1 << gpio);
837 spin_unlock_irqrestore(&bank->lock, flags);
840 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
841 case METHOD_GPIO_24XX:
842 if (bank->non_wakeup_gpios & (1 << gpio)) {
843 printk(KERN_ERR "Unable to modify wakeup on "
844 "non-wakeup GPIO%d\n",
845 (bank - gpio_bank) * 32 + gpio);
848 spin_lock_irqsave(&bank->lock, flags);
850 bank->suspend_wakeup |= (1 << gpio);
851 enable_irq_wake(bank->irq);
853 disable_irq_wake(bank->irq);
854 bank->suspend_wakeup &= ~(1 << gpio);
856 spin_unlock_irqrestore(&bank->lock, flags);
860 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
866 static void _reset_gpio(struct gpio_bank *bank, int gpio)
868 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
869 _set_gpio_irqenable(bank, gpio, 0);
870 _clear_gpio_irqstatus(bank, gpio);
871 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
874 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
875 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
877 unsigned int gpio = irq - IH_GPIO_BASE;
878 struct gpio_bank *bank;
881 if (check_gpio(gpio) < 0)
883 bank = get_irq_chip_data(irq);
884 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
889 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
891 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
894 spin_lock_irqsave(&bank->lock, flags);
896 /* Set trigger to none. You need to enable the desired trigger with
897 * request_irq() or set_irq_type().
899 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
901 #ifdef CONFIG_ARCH_OMAP15XX
902 if (bank->method == METHOD_GPIO_1510) {
905 /* Claim the pin for MPU */
906 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
907 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
910 spin_unlock_irqrestore(&bank->lock, flags);
915 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
917 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
920 spin_lock_irqsave(&bank->lock, flags);
921 #ifdef CONFIG_ARCH_OMAP16XX
922 if (bank->method == METHOD_GPIO_1610) {
923 /* Disable wake-up during idle for dynamic tick */
924 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
925 __raw_writel(1 << offset, reg);
928 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
929 if (bank->method == METHOD_GPIO_24XX) {
930 /* Disable wake-up during idle for dynamic tick */
931 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
932 __raw_writel(1 << offset, reg);
935 _reset_gpio(bank, bank->chip.base + offset);
936 spin_unlock_irqrestore(&bank->lock, flags);
940 * We need to unmask the GPIO bank interrupt as soon as possible to
941 * avoid missing GPIO interrupts for other lines in the bank.
942 * Then we need to mask-read-clear-unmask the triggered GPIO lines
943 * in the bank to avoid missing nested interrupts for a GPIO line.
944 * If we wait to unmask individual GPIO lines in the bank after the
945 * line's interrupt handler has been run, we may miss some nested
948 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
950 void __iomem *isr_reg = NULL;
952 unsigned int gpio_irq;
953 struct gpio_bank *bank;
957 desc->chip->ack(irq);
959 bank = get_irq_data(irq);
960 #ifdef CONFIG_ARCH_OMAP1
961 if (bank->method == METHOD_MPUIO)
962 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
964 #ifdef CONFIG_ARCH_OMAP15XX
965 if (bank->method == METHOD_GPIO_1510)
966 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
968 #if defined(CONFIG_ARCH_OMAP16XX)
969 if (bank->method == METHOD_GPIO_1610)
970 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
972 #ifdef CONFIG_ARCH_OMAP730
973 if (bank->method == METHOD_GPIO_730)
974 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
976 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
977 if (bank->method == METHOD_GPIO_24XX)
978 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
981 u32 isr_saved, level_mask = 0;
984 enabled = _get_gpio_irqbank_mask(bank);
985 isr_saved = isr = __raw_readl(isr_reg) & enabled;
987 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
990 if (cpu_class_is_omap2()) {
991 level_mask = bank->level_mask & enabled;
994 /* clear edge sensitive interrupts before handler(s) are
995 called so that we don't miss any interrupt occurred while
997 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
998 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
999 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1001 /* if there is only edge sensitive GPIO pin interrupts
1002 configured, we could unmask GPIO bank interrupt immediately */
1003 if (!level_mask && !unmasked) {
1005 desc->chip->unmask(irq);
1013 gpio_irq = bank->virtual_irq_start;
1014 for (; isr != 0; isr >>= 1, gpio_irq++) {
1018 generic_handle_irq(gpio_irq);
1021 /* if bank has any level sensitive GPIO pin interrupt
1022 configured, we must unmask the bank interrupt only after
1023 handler(s) are executed in order to avoid spurious bank
1026 desc->chip->unmask(irq);
1030 static void gpio_irq_shutdown(unsigned int irq)
1032 unsigned int gpio = irq - IH_GPIO_BASE;
1033 struct gpio_bank *bank = get_irq_chip_data(irq);
1035 _reset_gpio(bank, gpio);
1038 static void gpio_ack_irq(unsigned int irq)
1040 unsigned int gpio = irq - IH_GPIO_BASE;
1041 struct gpio_bank *bank = get_irq_chip_data(irq);
1043 _clear_gpio_irqstatus(bank, gpio);
1046 static void gpio_mask_irq(unsigned int irq)
1048 unsigned int gpio = irq - IH_GPIO_BASE;
1049 struct gpio_bank *bank = get_irq_chip_data(irq);
1051 _set_gpio_irqenable(bank, gpio, 0);
1054 static void gpio_unmask_irq(unsigned int irq)
1056 unsigned int gpio = irq - IH_GPIO_BASE;
1057 struct gpio_bank *bank = get_irq_chip_data(irq);
1058 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1060 /* For level-triggered GPIOs, the clearing must be done after
1061 * the HW source is cleared, thus after the handler has run */
1062 if (bank->level_mask & irq_mask) {
1063 _set_gpio_irqenable(bank, gpio, 0);
1064 _clear_gpio_irqstatus(bank, gpio);
1067 _set_gpio_irqenable(bank, gpio, 1);
1070 static struct irq_chip gpio_irq_chip = {
1072 .shutdown = gpio_irq_shutdown,
1073 .ack = gpio_ack_irq,
1074 .mask = gpio_mask_irq,
1075 .unmask = gpio_unmask_irq,
1076 .set_type = gpio_irq_type,
1077 .set_wake = gpio_wake_enable,
1080 /*---------------------------------------------------------------------*/
1082 #ifdef CONFIG_ARCH_OMAP1
1084 /* MPUIO uses the always-on 32k clock */
1086 static void mpuio_ack_irq(unsigned int irq)
1088 /* The ISR is reset automatically, so do nothing here. */
1091 static void mpuio_mask_irq(unsigned int irq)
1093 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1094 struct gpio_bank *bank = get_irq_chip_data(irq);
1096 _set_gpio_irqenable(bank, gpio, 0);
1099 static void mpuio_unmask_irq(unsigned int irq)
1101 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1102 struct gpio_bank *bank = get_irq_chip_data(irq);
1104 _set_gpio_irqenable(bank, gpio, 1);
1107 static struct irq_chip mpuio_irq_chip = {
1109 .ack = mpuio_ack_irq,
1110 .mask = mpuio_mask_irq,
1111 .unmask = mpuio_unmask_irq,
1112 .set_type = gpio_irq_type,
1113 #ifdef CONFIG_ARCH_OMAP16XX
1114 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1115 .set_wake = gpio_wake_enable,
1120 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1123 #ifdef CONFIG_ARCH_OMAP16XX
1125 #include <linux/platform_device.h>
1127 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1129 struct gpio_bank *bank = platform_get_drvdata(pdev);
1130 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1131 unsigned long flags;
1133 spin_lock_irqsave(&bank->lock, flags);
1134 bank->saved_wakeup = __raw_readl(mask_reg);
1135 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1136 spin_unlock_irqrestore(&bank->lock, flags);
1141 static int omap_mpuio_resume_early(struct platform_device *pdev)
1143 struct gpio_bank *bank = platform_get_drvdata(pdev);
1144 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1145 unsigned long flags;
1147 spin_lock_irqsave(&bank->lock, flags);
1148 __raw_writel(bank->saved_wakeup, mask_reg);
1149 spin_unlock_irqrestore(&bank->lock, flags);
1154 /* use platform_driver for this, now that there's no longer any
1155 * point to sys_device (other than not disturbing old code).
1157 static struct platform_driver omap_mpuio_driver = {
1158 .suspend_late = omap_mpuio_suspend_late,
1159 .resume_early = omap_mpuio_resume_early,
1165 static struct platform_device omap_mpuio_device = {
1169 .driver = &omap_mpuio_driver.driver,
1171 /* could list the /proc/iomem resources */
1174 static inline void mpuio_init(void)
1176 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1178 if (platform_driver_register(&omap_mpuio_driver) == 0)
1179 (void) platform_device_register(&omap_mpuio_device);
1183 static inline void mpuio_init(void) {}
1188 extern struct irq_chip mpuio_irq_chip;
1190 #define bank_is_mpuio(bank) 0
1191 static inline void mpuio_init(void) {}
1195 /*---------------------------------------------------------------------*/
1197 /* REVISIT these are stupid implementations! replace by ones that
1198 * don't switch on METHOD_* and which mostly avoid spinlocks
1201 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1203 struct gpio_bank *bank;
1204 unsigned long flags;
1206 bank = container_of(chip, struct gpio_bank, chip);
1207 spin_lock_irqsave(&bank->lock, flags);
1208 _set_gpio_direction(bank, offset, 1);
1209 spin_unlock_irqrestore(&bank->lock, flags);
1213 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1215 return __omap_get_gpio_datain(chip->base + offset);
1218 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1220 struct gpio_bank *bank;
1221 unsigned long flags;
1223 bank = container_of(chip, struct gpio_bank, chip);
1224 spin_lock_irqsave(&bank->lock, flags);
1225 _set_gpio_dataout(bank, offset, value);
1226 _set_gpio_direction(bank, offset, 0);
1227 spin_unlock_irqrestore(&bank->lock, flags);
1231 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1233 struct gpio_bank *bank;
1234 unsigned long flags;
1236 bank = container_of(chip, struct gpio_bank, chip);
1237 spin_lock_irqsave(&bank->lock, flags);
1238 _set_gpio_dataout(bank, offset, value);
1239 spin_unlock_irqrestore(&bank->lock, flags);
1242 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1244 struct gpio_bank *bank;
1246 bank = container_of(chip, struct gpio_bank, chip);
1247 return bank->virtual_irq_start + offset;
1250 /*---------------------------------------------------------------------*/
1252 static int initialized;
1253 #if !defined(CONFIG_ARCH_OMAP3)
1254 static struct clk * gpio_ick;
1257 #if defined(CONFIG_ARCH_OMAP2)
1258 static struct clk * gpio_fck;
1261 #if defined(CONFIG_ARCH_OMAP2430)
1262 static struct clk * gpio5_ick;
1263 static struct clk * gpio5_fck;
1266 #if defined(CONFIG_ARCH_OMAP3)
1267 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1270 /* This lock class tells lockdep that GPIO irqs are in a different
1271 * category than their parents, so it won't report false recursion.
1273 static struct lock_class_key gpio_lock_class;
1275 static int __init _omap_gpio_init(void)
1279 struct gpio_bank *bank;
1284 #if defined(CONFIG_ARCH_OMAP1)
1285 if (cpu_is_omap15xx()) {
1286 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1287 if (IS_ERR(gpio_ick))
1288 printk("Could not get arm_gpio_ck\n");
1290 clk_enable(gpio_ick);
1293 #if defined(CONFIG_ARCH_OMAP2)
1294 if (cpu_class_is_omap2()) {
1295 gpio_ick = clk_get(NULL, "gpios_ick");
1296 if (IS_ERR(gpio_ick))
1297 printk("Could not get gpios_ick\n");
1299 clk_enable(gpio_ick);
1300 gpio_fck = clk_get(NULL, "gpios_fck");
1301 if (IS_ERR(gpio_fck))
1302 printk("Could not get gpios_fck\n");
1304 clk_enable(gpio_fck);
1307 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1309 #if defined(CONFIG_ARCH_OMAP2430)
1310 if (cpu_is_omap2430()) {
1311 gpio5_ick = clk_get(NULL, "gpio5_ick");
1312 if (IS_ERR(gpio5_ick))
1313 printk("Could not get gpio5_ick\n");
1315 clk_enable(gpio5_ick);
1316 gpio5_fck = clk_get(NULL, "gpio5_fck");
1317 if (IS_ERR(gpio5_fck))
1318 printk("Could not get gpio5_fck\n");
1320 clk_enable(gpio5_fck);
1326 #if defined(CONFIG_ARCH_OMAP3)
1327 if (cpu_is_omap34xx()) {
1328 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1329 sprintf(clk_name, "gpio%d_ick", i + 1);
1330 gpio_iclks[i] = clk_get(NULL, clk_name);
1331 if (IS_ERR(gpio_iclks[i]))
1332 printk(KERN_ERR "Could not get %s\n", clk_name);
1334 clk_enable(gpio_iclks[i]);
1340 #ifdef CONFIG_ARCH_OMAP15XX
1341 if (cpu_is_omap15xx()) {
1342 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1343 gpio_bank_count = 2;
1344 gpio_bank = gpio_bank_1510;
1347 #if defined(CONFIG_ARCH_OMAP16XX)
1348 if (cpu_is_omap16xx()) {
1351 gpio_bank_count = 5;
1352 gpio_bank = gpio_bank_1610;
1353 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1354 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1355 (rev >> 4) & 0x0f, rev & 0x0f);
1358 #ifdef CONFIG_ARCH_OMAP730
1359 if (cpu_is_omap730()) {
1360 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1361 gpio_bank_count = 7;
1362 gpio_bank = gpio_bank_730;
1366 #ifdef CONFIG_ARCH_OMAP24XX
1367 if (cpu_is_omap242x()) {
1370 gpio_bank_count = 4;
1371 gpio_bank = gpio_bank_242x;
1372 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1373 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1374 (rev >> 4) & 0x0f, rev & 0x0f);
1376 if (cpu_is_omap243x()) {
1379 gpio_bank_count = 5;
1380 gpio_bank = gpio_bank_243x;
1381 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1382 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1383 (rev >> 4) & 0x0f, rev & 0x0f);
1386 #ifdef CONFIG_ARCH_OMAP34XX
1387 if (cpu_is_omap34xx()) {
1390 gpio_bank_count = OMAP34XX_NR_GPIOS;
1391 gpio_bank = gpio_bank_34xx;
1392 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1393 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1394 (rev >> 4) & 0x0f, rev & 0x0f);
1397 for (i = 0; i < gpio_bank_count; i++) {
1398 int j, gpio_count = 16;
1400 bank = &gpio_bank[i];
1401 spin_lock_init(&bank->lock);
1402 if (bank_is_mpuio(bank))
1403 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1404 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1405 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1406 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1408 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1409 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1410 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1411 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1413 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
1414 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1415 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1417 gpio_count = 32; /* 730 has 32-bit GPIOs */
1420 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1421 if (bank->method == METHOD_GPIO_24XX) {
1422 static const u32 non_wakeup_gpios[] = {
1423 0xe203ffc0, 0x08700040
1426 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1427 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1428 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1430 /* Initialize interface clock ungated, module enabled */
1431 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1432 if (i < ARRAY_SIZE(non_wakeup_gpios))
1433 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1438 /* REVISIT eventually switch from OMAP-specific gpio structs
1439 * over to the generic ones
1441 bank->chip.request = omap_gpio_request;
1442 bank->chip.free = omap_gpio_free;
1443 bank->chip.direction_input = gpio_input;
1444 bank->chip.get = gpio_get;
1445 bank->chip.direction_output = gpio_output;
1446 bank->chip.set = gpio_set;
1447 bank->chip.to_irq = gpio_2irq;
1448 if (bank_is_mpuio(bank)) {
1449 bank->chip.label = "mpuio";
1450 #ifdef CONFIG_ARCH_OMAP16XX
1451 bank->chip.dev = &omap_mpuio_device.dev;
1453 bank->chip.base = OMAP_MPUIO(0);
1455 bank->chip.label = "gpio";
1456 bank->chip.base = gpio;
1459 bank->chip.ngpio = gpio_count;
1461 gpiochip_add(&bank->chip);
1463 for (j = bank->virtual_irq_start;
1464 j < bank->virtual_irq_start + gpio_count; j++) {
1465 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1466 set_irq_chip_data(j, bank);
1467 if (bank_is_mpuio(bank))
1468 set_irq_chip(j, &mpuio_irq_chip);
1470 set_irq_chip(j, &gpio_irq_chip);
1471 set_irq_handler(j, handle_simple_irq);
1472 set_irq_flags(j, IRQF_VALID);
1474 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1475 set_irq_data(bank->irq, bank);
1477 if (cpu_is_omap34xx()) {
1478 sprintf(clk_name, "gpio%d_dbck", i + 1);
1479 bank->dbck = clk_get(NULL, clk_name);
1480 if (IS_ERR(bank->dbck))
1481 printk(KERN_ERR "Could not get %s\n", clk_name);
1485 /* Enable system clock for GPIO module.
1486 * The CAM_CLK_CTRL *is* really the right place. */
1487 if (cpu_is_omap16xx())
1488 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1490 /* Enable autoidle for the OCP interface */
1491 if (cpu_is_omap24xx())
1492 omap_writel(1 << 0, 0x48019010);
1493 if (cpu_is_omap34xx())
1494 omap_writel(1 << 0, 0x48306814);
1499 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1500 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1504 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1507 for (i = 0; i < gpio_bank_count; i++) {
1508 struct gpio_bank *bank = &gpio_bank[i];
1509 void __iomem *wake_status;
1510 void __iomem *wake_clear;
1511 void __iomem *wake_set;
1512 unsigned long flags;
1514 switch (bank->method) {
1515 #ifdef CONFIG_ARCH_OMAP16XX
1516 case METHOD_GPIO_1610:
1517 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1518 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1519 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1522 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1523 case METHOD_GPIO_24XX:
1524 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1525 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1526 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1533 spin_lock_irqsave(&bank->lock, flags);
1534 bank->saved_wakeup = __raw_readl(wake_status);
1535 __raw_writel(0xffffffff, wake_clear);
1536 __raw_writel(bank->suspend_wakeup, wake_set);
1537 spin_unlock_irqrestore(&bank->lock, flags);
1543 static int omap_gpio_resume(struct sys_device *dev)
1547 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1550 for (i = 0; i < gpio_bank_count; i++) {
1551 struct gpio_bank *bank = &gpio_bank[i];
1552 void __iomem *wake_clear;
1553 void __iomem *wake_set;
1554 unsigned long flags;
1556 switch (bank->method) {
1557 #ifdef CONFIG_ARCH_OMAP16XX
1558 case METHOD_GPIO_1610:
1559 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1560 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1563 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1564 case METHOD_GPIO_24XX:
1565 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1566 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1573 spin_lock_irqsave(&bank->lock, flags);
1574 __raw_writel(0xffffffff, wake_clear);
1575 __raw_writel(bank->saved_wakeup, wake_set);
1576 spin_unlock_irqrestore(&bank->lock, flags);
1582 static struct sysdev_class omap_gpio_sysclass = {
1584 .suspend = omap_gpio_suspend,
1585 .resume = omap_gpio_resume,
1588 static struct sys_device omap_gpio_device = {
1590 .cls = &omap_gpio_sysclass,
1595 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1597 static int workaround_enabled;
1599 void omap2_gpio_prepare_for_retention(void)
1603 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1604 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1605 for (i = 0; i < gpio_bank_count; i++) {
1606 struct gpio_bank *bank = &gpio_bank[i];
1609 if (!(bank->enabled_non_wakeup_gpios))
1611 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1612 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1613 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1614 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1616 bank->saved_fallingdetect = l1;
1617 bank->saved_risingdetect = l2;
1618 l1 &= ~bank->enabled_non_wakeup_gpios;
1619 l2 &= ~bank->enabled_non_wakeup_gpios;
1620 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1621 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1622 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1627 workaround_enabled = 0;
1630 workaround_enabled = 1;
1633 void omap2_gpio_resume_after_retention(void)
1637 if (!workaround_enabled)
1639 for (i = 0; i < gpio_bank_count; i++) {
1640 struct gpio_bank *bank = &gpio_bank[i];
1643 if (!(bank->enabled_non_wakeup_gpios))
1645 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1646 __raw_writel(bank->saved_fallingdetect,
1647 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1648 __raw_writel(bank->saved_risingdetect,
1649 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1651 /* Check if any of the non-wakeup interrupt GPIOs have changed
1652 * state. If so, generate an IRQ by software. This is
1653 * horribly racy, but it's the best we can do to work around
1654 * this silicon bug. */
1655 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1656 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1658 l ^= bank->saved_datain;
1659 l &= bank->non_wakeup_gpios;
1662 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1663 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1664 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1665 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1666 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1667 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1668 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1678 * This may get called early from board specific init
1679 * for boards that have interrupts routed via FPGA.
1681 int __init omap_gpio_init(void)
1684 return _omap_gpio_init();
1689 static int __init omap_gpio_sysinit(void)
1694 ret = _omap_gpio_init();
1698 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1699 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1701 ret = sysdev_class_register(&omap_gpio_sysclass);
1703 ret = sysdev_register(&omap_gpio_device);
1711 arch_initcall(omap_gpio_sysinit);
1714 #ifdef CONFIG_DEBUG_FS
1716 #include <linux/debugfs.h>
1717 #include <linux/seq_file.h>
1719 static int gpio_is_input(struct gpio_bank *bank, int mask)
1721 void __iomem *reg = bank->base;
1723 switch (bank->method) {
1725 reg += OMAP_MPUIO_IO_CNTL;
1727 case METHOD_GPIO_1510:
1728 reg += OMAP1510_GPIO_DIR_CONTROL;
1730 case METHOD_GPIO_1610:
1731 reg += OMAP1610_GPIO_DIRECTION;
1733 case METHOD_GPIO_730:
1734 reg += OMAP730_GPIO_DIR_CONTROL;
1736 case METHOD_GPIO_24XX:
1737 reg += OMAP24XX_GPIO_OE;
1740 return __raw_readl(reg) & mask;
1744 static int dbg_gpio_show(struct seq_file *s, void *unused)
1746 unsigned i, j, gpio;
1748 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1749 struct gpio_bank *bank = gpio_bank + i;
1750 unsigned bankwidth = 16;
1753 if (bank_is_mpuio(bank))
1754 gpio = OMAP_MPUIO(0);
1755 else if (cpu_class_is_omap2() || cpu_is_omap730())
1758 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1759 unsigned irq, value, is_in, irqstat;
1762 label = gpiochip_is_requested(&bank->chip, j);
1766 irq = bank->virtual_irq_start + j;
1767 value = gpio_get_value(gpio);
1768 is_in = gpio_is_input(bank, mask);
1770 if (bank_is_mpuio(bank))
1771 seq_printf(s, "MPUIO %2d ", j);
1773 seq_printf(s, "GPIO %3d ", gpio);
1774 seq_printf(s, "(%-20.20s): %s %s",
1776 is_in ? "in " : "out",
1777 value ? "hi" : "lo");
1779 /* FIXME for at least omap2, show pullup/pulldown state */
1781 irqstat = irq_desc[irq].status;
1782 if (is_in && ((bank->suspend_wakeup & mask)
1783 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1784 char *trigger = NULL;
1786 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1787 case IRQ_TYPE_EDGE_FALLING:
1788 trigger = "falling";
1790 case IRQ_TYPE_EDGE_RISING:
1793 case IRQ_TYPE_EDGE_BOTH:
1794 trigger = "bothedge";
1796 case IRQ_TYPE_LEVEL_LOW:
1799 case IRQ_TYPE_LEVEL_HIGH:
1806 seq_printf(s, ", irq-%d %-8s%s",
1808 (bank->suspend_wakeup & mask)
1811 seq_printf(s, "\n");
1814 if (bank_is_mpuio(bank)) {
1815 seq_printf(s, "\n");
1822 static int dbg_gpio_open(struct inode *inode, struct file *file)
1824 return single_open(file, dbg_gpio_show, &inode->i_private);
1827 static const struct file_operations debug_fops = {
1828 .open = dbg_gpio_open,
1830 .llseek = seq_lseek,
1831 .release = single_release,
1834 static int __init omap_gpio_debuginit(void)
1836 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1837 NULL, NULL, &debug_fops);
1840 late_initcall(omap_gpio_debuginit);