2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
25 #include <mach/hardware.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
32 * OMAP1510 GPIO registers
34 #define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
35 #define OMAP1510_GPIO_DATA_INPUT 0x00
36 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
37 #define OMAP1510_GPIO_DIR_CONTROL 0x08
38 #define OMAP1510_GPIO_INT_CONTROL 0x0c
39 #define OMAP1510_GPIO_INT_MASK 0x10
40 #define OMAP1510_GPIO_INT_STATUS 0x14
41 #define OMAP1510_GPIO_PIN_CONTROL 0x18
43 #define OMAP1510_IH_GPIO_BASE 64
46 * OMAP1610 specific GPIO registers
48 #define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
49 #define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
50 #define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
51 #define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
52 #define OMAP1610_GPIO_REVISION 0x0000
53 #define OMAP1610_GPIO_SYSCONFIG 0x0010
54 #define OMAP1610_GPIO_SYSSTATUS 0x0014
55 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
56 #define OMAP1610_GPIO_IRQENABLE1 0x001c
57 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
58 #define OMAP1610_GPIO_DATAIN 0x002c
59 #define OMAP1610_GPIO_DATAOUT 0x0030
60 #define OMAP1610_GPIO_DIRECTION 0x0034
61 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
64 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
65 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
67 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
68 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
71 * OMAP730 specific GPIO registers
73 #define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
74 #define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
75 #define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
76 #define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
77 #define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
78 #define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
79 #define OMAP730_GPIO_DATA_INPUT 0x00
80 #define OMAP730_GPIO_DATA_OUTPUT 0x04
81 #define OMAP730_GPIO_DIR_CONTROL 0x08
82 #define OMAP730_GPIO_INT_CONTROL 0x0c
83 #define OMAP730_GPIO_INT_MASK 0x10
84 #define OMAP730_GPIO_INT_STATUS 0x14
87 * OMAP850 specific GPIO registers
89 #define OMAP850_GPIO1_BASE IO_ADDRESS(0xfffbc000)
90 #define OMAP850_GPIO2_BASE IO_ADDRESS(0xfffbc800)
91 #define OMAP850_GPIO3_BASE IO_ADDRESS(0xfffbd000)
92 #define OMAP850_GPIO4_BASE IO_ADDRESS(0xfffbd800)
93 #define OMAP850_GPIO5_BASE IO_ADDRESS(0xfffbe000)
94 #define OMAP850_GPIO6_BASE IO_ADDRESS(0xfffbe800)
95 #define OMAP850_GPIO_DATA_INPUT 0x00
96 #define OMAP850_GPIO_DATA_OUTPUT 0x04
97 #define OMAP850_GPIO_DIR_CONTROL 0x08
98 #define OMAP850_GPIO_INT_CONTROL 0x0c
99 #define OMAP850_GPIO_INT_MASK 0x10
100 #define OMAP850_GPIO_INT_STATUS 0x14
103 * omap24xx specific GPIO registers
105 #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
106 #define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
107 #define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
108 #define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
110 #define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
111 #define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
112 #define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
113 #define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
114 #define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
116 #define OMAP24XX_GPIO_REVISION 0x0000
117 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
118 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
119 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
120 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
121 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
122 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
123 #define OMAP24XX_GPIO_WAKE_EN 0x0020
124 #define OMAP24XX_GPIO_CTRL 0x0030
125 #define OMAP24XX_GPIO_OE 0x0034
126 #define OMAP24XX_GPIO_DATAIN 0x0038
127 #define OMAP24XX_GPIO_DATAOUT 0x003c
128 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
129 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
130 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
131 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
132 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
133 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
134 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
135 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
136 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
137 #define OMAP24XX_GPIO_SETWKUENA 0x0084
138 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
139 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
141 #define OMAP4_GPIO_REVISION 0x0000
142 #define OMAP4_GPIO_SYSCONFIG 0x0010
143 #define OMAP4_GPIO_EOI 0x0020
144 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
145 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
146 #define OMAP4_GPIO_IRQSTATUS0 0x002c
147 #define OMAP4_GPIO_IRQSTATUS1 0x0030
148 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
149 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
150 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
151 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
152 #define OMAP4_GPIO_IRQWAKEN0 0x0044
153 #define OMAP4_GPIO_IRQWAKEN1 0x0048
154 #define OMAP4_GPIO_SYSSTATUS 0x0104
155 #define OMAP4_GPIO_CTRL 0x0130
156 #define OMAP4_GPIO_OE 0x0134
157 #define OMAP4_GPIO_DATAIN 0x0138
158 #define OMAP4_GPIO_DATAOUT 0x013c
159 #define OMAP4_GPIO_LEVELDETECT0 0x0140
160 #define OMAP4_GPIO_LEVELDETECT1 0x0144
161 #define OMAP4_GPIO_RISINGDETECT 0x0148
162 #define OMAP4_GPIO_FALLINGDETECT 0x014c
163 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
164 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
165 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
166 #define OMAP4_GPIO_SETDATAOUT 0x0194
168 * omap34xx specific GPIO registers
171 #define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
172 #define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
173 #define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
174 #define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
175 #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
176 #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
179 * OMAP44XX specific GPIO registers
181 #define OMAP44XX_GPIO1_BASE IO_ADDRESS(0x4a310000)
182 #define OMAP44XX_GPIO2_BASE IO_ADDRESS(0x48055000)
183 #define OMAP44XX_GPIO3_BASE IO_ADDRESS(0x48057000)
184 #define OMAP44XX_GPIO4_BASE IO_ADDRESS(0x48059000)
185 #define OMAP44XX_GPIO5_BASE IO_ADDRESS(0x4805B000)
186 #define OMAP44XX_GPIO6_BASE IO_ADDRESS(0x4805D000)
188 #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
193 u16 virtual_irq_start;
195 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
196 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
200 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
201 defined(CONFIG_ARCH_OMAP4)
202 u32 non_wakeup_gpios;
203 u32 enabled_non_wakeup_gpios;
206 u32 saved_fallingdetect;
207 u32 saved_risingdetect;
211 struct gpio_chip chip;
215 #define METHOD_MPUIO 0
216 #define METHOD_GPIO_1510 1
217 #define METHOD_GPIO_1610 2
218 #define METHOD_GPIO_730 3
219 #define METHOD_GPIO_850 4
220 #define METHOD_GPIO_24XX 5
222 #ifdef CONFIG_ARCH_OMAP16XX
223 static struct gpio_bank gpio_bank_1610[5] = {
224 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
225 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
226 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
227 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
228 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
232 #ifdef CONFIG_ARCH_OMAP15XX
233 static struct gpio_bank gpio_bank_1510[2] = {
234 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
235 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
239 #ifdef CONFIG_ARCH_OMAP730
240 static struct gpio_bank gpio_bank_730[7] = {
241 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
242 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
243 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
244 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
245 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
246 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
247 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
251 #ifdef CONFIG_ARCH_OMAP850
252 static struct gpio_bank gpio_bank_850[7] = {
253 { OMAP_MPUIO_BASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
254 { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 },
255 { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 },
256 { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 },
257 { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_850 },
258 { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_850 },
259 { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_850 },
264 #ifdef CONFIG_ARCH_OMAP24XX
266 static struct gpio_bank gpio_bank_242x[4] = {
267 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
268 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
269 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
270 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
273 static struct gpio_bank gpio_bank_243x[5] = {
274 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
275 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
276 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
277 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
278 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
283 #ifdef CONFIG_ARCH_OMAP34XX
284 static struct gpio_bank gpio_bank_34xx[6] = {
285 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
286 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
287 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
288 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
289 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
290 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
295 #ifdef CONFIG_ARCH_OMAP4
296 static struct gpio_bank gpio_bank_44xx[6] = {
297 { OMAP44XX_GPIO1_BASE, INT_44XX_GPIO_BANK1, IH_GPIO_BASE, \
299 { OMAP44XX_GPIO2_BASE, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32, \
301 { OMAP44XX_GPIO3_BASE, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64, \
303 { OMAP44XX_GPIO4_BASE, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96, \
305 { OMAP44XX_GPIO5_BASE, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, \
307 { OMAP44XX_GPIO6_BASE, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, \
313 static struct gpio_bank *gpio_bank;
314 static int gpio_bank_count;
316 static inline struct gpio_bank *get_gpio_bank(int gpio)
318 if (cpu_is_omap15xx()) {
319 if (OMAP_GPIO_IS_MPUIO(gpio))
320 return &gpio_bank[0];
321 return &gpio_bank[1];
323 if (cpu_is_omap16xx()) {
324 if (OMAP_GPIO_IS_MPUIO(gpio))
325 return &gpio_bank[0];
326 return &gpio_bank[1 + (gpio >> 4)];
328 if (cpu_is_omap7xx()) {
329 if (OMAP_GPIO_IS_MPUIO(gpio))
330 return &gpio_bank[0];
331 return &gpio_bank[1 + (gpio >> 5)];
333 if (cpu_is_omap24xx())
334 return &gpio_bank[gpio >> 5];
335 if (cpu_is_omap34xx() || cpu_is_omap44xx())
336 return &gpio_bank[gpio >> 5];
341 static inline int get_gpio_index(int gpio)
343 if (cpu_is_omap7xx())
345 if (cpu_is_omap24xx())
347 if (cpu_is_omap34xx() || cpu_is_omap44xx())
352 static inline int gpio_valid(int gpio)
356 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
357 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
361 if (cpu_is_omap15xx() && gpio < 16)
363 if ((cpu_is_omap16xx()) && gpio < 64)
365 if (cpu_is_omap7xx() && gpio < 192)
367 if (cpu_is_omap24xx() && gpio < 128)
369 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
374 static int check_gpio(int gpio)
376 if (unlikely(gpio_valid(gpio)) < 0) {
377 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
384 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
386 void __iomem *reg = bank->base;
389 switch (bank->method) {
390 #ifdef CONFIG_ARCH_OMAP1
392 reg += OMAP_MPUIO_IO_CNTL;
395 #ifdef CONFIG_ARCH_OMAP15XX
396 case METHOD_GPIO_1510:
397 reg += OMAP1510_GPIO_DIR_CONTROL;
400 #ifdef CONFIG_ARCH_OMAP16XX
401 case METHOD_GPIO_1610:
402 reg += OMAP1610_GPIO_DIRECTION;
405 #ifdef CONFIG_ARCH_OMAP730
406 case METHOD_GPIO_730:
407 reg += OMAP730_GPIO_DIR_CONTROL;
410 #ifdef CONFIG_ARCH_OMAP850
411 case METHOD_GPIO_850:
412 reg += OMAP850_GPIO_DIR_CONTROL;
415 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
416 case METHOD_GPIO_24XX:
417 reg += OMAP24XX_GPIO_OE;
420 #if defined(CONFIG_ARCH_OMAP4)
421 case METHOD_GPIO_24XX:
422 reg += OMAP4_GPIO_OE;
429 l = __raw_readl(reg);
434 __raw_writel(l, reg);
437 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
439 void __iomem *reg = bank->base;
442 switch (bank->method) {
443 #ifdef CONFIG_ARCH_OMAP1
445 reg += OMAP_MPUIO_OUTPUT;
446 l = __raw_readl(reg);
453 #ifdef CONFIG_ARCH_OMAP15XX
454 case METHOD_GPIO_1510:
455 reg += OMAP1510_GPIO_DATA_OUTPUT;
456 l = __raw_readl(reg);
463 #ifdef CONFIG_ARCH_OMAP16XX
464 case METHOD_GPIO_1610:
466 reg += OMAP1610_GPIO_SET_DATAOUT;
468 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
472 #ifdef CONFIG_ARCH_OMAP730
473 case METHOD_GPIO_730:
474 reg += OMAP730_GPIO_DATA_OUTPUT;
475 l = __raw_readl(reg);
482 #ifdef CONFIG_ARCH_OMAP850
483 case METHOD_GPIO_850:
484 reg += OMAP850_GPIO_DATA_OUTPUT;
485 l = __raw_readl(reg);
492 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
493 case METHOD_GPIO_24XX:
495 reg += OMAP24XX_GPIO_SETDATAOUT;
497 reg += OMAP24XX_GPIO_CLEARDATAOUT;
501 #ifdef CONFIG_ARCH_OMAP4
502 case METHOD_GPIO_24XX:
504 reg += OMAP4_GPIO_SETDATAOUT;
506 reg += OMAP4_GPIO_CLEARDATAOUT;
514 __raw_writel(l, reg);
517 static int __omap_get_gpio_datain(int gpio)
519 struct gpio_bank *bank;
522 if (check_gpio(gpio) < 0)
524 bank = get_gpio_bank(gpio);
526 switch (bank->method) {
527 #ifdef CONFIG_ARCH_OMAP1
529 reg += OMAP_MPUIO_INPUT_LATCH;
532 #ifdef CONFIG_ARCH_OMAP15XX
533 case METHOD_GPIO_1510:
534 reg += OMAP1510_GPIO_DATA_INPUT;
537 #ifdef CONFIG_ARCH_OMAP16XX
538 case METHOD_GPIO_1610:
539 reg += OMAP1610_GPIO_DATAIN;
542 #ifdef CONFIG_ARCH_OMAP730
543 case METHOD_GPIO_730:
544 reg += OMAP730_GPIO_DATA_INPUT;
547 #ifdef CONFIG_ARCH_OMAP850
548 case METHOD_GPIO_850:
549 reg += OMAP850_GPIO_DATA_INPUT;
552 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
553 case METHOD_GPIO_24XX:
554 reg += OMAP24XX_GPIO_DATAIN;
557 #ifdef CONFIG_ARCH_OMAP4
558 case METHOD_GPIO_24XX:
559 reg += OMAP4_GPIO_DATAIN;
565 return (__raw_readl(reg)
566 & (1 << get_gpio_index(gpio))) != 0;
569 #define MOD_REG_BIT(reg, bit_mask, set) \
571 int l = __raw_readl(base + reg); \
572 if (set) l |= bit_mask; \
573 else l &= ~bit_mask; \
574 __raw_writel(l, base + reg); \
577 void omap_set_gpio_debounce(int gpio, int enable)
579 struct gpio_bank *bank;
582 u32 val, l = 1 << get_gpio_index(gpio);
584 if (cpu_class_is_omap1())
587 bank = get_gpio_bank(gpio);
589 #ifdef CONFIG_ARCH_OMAP4
590 reg += OMAP4_GPIO_DEBOUNCENABLE;
592 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
595 spin_lock_irqsave(&bank->lock, flags);
596 val = __raw_readl(reg);
598 if (enable && !(val & l))
600 else if (!enable && (val & l))
605 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
607 clk_enable(bank->dbck);
609 clk_disable(bank->dbck);
612 __raw_writel(val, reg);
614 spin_unlock_irqrestore(&bank->lock, flags);
616 EXPORT_SYMBOL(omap_set_gpio_debounce);
618 void omap_set_gpio_debounce_time(int gpio, int enc_time)
620 struct gpio_bank *bank;
623 if (cpu_class_is_omap1())
626 bank = get_gpio_bank(gpio);
630 #ifdef CONFIG_ARCH_OMAP4
631 reg += OMAP4_GPIO_DEBOUNCINGTIME;
633 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
635 __raw_writel(enc_time, reg);
637 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
639 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
640 defined(CONFIG_ARCH_OMAP4)
641 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
644 void __iomem *base = bank->base;
645 u32 gpio_bit = 1 << gpio;
648 if (cpu_is_omap44xx()) {
649 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
650 trigger & IRQ_TYPE_LEVEL_LOW);
651 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
652 trigger & IRQ_TYPE_LEVEL_HIGH);
653 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
654 trigger & IRQ_TYPE_EDGE_RISING);
655 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
656 trigger & IRQ_TYPE_EDGE_FALLING);
658 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
659 trigger & IRQ_TYPE_LEVEL_LOW);
660 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
661 trigger & IRQ_TYPE_LEVEL_HIGH);
662 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
663 trigger & IRQ_TYPE_EDGE_RISING);
664 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
665 trigger & IRQ_TYPE_EDGE_FALLING);
667 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
668 if (cpu_is_omap44xx()) {
670 __raw_writel(1 << gpio, bank->base+
671 OMAP4_GPIO_IRQWAKEN0);
673 val = __raw_readl(bank->base +
674 OMAP4_GPIO_IRQWAKEN0);
675 __raw_writel(val & (~(1 << gpio)), bank->base +
676 OMAP4_GPIO_IRQWAKEN0);
680 __raw_writel(1 << gpio, bank->base
681 + OMAP24XX_GPIO_SETWKUENA);
683 __raw_writel(1 << gpio, bank->base
684 + OMAP24XX_GPIO_CLEARWKUENA);
688 bank->enabled_non_wakeup_gpios |= gpio_bit;
690 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
693 if (cpu_is_omap44xx()) {
695 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
696 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
699 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
700 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
705 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
707 void __iomem *reg = bank->base;
710 switch (bank->method) {
711 #ifdef CONFIG_ARCH_OMAP1
713 reg += OMAP_MPUIO_GPIO_INT_EDGE;
714 l = __raw_readl(reg);
715 if (trigger & IRQ_TYPE_EDGE_RISING)
717 else if (trigger & IRQ_TYPE_EDGE_FALLING)
723 #ifdef CONFIG_ARCH_OMAP15XX
724 case METHOD_GPIO_1510:
725 reg += OMAP1510_GPIO_INT_CONTROL;
726 l = __raw_readl(reg);
727 if (trigger & IRQ_TYPE_EDGE_RISING)
729 else if (trigger & IRQ_TYPE_EDGE_FALLING)
735 #ifdef CONFIG_ARCH_OMAP16XX
736 case METHOD_GPIO_1610:
738 reg += OMAP1610_GPIO_EDGE_CTRL2;
740 reg += OMAP1610_GPIO_EDGE_CTRL1;
742 l = __raw_readl(reg);
743 l &= ~(3 << (gpio << 1));
744 if (trigger & IRQ_TYPE_EDGE_RISING)
745 l |= 2 << (gpio << 1);
746 if (trigger & IRQ_TYPE_EDGE_FALLING)
747 l |= 1 << (gpio << 1);
749 /* Enable wake-up during idle for dynamic tick */
750 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
752 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
755 #ifdef CONFIG_ARCH_OMAP730
756 case METHOD_GPIO_730:
757 reg += OMAP730_GPIO_INT_CONTROL;
758 l = __raw_readl(reg);
759 if (trigger & IRQ_TYPE_EDGE_RISING)
761 else if (trigger & IRQ_TYPE_EDGE_FALLING)
767 #ifdef CONFIG_ARCH_OMAP850
768 case METHOD_GPIO_850:
769 reg += OMAP850_GPIO_INT_CONTROL;
770 l = __raw_readl(reg);
771 if (trigger & IRQ_TYPE_EDGE_RISING)
773 else if (trigger & IRQ_TYPE_EDGE_FALLING)
779 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
780 defined(CONFIG_ARCH_OMAP4)
781 case METHOD_GPIO_24XX:
782 set_24xx_gpio_triggering(bank, gpio, trigger);
788 __raw_writel(l, reg);
794 static int gpio_irq_type(unsigned irq, unsigned type)
796 struct gpio_bank *bank;
801 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
802 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
804 gpio = irq - IH_GPIO_BASE;
806 if (check_gpio(gpio) < 0)
809 if (type & ~IRQ_TYPE_SENSE_MASK)
812 /* OMAP1 allows only only edge triggering */
813 if (!cpu_class_is_omap2()
814 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
817 bank = get_irq_chip_data(irq);
818 spin_lock_irqsave(&bank->lock, flags);
819 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
821 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
822 irq_desc[irq].status |= type;
824 spin_unlock_irqrestore(&bank->lock, flags);
826 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
827 __set_irq_handler_unlocked(irq, handle_level_irq);
828 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
829 __set_irq_handler_unlocked(irq, handle_edge_irq);
834 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
836 void __iomem *reg = bank->base;
838 switch (bank->method) {
839 #ifdef CONFIG_ARCH_OMAP1
841 /* MPUIO irqstatus is reset by reading the status register,
842 * so do nothing here */
845 #ifdef CONFIG_ARCH_OMAP15XX
846 case METHOD_GPIO_1510:
847 reg += OMAP1510_GPIO_INT_STATUS;
850 #ifdef CONFIG_ARCH_OMAP16XX
851 case METHOD_GPIO_1610:
852 reg += OMAP1610_GPIO_IRQSTATUS1;
855 #ifdef CONFIG_ARCH_OMAP730
856 case METHOD_GPIO_730:
857 reg += OMAP730_GPIO_INT_STATUS;
860 #ifdef CONFIG_ARCH_OMAP850
861 case METHOD_GPIO_850:
862 reg += OMAP850_GPIO_INT_STATUS;
865 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
866 case METHOD_GPIO_24XX:
867 reg += OMAP24XX_GPIO_IRQSTATUS1;
870 #if defined(CONFIG_ARCH_OMAP4)
871 case METHOD_GPIO_24XX:
872 reg += OMAP4_GPIO_IRQSTATUS0;
879 __raw_writel(gpio_mask, reg);
881 /* Workaround for clearing DSP GPIO interrupts to allow retention */
882 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
883 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
885 #if defined(CONFIG_ARCH_OMAP4)
886 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
888 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
889 __raw_writel(gpio_mask, reg);
891 /* Flush posted write for the irq status to avoid spurious interrupts */
896 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
898 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
901 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
903 void __iomem *reg = bank->base;
908 switch (bank->method) {
909 #ifdef CONFIG_ARCH_OMAP1
911 reg += OMAP_MPUIO_GPIO_MASKIT;
916 #ifdef CONFIG_ARCH_OMAP15XX
917 case METHOD_GPIO_1510:
918 reg += OMAP1510_GPIO_INT_MASK;
923 #ifdef CONFIG_ARCH_OMAP16XX
924 case METHOD_GPIO_1610:
925 reg += OMAP1610_GPIO_IRQENABLE1;
929 #ifdef CONFIG_ARCH_OMAP730
930 case METHOD_GPIO_730:
931 reg += OMAP730_GPIO_INT_MASK;
936 #ifdef CONFIG_ARCH_OMAP850
937 case METHOD_GPIO_850:
938 reg += OMAP850_GPIO_INT_MASK;
943 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
944 case METHOD_GPIO_24XX:
945 reg += OMAP24XX_GPIO_IRQENABLE1;
949 #if defined(CONFIG_ARCH_OMAP4)
950 case METHOD_GPIO_24XX:
951 reg += OMAP4_GPIO_IRQSTATUSSET0;
960 l = __raw_readl(reg);
967 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
969 void __iomem *reg = bank->base;
972 switch (bank->method) {
973 #ifdef CONFIG_ARCH_OMAP1
975 reg += OMAP_MPUIO_GPIO_MASKIT;
976 l = __raw_readl(reg);
983 #ifdef CONFIG_ARCH_OMAP15XX
984 case METHOD_GPIO_1510:
985 reg += OMAP1510_GPIO_INT_MASK;
986 l = __raw_readl(reg);
993 #ifdef CONFIG_ARCH_OMAP16XX
994 case METHOD_GPIO_1610:
996 reg += OMAP1610_GPIO_SET_IRQENABLE1;
998 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
1002 #ifdef CONFIG_ARCH_OMAP730
1003 case METHOD_GPIO_730:
1004 reg += OMAP730_GPIO_INT_MASK;
1005 l = __raw_readl(reg);
1012 #ifdef CONFIG_ARCH_OMAP850
1013 case METHOD_GPIO_850:
1014 reg += OMAP850_GPIO_INT_MASK;
1015 l = __raw_readl(reg);
1022 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1023 case METHOD_GPIO_24XX:
1025 reg += OMAP24XX_GPIO_SETIRQENABLE1;
1027 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
1031 #ifdef CONFIG_ARCH_OMAP4
1032 case METHOD_GPIO_24XX:
1034 reg += OMAP4_GPIO_IRQSTATUSSET0;
1036 reg += OMAP4_GPIO_IRQSTATUSCLR0;
1044 __raw_writel(l, reg);
1047 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
1049 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
1053 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
1054 * 1510 does not seem to have a wake-up register. If JTAG is connected
1055 * to the target, system will wake up always on GPIO events. While
1056 * system is running all registered GPIO interrupts need to have wake-up
1057 * enabled. When system is suspended, only selected GPIO interrupts need
1058 * to have wake-up enabled.
1060 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1062 unsigned long flags;
1064 switch (bank->method) {
1065 #ifdef CONFIG_ARCH_OMAP16XX
1067 case METHOD_GPIO_1610:
1068 spin_lock_irqsave(&bank->lock, flags);
1070 bank->suspend_wakeup |= (1 << gpio);
1072 bank->suspend_wakeup &= ~(1 << gpio);
1073 spin_unlock_irqrestore(&bank->lock, flags);
1076 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1077 defined(CONFIG_ARCH_OMAP4)
1078 case METHOD_GPIO_24XX:
1079 if (bank->non_wakeup_gpios & (1 << gpio)) {
1080 printk(KERN_ERR "Unable to modify wakeup on "
1081 "non-wakeup GPIO%d\n",
1082 (bank - gpio_bank) * 32 + gpio);
1085 spin_lock_irqsave(&bank->lock, flags);
1087 bank->suspend_wakeup |= (1 << gpio);
1089 bank->suspend_wakeup &= ~(1 << gpio);
1090 spin_unlock_irqrestore(&bank->lock, flags);
1094 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1100 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1102 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1103 _set_gpio_irqenable(bank, gpio, 0);
1104 _clear_gpio_irqstatus(bank, gpio);
1105 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1108 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1109 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1111 unsigned int gpio = irq - IH_GPIO_BASE;
1112 struct gpio_bank *bank;
1115 if (check_gpio(gpio) < 0)
1117 bank = get_irq_chip_data(irq);
1118 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1123 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1125 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1126 unsigned long flags;
1128 spin_lock_irqsave(&bank->lock, flags);
1130 /* Set trigger to none. You need to enable the desired trigger with
1131 * request_irq() or set_irq_type().
1133 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1135 #ifdef CONFIG_ARCH_OMAP15XX
1136 if (bank->method == METHOD_GPIO_1510) {
1139 /* Claim the pin for MPU */
1140 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1141 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1144 spin_unlock_irqrestore(&bank->lock, flags);
1149 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1151 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1152 unsigned long flags;
1154 spin_lock_irqsave(&bank->lock, flags);
1155 #ifdef CONFIG_ARCH_OMAP16XX
1156 if (bank->method == METHOD_GPIO_1610) {
1157 /* Disable wake-up during idle for dynamic tick */
1158 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1159 __raw_writel(1 << offset, reg);
1162 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1163 defined(CONFIG_ARCH_OMAP4)
1164 if (bank->method == METHOD_GPIO_24XX) {
1165 /* Disable wake-up during idle for dynamic tick */
1166 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1167 __raw_writel(1 << offset, reg);
1170 _reset_gpio(bank, bank->chip.base + offset);
1171 spin_unlock_irqrestore(&bank->lock, flags);
1175 * We need to unmask the GPIO bank interrupt as soon as possible to
1176 * avoid missing GPIO interrupts for other lines in the bank.
1177 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1178 * in the bank to avoid missing nested interrupts for a GPIO line.
1179 * If we wait to unmask individual GPIO lines in the bank after the
1180 * line's interrupt handler has been run, we may miss some nested
1183 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1185 void __iomem *isr_reg = NULL;
1187 unsigned int gpio_irq;
1188 struct gpio_bank *bank;
1192 desc->chip->ack(irq);
1194 bank = get_irq_data(irq);
1195 #ifdef CONFIG_ARCH_OMAP1
1196 if (bank->method == METHOD_MPUIO)
1197 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1199 #ifdef CONFIG_ARCH_OMAP15XX
1200 if (bank->method == METHOD_GPIO_1510)
1201 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1203 #if defined(CONFIG_ARCH_OMAP16XX)
1204 if (bank->method == METHOD_GPIO_1610)
1205 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1207 #ifdef CONFIG_ARCH_OMAP730
1208 if (bank->method == METHOD_GPIO_730)
1209 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1211 #ifdef CONFIG_ARCH_OMAP850
1212 if (bank->method == METHOD_GPIO_850)
1213 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
1215 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1216 if (bank->method == METHOD_GPIO_24XX)
1217 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1219 #if defined(CONFIG_ARCH_OMAP4)
1220 if (bank->method == METHOD_GPIO_24XX)
1221 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1224 u32 isr_saved, level_mask = 0;
1227 enabled = _get_gpio_irqbank_mask(bank);
1228 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1230 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1233 if (cpu_class_is_omap2()) {
1234 level_mask = bank->level_mask & enabled;
1237 /* clear edge sensitive interrupts before handler(s) are
1238 called so that we don't miss any interrupt occurred while
1240 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1241 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1242 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1244 /* if there is only edge sensitive GPIO pin interrupts
1245 configured, we could unmask GPIO bank interrupt immediately */
1246 if (!level_mask && !unmasked) {
1248 desc->chip->unmask(irq);
1256 gpio_irq = bank->virtual_irq_start;
1257 for (; isr != 0; isr >>= 1, gpio_irq++) {
1261 generic_handle_irq(gpio_irq);
1264 /* if bank has any level sensitive GPIO pin interrupt
1265 configured, we must unmask the bank interrupt only after
1266 handler(s) are executed in order to avoid spurious bank
1269 desc->chip->unmask(irq);
1273 static void gpio_irq_shutdown(unsigned int irq)
1275 unsigned int gpio = irq - IH_GPIO_BASE;
1276 struct gpio_bank *bank = get_irq_chip_data(irq);
1278 _reset_gpio(bank, gpio);
1281 static void gpio_ack_irq(unsigned int irq)
1283 unsigned int gpio = irq - IH_GPIO_BASE;
1284 struct gpio_bank *bank = get_irq_chip_data(irq);
1286 _clear_gpio_irqstatus(bank, gpio);
1289 static void gpio_mask_irq(unsigned int irq)
1291 unsigned int gpio = irq - IH_GPIO_BASE;
1292 struct gpio_bank *bank = get_irq_chip_data(irq);
1294 _set_gpio_irqenable(bank, gpio, 0);
1295 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1298 static void gpio_unmask_irq(unsigned int irq)
1300 unsigned int gpio = irq - IH_GPIO_BASE;
1301 struct gpio_bank *bank = get_irq_chip_data(irq);
1302 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1303 struct irq_desc *desc = irq_to_desc(irq);
1304 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1307 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1309 /* For level-triggered GPIOs, the clearing must be done after
1310 * the HW source is cleared, thus after the handler has run */
1311 if (bank->level_mask & irq_mask) {
1312 _set_gpio_irqenable(bank, gpio, 0);
1313 _clear_gpio_irqstatus(bank, gpio);
1316 _set_gpio_irqenable(bank, gpio, 1);
1319 static struct irq_chip gpio_irq_chip = {
1321 .shutdown = gpio_irq_shutdown,
1322 .ack = gpio_ack_irq,
1323 .mask = gpio_mask_irq,
1324 .unmask = gpio_unmask_irq,
1325 .set_type = gpio_irq_type,
1326 .set_wake = gpio_wake_enable,
1329 /*---------------------------------------------------------------------*/
1331 #ifdef CONFIG_ARCH_OMAP1
1333 /* MPUIO uses the always-on 32k clock */
1335 static void mpuio_ack_irq(unsigned int irq)
1337 /* The ISR is reset automatically, so do nothing here. */
1340 static void mpuio_mask_irq(unsigned int irq)
1342 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1343 struct gpio_bank *bank = get_irq_chip_data(irq);
1345 _set_gpio_irqenable(bank, gpio, 0);
1348 static void mpuio_unmask_irq(unsigned int irq)
1350 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1351 struct gpio_bank *bank = get_irq_chip_data(irq);
1353 _set_gpio_irqenable(bank, gpio, 1);
1356 static struct irq_chip mpuio_irq_chip = {
1358 .ack = mpuio_ack_irq,
1359 .mask = mpuio_mask_irq,
1360 .unmask = mpuio_unmask_irq,
1361 .set_type = gpio_irq_type,
1362 #ifdef CONFIG_ARCH_OMAP16XX
1363 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1364 .set_wake = gpio_wake_enable,
1369 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1372 #ifdef CONFIG_ARCH_OMAP16XX
1374 #include <linux/platform_device.h>
1376 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1378 struct gpio_bank *bank = platform_get_drvdata(pdev);
1379 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1380 unsigned long flags;
1382 spin_lock_irqsave(&bank->lock, flags);
1383 bank->saved_wakeup = __raw_readl(mask_reg);
1384 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1385 spin_unlock_irqrestore(&bank->lock, flags);
1390 static int omap_mpuio_resume_early(struct platform_device *pdev)
1392 struct gpio_bank *bank = platform_get_drvdata(pdev);
1393 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1394 unsigned long flags;
1396 spin_lock_irqsave(&bank->lock, flags);
1397 __raw_writel(bank->saved_wakeup, mask_reg);
1398 spin_unlock_irqrestore(&bank->lock, flags);
1403 /* use platform_driver for this, now that there's no longer any
1404 * point to sys_device (other than not disturbing old code).
1406 static struct platform_driver omap_mpuio_driver = {
1407 .suspend_late = omap_mpuio_suspend_late,
1408 .resume_early = omap_mpuio_resume_early,
1414 static struct platform_device omap_mpuio_device = {
1418 .driver = &omap_mpuio_driver.driver,
1420 /* could list the /proc/iomem resources */
1423 static inline void mpuio_init(void)
1425 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1427 if (platform_driver_register(&omap_mpuio_driver) == 0)
1428 (void) platform_device_register(&omap_mpuio_device);
1432 static inline void mpuio_init(void) {}
1437 extern struct irq_chip mpuio_irq_chip;
1439 #define bank_is_mpuio(bank) 0
1440 static inline void mpuio_init(void) {}
1444 /*---------------------------------------------------------------------*/
1446 /* REVISIT these are stupid implementations! replace by ones that
1447 * don't switch on METHOD_* and which mostly avoid spinlocks
1450 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1452 struct gpio_bank *bank;
1453 unsigned long flags;
1455 bank = container_of(chip, struct gpio_bank, chip);
1456 spin_lock_irqsave(&bank->lock, flags);
1457 _set_gpio_direction(bank, offset, 1);
1458 spin_unlock_irqrestore(&bank->lock, flags);
1462 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1464 return __omap_get_gpio_datain(chip->base + offset);
1467 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1469 struct gpio_bank *bank;
1470 unsigned long flags;
1472 bank = container_of(chip, struct gpio_bank, chip);
1473 spin_lock_irqsave(&bank->lock, flags);
1474 _set_gpio_dataout(bank, offset, value);
1475 _set_gpio_direction(bank, offset, 0);
1476 spin_unlock_irqrestore(&bank->lock, flags);
1480 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1482 struct gpio_bank *bank;
1483 unsigned long flags;
1485 bank = container_of(chip, struct gpio_bank, chip);
1486 spin_lock_irqsave(&bank->lock, flags);
1487 _set_gpio_dataout(bank, offset, value);
1488 spin_unlock_irqrestore(&bank->lock, flags);
1491 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1493 struct gpio_bank *bank;
1495 bank = container_of(chip, struct gpio_bank, chip);
1496 return bank->virtual_irq_start + offset;
1499 /*---------------------------------------------------------------------*/
1501 static int initialized;
1502 #if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4))
1503 static struct clk * gpio_ick;
1506 #if defined(CONFIG_ARCH_OMAP2)
1507 static struct clk * gpio_fck;
1510 #if defined(CONFIG_ARCH_OMAP2430)
1511 static struct clk * gpio5_ick;
1512 static struct clk * gpio5_fck;
1515 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1516 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1519 /* This lock class tells lockdep that GPIO irqs are in a different
1520 * category than their parents, so it won't report false recursion.
1522 static struct lock_class_key gpio_lock_class;
1524 static int __init _omap_gpio_init(void)
1528 struct gpio_bank *bank;
1533 #if defined(CONFIG_ARCH_OMAP1)
1534 if (cpu_is_omap15xx()) {
1535 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1536 if (IS_ERR(gpio_ick))
1537 printk("Could not get arm_gpio_ck\n");
1539 clk_enable(gpio_ick);
1542 #if defined(CONFIG_ARCH_OMAP2)
1543 if (cpu_class_is_omap2()) {
1544 gpio_ick = clk_get(NULL, "gpios_ick");
1545 if (IS_ERR(gpio_ick))
1546 printk("Could not get gpios_ick\n");
1548 clk_enable(gpio_ick);
1549 gpio_fck = clk_get(NULL, "gpios_fck");
1550 if (IS_ERR(gpio_fck))
1551 printk("Could not get gpios_fck\n");
1553 clk_enable(gpio_fck);
1556 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1558 #if defined(CONFIG_ARCH_OMAP2430)
1559 if (cpu_is_omap2430()) {
1560 gpio5_ick = clk_get(NULL, "gpio5_ick");
1561 if (IS_ERR(gpio5_ick))
1562 printk("Could not get gpio5_ick\n");
1564 clk_enable(gpio5_ick);
1565 gpio5_fck = clk_get(NULL, "gpio5_fck");
1566 if (IS_ERR(gpio5_fck))
1567 printk("Could not get gpio5_fck\n");
1569 clk_enable(gpio5_fck);
1575 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1576 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1577 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1578 sprintf(clk_name, "gpio%d_ick", i + 1);
1579 gpio_iclks[i] = clk_get(NULL, clk_name);
1580 if (IS_ERR(gpio_iclks[i]))
1581 printk(KERN_ERR "Could not get %s\n", clk_name);
1583 clk_enable(gpio_iclks[i]);
1589 #ifdef CONFIG_ARCH_OMAP15XX
1590 if (cpu_is_omap15xx()) {
1591 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1592 gpio_bank_count = 2;
1593 gpio_bank = gpio_bank_1510;
1596 #if defined(CONFIG_ARCH_OMAP16XX)
1597 if (cpu_is_omap16xx()) {
1600 gpio_bank_count = 5;
1601 gpio_bank = gpio_bank_1610;
1602 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1603 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1604 (rev >> 4) & 0x0f, rev & 0x0f);
1607 #ifdef CONFIG_ARCH_OMAP730
1608 if (cpu_is_omap730()) {
1609 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1610 gpio_bank_count = 7;
1611 gpio_bank = gpio_bank_730;
1614 #ifdef CONFIG_ARCH_OMAP850
1615 if (cpu_is_omap850()) {
1616 printk(KERN_INFO "OMAP850 GPIO hardware\n");
1617 gpio_bank_count = 7;
1618 gpio_bank = gpio_bank_850;
1622 #ifdef CONFIG_ARCH_OMAP24XX
1623 if (cpu_is_omap242x()) {
1626 gpio_bank_count = 4;
1627 gpio_bank = gpio_bank_242x;
1628 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1629 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1630 (rev >> 4) & 0x0f, rev & 0x0f);
1632 if (cpu_is_omap243x()) {
1635 gpio_bank_count = 5;
1636 gpio_bank = gpio_bank_243x;
1637 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1638 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1639 (rev >> 4) & 0x0f, rev & 0x0f);
1642 #ifdef CONFIG_ARCH_OMAP34XX
1643 if (cpu_is_omap34xx()) {
1646 gpio_bank_count = OMAP34XX_NR_GPIOS;
1647 gpio_bank = gpio_bank_34xx;
1648 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1649 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1650 (rev >> 4) & 0x0f, rev & 0x0f);
1653 #ifdef CONFIG_ARCH_OMAP4
1654 if (cpu_is_omap44xx()) {
1657 gpio_bank_count = OMAP34XX_NR_GPIOS;
1658 gpio_bank = gpio_bank_44xx;
1659 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1660 printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
1661 (rev >> 4) & 0x0f, rev & 0x0f);
1664 for (i = 0; i < gpio_bank_count; i++) {
1665 int j, gpio_count = 16;
1667 bank = &gpio_bank[i];
1668 spin_lock_init(&bank->lock);
1669 if (bank_is_mpuio(bank))
1670 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1671 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1672 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1673 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1675 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1676 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1677 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1678 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1680 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) {
1681 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1682 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1684 gpio_count = 32; /* 730 has 32-bit GPIOs */
1687 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1688 defined(CONFIG_ARCH_OMAP4)
1689 if (bank->method == METHOD_GPIO_24XX) {
1690 static const u32 non_wakeup_gpios[] = {
1691 0xe203ffc0, 0x08700040
1693 if (cpu_is_omap44xx()) {
1694 __raw_writel(0xffffffff, bank->base +
1695 OMAP4_GPIO_IRQSTATUSCLR0);
1696 __raw_writew(0x0015, bank->base +
1697 OMAP4_GPIO_SYSCONFIG);
1698 __raw_writel(0x00000000, bank->base +
1699 OMAP4_GPIO_DEBOUNCENABLE);
1700 /* Initialize interface clock ungated, module enabled */
1701 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1703 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1704 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1705 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1706 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
1708 /* Initialize interface clock ungated, module enabled */
1709 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1711 if (i < ARRAY_SIZE(non_wakeup_gpios))
1712 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1716 /* REVISIT eventually switch from OMAP-specific gpio structs
1717 * over to the generic ones
1719 bank->chip.request = omap_gpio_request;
1720 bank->chip.free = omap_gpio_free;
1721 bank->chip.direction_input = gpio_input;
1722 bank->chip.get = gpio_get;
1723 bank->chip.direction_output = gpio_output;
1724 bank->chip.set = gpio_set;
1725 bank->chip.to_irq = gpio_2irq;
1726 if (bank_is_mpuio(bank)) {
1727 bank->chip.label = "mpuio";
1728 #ifdef CONFIG_ARCH_OMAP16XX
1729 bank->chip.dev = &omap_mpuio_device.dev;
1731 bank->chip.base = OMAP_MPUIO(0);
1733 bank->chip.label = "gpio";
1734 bank->chip.base = gpio;
1737 bank->chip.ngpio = gpio_count;
1739 gpiochip_add(&bank->chip);
1741 for (j = bank->virtual_irq_start;
1742 j < bank->virtual_irq_start + gpio_count; j++) {
1743 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1744 set_irq_chip_data(j, bank);
1745 if (bank_is_mpuio(bank))
1746 set_irq_chip(j, &mpuio_irq_chip);
1748 set_irq_chip(j, &gpio_irq_chip);
1749 set_irq_handler(j, handle_simple_irq);
1750 set_irq_flags(j, IRQF_VALID);
1752 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1753 set_irq_data(bank->irq, bank);
1755 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1756 sprintf(clk_name, "gpio%d_dbck", i + 1);
1757 bank->dbck = clk_get(NULL, clk_name);
1758 if (IS_ERR(bank->dbck))
1759 printk(KERN_ERR "Could not get %s\n", clk_name);
1763 /* Enable system clock for GPIO module.
1764 * The CAM_CLK_CTRL *is* really the right place. */
1765 if (cpu_is_omap16xx())
1766 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1768 /* Enable autoidle for the OCP interface */
1769 if (cpu_is_omap24xx())
1770 omap_writel(1 << 0, 0x48019010);
1771 if (cpu_is_omap34xx())
1772 omap_writel(1 << 0, 0x48306814);
1777 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1778 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
1779 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1783 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1786 for (i = 0; i < gpio_bank_count; i++) {
1787 struct gpio_bank *bank = &gpio_bank[i];
1788 void __iomem *wake_status;
1789 void __iomem *wake_clear;
1790 void __iomem *wake_set;
1791 unsigned long flags;
1793 switch (bank->method) {
1794 #ifdef CONFIG_ARCH_OMAP16XX
1795 case METHOD_GPIO_1610:
1796 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1797 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1798 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1801 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1802 case METHOD_GPIO_24XX:
1803 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1804 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1805 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1808 #ifdef CONFIG_ARCH_OMAP4
1809 case METHOD_GPIO_24XX:
1810 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1811 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1812 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1819 spin_lock_irqsave(&bank->lock, flags);
1820 bank->saved_wakeup = __raw_readl(wake_status);
1821 __raw_writel(0xffffffff, wake_clear);
1822 __raw_writel(bank->suspend_wakeup, wake_set);
1823 spin_unlock_irqrestore(&bank->lock, flags);
1829 static int omap_gpio_resume(struct sys_device *dev)
1833 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1836 for (i = 0; i < gpio_bank_count; i++) {
1837 struct gpio_bank *bank = &gpio_bank[i];
1838 void __iomem *wake_clear;
1839 void __iomem *wake_set;
1840 unsigned long flags;
1842 switch (bank->method) {
1843 #ifdef CONFIG_ARCH_OMAP16XX
1844 case METHOD_GPIO_1610:
1845 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1846 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1849 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1850 case METHOD_GPIO_24XX:
1851 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1852 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1855 #ifdef CONFIG_ARCH_OMAP4
1856 case METHOD_GPIO_24XX:
1857 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1858 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1865 spin_lock_irqsave(&bank->lock, flags);
1866 __raw_writel(0xffffffff, wake_clear);
1867 __raw_writel(bank->saved_wakeup, wake_set);
1868 spin_unlock_irqrestore(&bank->lock, flags);
1874 static struct sysdev_class omap_gpio_sysclass = {
1876 .suspend = omap_gpio_suspend,
1877 .resume = omap_gpio_resume,
1880 static struct sys_device omap_gpio_device = {
1882 .cls = &omap_gpio_sysclass,
1887 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1888 defined(CONFIG_ARCH_OMAP4)
1890 static int workaround_enabled;
1892 void omap2_gpio_prepare_for_retention(void)
1896 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1897 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1898 for (i = 0; i < gpio_bank_count; i++) {
1899 struct gpio_bank *bank = &gpio_bank[i];
1902 if (!(bank->enabled_non_wakeup_gpios))
1904 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1905 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1906 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1907 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1909 #ifdef CONFIG_ARCH_OMAP4
1910 bank->saved_datain = __raw_readl(bank->base +
1912 l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
1913 l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
1915 bank->saved_fallingdetect = l1;
1916 bank->saved_risingdetect = l2;
1917 l1 &= ~bank->enabled_non_wakeup_gpios;
1918 l2 &= ~bank->enabled_non_wakeup_gpios;
1919 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1920 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1921 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1923 #ifdef CONFIG_ARCH_OMAP4
1924 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1925 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1930 workaround_enabled = 0;
1933 workaround_enabled = 1;
1936 void omap2_gpio_resume_after_retention(void)
1940 if (!workaround_enabled)
1942 for (i = 0; i < gpio_bank_count; i++) {
1943 struct gpio_bank *bank = &gpio_bank[i];
1946 if (!(bank->enabled_non_wakeup_gpios))
1948 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1949 __raw_writel(bank->saved_fallingdetect,
1950 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1951 __raw_writel(bank->saved_risingdetect,
1952 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1953 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1955 #ifdef CONFIG_ARCH_OMAP4
1956 __raw_writel(bank->saved_fallingdetect,
1957 bank->base + OMAP4_GPIO_FALLINGDETECT);
1958 __raw_writel(bank->saved_risingdetect,
1959 bank->base + OMAP4_GPIO_RISINGDETECT);
1960 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1962 /* Check if any of the non-wakeup interrupt GPIOs have changed
1963 * state. If so, generate an IRQ by software. This is
1964 * horribly racy, but it's the best we can do to work around
1965 * this silicon bug. */
1966 l ^= bank->saved_datain;
1967 l &= bank->non_wakeup_gpios;
1970 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1971 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1972 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1973 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1974 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1975 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1976 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1978 #ifdef CONFIG_ARCH_OMAP4
1979 old0 = __raw_readl(bank->base +
1980 OMAP4_GPIO_LEVELDETECT0);
1981 old1 = __raw_readl(bank->base +
1982 OMAP4_GPIO_LEVELDETECT1);
1983 __raw_writel(old0 | l, bank->base +
1984 OMAP4_GPIO_LEVELDETECT0);
1985 __raw_writel(old1 | l, bank->base +
1986 OMAP4_GPIO_LEVELDETECT1);
1987 __raw_writel(old0, bank->base +
1988 OMAP4_GPIO_LEVELDETECT0);
1989 __raw_writel(old1, bank->base +
1990 OMAP4_GPIO_LEVELDETECT1);
2000 * This may get called early from board specific init
2001 * for boards that have interrupts routed via FPGA.
2003 int __init omap_gpio_init(void)
2006 return _omap_gpio_init();
2011 static int __init omap_gpio_sysinit(void)
2016 ret = _omap_gpio_init();
2020 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2021 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2022 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2024 ret = sysdev_class_register(&omap_gpio_sysclass);
2026 ret = sysdev_register(&omap_gpio_device);
2034 arch_initcall(omap_gpio_sysinit);
2037 #ifdef CONFIG_DEBUG_FS
2039 #include <linux/debugfs.h>
2040 #include <linux/seq_file.h>
2042 static int gpio_is_input(struct gpio_bank *bank, int mask)
2044 void __iomem *reg = bank->base;
2046 switch (bank->method) {
2048 reg += OMAP_MPUIO_IO_CNTL;
2050 case METHOD_GPIO_1510:
2051 reg += OMAP1510_GPIO_DIR_CONTROL;
2053 case METHOD_GPIO_1610:
2054 reg += OMAP1610_GPIO_DIRECTION;
2056 case METHOD_GPIO_730:
2057 reg += OMAP730_GPIO_DIR_CONTROL;
2059 case METHOD_GPIO_850:
2060 reg += OMAP850_GPIO_DIR_CONTROL;
2062 case METHOD_GPIO_24XX:
2063 reg += OMAP24XX_GPIO_OE;
2066 return __raw_readl(reg) & mask;
2070 static int dbg_gpio_show(struct seq_file *s, void *unused)
2072 unsigned i, j, gpio;
2074 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
2075 struct gpio_bank *bank = gpio_bank + i;
2076 unsigned bankwidth = 16;
2079 if (bank_is_mpuio(bank))
2080 gpio = OMAP_MPUIO(0);
2081 else if (cpu_class_is_omap2() || cpu_is_omap730() ||
2085 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
2086 unsigned irq, value, is_in, irqstat;
2089 label = gpiochip_is_requested(&bank->chip, j);
2093 irq = bank->virtual_irq_start + j;
2094 value = gpio_get_value(gpio);
2095 is_in = gpio_is_input(bank, mask);
2097 if (bank_is_mpuio(bank))
2098 seq_printf(s, "MPUIO %2d ", j);
2100 seq_printf(s, "GPIO %3d ", gpio);
2101 seq_printf(s, "(%-20.20s): %s %s",
2103 is_in ? "in " : "out",
2104 value ? "hi" : "lo");
2106 /* FIXME for at least omap2, show pullup/pulldown state */
2108 irqstat = irq_desc[irq].status;
2109 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2110 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2111 if (is_in && ((bank->suspend_wakeup & mask)
2112 || irqstat & IRQ_TYPE_SENSE_MASK)) {
2113 char *trigger = NULL;
2115 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
2116 case IRQ_TYPE_EDGE_FALLING:
2117 trigger = "falling";
2119 case IRQ_TYPE_EDGE_RISING:
2122 case IRQ_TYPE_EDGE_BOTH:
2123 trigger = "bothedge";
2125 case IRQ_TYPE_LEVEL_LOW:
2128 case IRQ_TYPE_LEVEL_HIGH:
2135 seq_printf(s, ", irq-%d %-8s%s",
2137 (bank->suspend_wakeup & mask)
2141 seq_printf(s, "\n");
2144 if (bank_is_mpuio(bank)) {
2145 seq_printf(s, "\n");
2152 static int dbg_gpio_open(struct inode *inode, struct file *file)
2154 return single_open(file, dbg_gpio_show, &inode->i_private);
2157 static const struct file_operations debug_fops = {
2158 .open = dbg_gpio_open,
2160 .llseek = seq_lseek,
2161 .release = single_release,
2164 static int __init omap_gpio_debuginit(void)
2166 (void) debugfs_create_file("omap_gpio", S_IRUGO,
2167 NULL, NULL, &debug_fops);
2170 late_initcall(omap_gpio_debuginit);