SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/arm/plat-omap/dmtimer.c

   1 /*
   2  * linux/arch/arm/plat-omap/dmtimer.c
   3  *
   4  * OMAP Dual-Mode Timers
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * OMAP2 support by Juha Yrjola
   8  * API improvements and OMAP2 clock framework support by Timo Teras
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License as published by the
  12  * Free Software Foundation; either version 2 of the License, or (at your
  13  * option) any later version.
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  17  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  18  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  21  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  *
  24  * You should have received a copy of the  GNU General Public License along
  25  * with this program; if not, write  to the Free Software Foundation, Inc.,
  26  * 675 Mass Ave, Cambridge, MA 02139, USA.
  27  */
  28
  29 #include <linux/init.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/errno.h>
  32 #include <linux/list.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <asm/hardware.h>
  36 #include <asm/arch/dmtimer.h>
  37 #include <asm/io.h>
  38 #include <asm/arch/irqs.h>
  39
  40 /* register offsets */
  41 #define OMAP_TIMER_ID_REG               0x00
  42 #define OMAP_TIMER_OCP_CFG_REG          0x10
  43 #define OMAP_TIMER_SYS_STAT_REG         0x14
  44 #define OMAP_TIMER_STAT_REG             0x18
  45 #define OMAP_TIMER_INT_EN_REG           0x1c
  46 #define OMAP_TIMER_WAKEUP_EN_REG        0x20
  47 #define OMAP_TIMER_CTRL_REG             0x24
  48 #define OMAP_TIMER_COUNTER_REG          0x28
  49 #define OMAP_TIMER_LOAD_REG             0x2c
  50 #define OMAP_TIMER_TRIGGER_REG          0x30
  51 #define OMAP_TIMER_WRITE_PEND_REG       0x34
  52 #define OMAP_TIMER_MATCH_REG            0x38
  53 #define OMAP_TIMER_CAPTURE_REG          0x3c
  54 #define OMAP_TIMER_IF_CTRL_REG          0x40
  55
  56 /* timer control reg bits */
  57 #define OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
  58 #define OMAP_TIMER_CTRL_CAPTMODE        (1 << 13)
  59 #define OMAP_TIMER_CTRL_PT              (1 << 12)
  60 #define OMAP_TIMER_CTRL_TCM_LOWTOHIGH   (0x1 << 8)
  61 #define OMAP_TIMER_CTRL_TCM_HIGHTOLOW   (0x2 << 8)
  62 #define OMAP_TIMER_CTRL_TCM_BOTHEDGES   (0x3 << 8)
  63 #define OMAP_TIMER_CTRL_SCPWM           (1 << 7)
  64 #define OMAP_TIMER_CTRL_CE              (1 << 6)        /* compare enable */
  65 #define OMAP_TIMER_CTRL_PRE             (1 << 5)        /* prescaler enable */
  66 #define OMAP_TIMER_CTRL_PTV_SHIFT       2               /* how much to shift the prescaler value */
  67 #define OMAP_TIMER_CTRL_AR              (1 << 1)        /* auto-reload enable */
  68 #define OMAP_TIMER_CTRL_ST              (1 << 0)        /* start timer */
  69
  70 struct omap_dm_timer {
  71         unsigned long phys_base;
  72         int irq;
  73 #ifdef CONFIG_ARCH_OMAP2
  74         struct clk *iclk, *fclk;
  75 #endif
  76         void __iomem *io_base;
  77         unsigned reserved:1;
  78 };
  79
  80 #ifdef CONFIG_ARCH_OMAP1
  81
  82 static struct omap_dm_timer dm_timers[] = {
  83         { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
  84         { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
  85         { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
  86         { .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 },
  87         { .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 },
  88         { .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 },
  89         { .phys_base = 0xfffb4400, .irq = INT_1610_GPTIMER7 },
  90         { .phys_base = 0xfffb4c00, .irq = INT_1610_GPTIMER8 },
  91 };
  92
  93 #elif defined(CONFIG_ARCH_OMAP2)
  94
  95 static struct omap_dm_timer dm_timers[] = {
  96         { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
  97         { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
  98         { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
  99         { .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 },
 100         { .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 },
 101         { .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 },
 102         { .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 },
 103         { .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 },
 104         { .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 },
 105         { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
 106         { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
 107         { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
 108 };
 109
 110 #else
 111
 112 #error OMAP architecture not supported!
 113
 114 #endif
 115
 116 static const int dm_timer_count = ARRAY_SIZE(dm_timers);
 117
 118 static spinlock_t dm_timer_lock;
 119
 120 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
 121 {
 122         return readl(timer->io_base + reg);
 123 }
 124
 125 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value)
 126 {
 127         writel(value, timer->io_base + reg);
 128         while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG))
 129                 ;
 130 }
 131
 132 static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
 133 {
 134         int c;
 135
 136         c = 0;
 137         while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) {
 138                 c++;
 139                 if (c > 100000) {
 140                         printk(KERN_ERR "Timer failed to reset\n");
 141                         return;
 142                 }
 143         }
 144 }
 145
 146 static void omap_dm_timer_reset(struct omap_dm_timer *timer)
 147 {
 148         u32 l;
 149
 150         if (timer != &dm_timers[0]) {
 151                 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
 152                 omap_dm_timer_wait_for_reset(timer);
 153         }
 154         omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_SYS_CLK);
 155
 156         /* Set to smart-idle mode */
 157         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
 158         l |= 0x02 << 3;
 159         omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
 160 }
 161
 162 static void omap_dm_timer_reserve(struct omap_dm_timer *timer)
 163 {
 164         timer->reserved = 1;
 165 #ifdef CONFIG_ARCH_OMAP2
 166         clk_enable(timer->iclk);
 167         clk_enable(timer->fclk);
 168 #endif
 169         omap_dm_timer_reset(timer);
 170 }
 171
 172 struct omap_dm_timer *omap_dm_timer_request(void)
 173 {
 174         struct omap_dm_timer *timer = NULL;
 175         unsigned long flags;
 176         int i;
 177
 178         spin_lock_irqsave(&dm_timer_lock, flags);
 179         for (i = 0; i < dm_timer_count; i++) {
 180                 if (dm_timers[i].reserved)
 181                         continue;
 182
 183                 timer = &dm_timers[i];
 184                 omap_dm_timer_reserve(timer);
 185                 break;
 186         }
 187         spin_unlock_irqrestore(&dm_timer_lock, flags);
 188
 189         return timer;
 190 }
 191
 192 struct omap_dm_timer *omap_dm_timer_request_specific(int id)
 193 {
 194         struct omap_dm_timer *timer;
 195         unsigned long flags;
 196
 197         spin_lock_irqsave(&dm_timer_lock, flags);
 198         if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) {
 199                 spin_unlock_irqrestore(&dm_timer_lock, flags);
 200                 printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
 201                        __FILE__, __LINE__, __FUNCTION__, id);
 202                 dump_stack();
 203                 return NULL;
 204         }
 205
 206         timer = &dm_timers[id-1];
 207         omap_dm_timer_reserve(timer);
 208         spin_unlock_irqrestore(&dm_timer_lock, flags);
 209
 210         return timer;
 211 }
 212
 213 void omap_dm_timer_free(struct omap_dm_timer *timer)
 214 {
 215         omap_dm_timer_reset(timer);
 216 #ifdef CONFIG_ARCH_OMAP2
 217         clk_disable(timer->iclk);
 218         clk_disable(timer->fclk);
 219 #endif
 220         WARN_ON(!timer->reserved);
 221         timer->reserved = 0;
 222 }
 223
 224 int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
 225 {
 226         return timer->irq;
 227 }
 228
 229 #if defined(CONFIG_ARCH_OMAP1)
 230
 231 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 232 {
 233         BUG();
 234 }
 235
 236 /**
 237  * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
 238  * @inputmask: current value of idlect mask
 239  */
 240 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 241 {
 242         int i;
 243
 244         /* If ARMXOR cannot be idled this function call is unnecessary */
 245         if (!(inputmask & (1 << 1)))
 246                 return inputmask;
 247
 248         /* If any active timer is using ARMXOR return modified mask */
 249         for (i = 0; i < dm_timer_count; i++) {
 250                 u32 l;
 251
 252                 l = omap_dm_timer_read_reg(&dm_timers[n], OMAP_TIMER_CTRL_REG);
 253                 if (l & OMAP_TIMER_CTRL_ST) {
 254                         if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
 255                                 inputmask &= ~(1 << 1);
 256                         else
 257                                 inputmask &= ~(1 << 2);
 258                 }
 259         }
 260
 261         return inputmask;
 262 }
 263
 264 #elif defined(CONFIG_ARCH_OMAP2)
 265
 266 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 267 {
 268         return timer->fclk;
 269 }
 270
 271 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 272 {
 273         BUG();
 274 }
 275
 276 #endif
 277
 278 void omap_dm_timer_trigger(struct omap_dm_timer *timer)
 279 {
 280         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 281 }
 282
 283 void omap_dm_timer_start(struct omap_dm_timer *timer)
 284 {
 285         u32 l;
 286
 287         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 288         if (!(l & OMAP_TIMER_CTRL_ST)) {
 289                 l |= OMAP_TIMER_CTRL_ST;
 290                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 291         }
 292 }
 293
 294 void omap_dm_timer_stop(struct omap_dm_timer *timer)
 295 {
 296         u32 l;
 297
 298         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 299         if (l & OMAP_TIMER_CTRL_ST) {
 300                 l &= ~0x1;
 301                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 302         }
 303 }
 304
 305 #ifdef CONFIG_ARCH_OMAP1
 306
 307 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 308 {
 309         int n = (timer - dm_timers) << 1;
 310         u32 l;
 311
 312         l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
 313         l |= source << n;
 314         omap_writel(l, MOD_CONF_CTRL_1);
 315 }
 316
 317 #else
 318
 319 void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 320 {
 321         static const char *source_timers[] = {
 322                 "sys_ck",
 323                 "func_32k_ck",
 324                 "alt_ck"
 325         };
 326         struct clk *parent;
 327
 328         if (source < 0 || source >= 3)
 329                 return;
 330
 331         parent = clk_get(NULL, source_timers[source]);
 332         clk_disable(timer->fclk);
 333         clk_set_parent(timer->fclk, parent);
 334         clk_enable(timer->fclk);
 335         clk_put(parent);
 336
 337         /* When the functional clock disappears, too quick writes seem to
 338          * cause an abort. */
 339         __delay(15000);
 340 }
 341
 342 #endif
 343
 344 void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
 345                             unsigned int load)
 346 {
 347         u32 l;
 348
 349         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 350         if (autoreload)
 351                 l |= OMAP_TIMER_CTRL_AR;
 352         else
 353                 l &= ~OMAP_TIMER_CTRL_AR;
 354         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 355         omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
 356         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 357 }
 358
 359 void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
 360                              unsigned int match)
 361 {
 362         u32 l;
 363
 364         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 365         if (enable)
 366                 l |= OMAP_TIMER_CTRL_CE;
 367         else
 368                 l &= ~OMAP_TIMER_CTRL_CE;
 369         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 370         omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
 371 }
 372
 373
 374 void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
 375                            int toggle, int trigger)
 376 {
 377         u32 l;
 378
 379         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 380         l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
 381                OMAP_TIMER_CTRL_PT | (0x03 << 10));
 382         if (def_on)
 383                 l |= OMAP_TIMER_CTRL_SCPWM;
 384         if (toggle)
 385                 l |= OMAP_TIMER_CTRL_PT;
 386         l |= trigger << 10;
 387         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 388 }
 389
 390 void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
 391 {
 392         u32 l;
 393
 394         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 395         l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
 396         if (prescaler >= 0x00 && prescaler <= 0x07) {
 397                 l |= OMAP_TIMER_CTRL_PRE;
 398                 l |= prescaler << 2;
 399         }
 400         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 401 }
 402
 403 void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
 404                                   unsigned int value)
 405 {
 406         omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
 407 }
 408
 409 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
 410 {
 411         return omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
 412 }
 413
 414 void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
 415 {
 416         omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
 417 }
 418
 419 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
 420 {
 421         return omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
 422 }
 423
 424 int omap_dm_timers_active(void)
 425 {
 426         int i;
 427
 428         for (i = 0; i < dm_timer_count; i++) {
 429                 struct omap_dm_timer *timer;
 430
 431                 timer = &dm_timers[i];
 432                 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
 433                     OMAP_TIMER_CTRL_ST)
 434                         return 1;
 435         }
 436         return 0;
 437 }
 438
 439 int omap_dm_timer_init(void)
 440 {
 441         struct omap_dm_timer *timer;
 442         int i;
 443
 444         if (!(cpu_is_omap16xx() || cpu_is_omap24xx()))
 445                 return -ENODEV;
 446
 447         spin_lock_init(&dm_timer_lock);
 448         for (i = 0; i < dm_timer_count; i++) {
 449 #ifdef CONFIG_ARCH_OMAP2
 450                 char clk_name[16];
 451 #endif
 452
 453                 timer = &dm_timers[i];
 454                 timer->io_base = (void __iomem *) io_p2v(timer->phys_base);
 455 #ifdef CONFIG_ARCH_OMAP2
 456                 sprintf(clk_name, "gpt%d_ick", i + 1);
 457                 timer->iclk = clk_get(NULL, clk_name);
 458                 sprintf(clk_name, "gpt%d_fck", i + 1);
 459                 timer->fclk = clk_get(NULL, clk_name);
 460 #endif
 461         }
 462
 463         return 0;
 464 }