2 * Freescale STMP378X platform support
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/irq.h>
24 #include <asm/setup.h>
25 #include <asm/mach-types.h>
27 #include <asm/mach/arch.h>
28 #include <asm/mach/irq.h>
29 #include <asm/mach/map.h>
30 #include <asm/mach/time.h>
32 #include <mach/pins.h>
33 #include <mach/pinmux.h>
35 #include <mach/hardware.h>
36 #include <mach/system.h>
37 #include <mach/platform.h>
38 #include <mach/stmp3xxx.h>
39 #include <mach/regs-icoll.h>
40 #include <mach/regs-apbh.h>
41 #include <mach/regs-apbx.h>
47 static void stmp378x_ack_irq(unsigned int irq)
49 /* Tell ICOLL to release IRQ line */
50 HW_ICOLL_VECTOR_WR(0x0);
52 /* ACK current interrupt */
53 HW_ICOLL_LEVELACK_WR(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0);
56 (void) HW_ICOLL_STAT_RD();
59 static void stmp378x_mask_irq(unsigned int irq)
62 HW_ICOLL_INTERRUPTn_CLR(irq, BM_ICOLL_INTERRUPTn_ENABLE);
65 static void stmp378x_unmask_irq(unsigned int irq)
68 HW_ICOLL_INTERRUPTn_SET(irq, BM_ICOLL_INTERRUPTn_ENABLE);
71 static struct irq_chip stmp378x_chip = {
72 .ack = stmp378x_ack_irq,
73 .mask = stmp378x_mask_irq,
74 .unmask = stmp378x_unmask_irq,
77 void __init stmp378x_init_irq(void)
79 stmp3xxx_init_irq(&stmp378x_chip);
83 * DMA interrupt handling
85 void stmp3xxx_arch_dma_enable_interrupt(int channel)
87 int dmabus = channel / 16;
90 case STMP3XXX_BUS_APBH:
91 HW_APBH_CTRL1_SET(1 << (16 + (channel % 16)));
92 HW_APBH_CTRL2_SET(1 << (16 + (channel % 16)));
95 case STMP3XXX_BUS_APBX:
96 HW_APBX_CTRL1_SET(1 << (16 + (channel % 16)));
97 HW_APBX_CTRL2_SET(1 << (16 + (channel % 16)));
101 EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
103 void stmp3xxx_arch_dma_clear_interrupt(int channel)
105 int dmabus = channel / 16;
108 case STMP3XXX_BUS_APBH:
109 HW_APBH_CTRL1_CLR(1 << (channel % 16));
110 HW_APBH_CTRL2_CLR(1 << (channel % 16));
113 case STMP3XXX_BUS_APBX:
114 HW_APBX_CTRL1_CLR(1 << (channel % 16));
115 HW_APBX_CTRL2_CLR(1 << (channel % 16));
119 EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
121 int stmp3xxx_arch_dma_is_interrupt(int channel)
123 int dmabus = channel / 16;
127 case STMP3XXX_BUS_APBH:
128 r = HW_APBH_CTRL1_RD() & (1 << (channel % 16));
131 case STMP3XXX_BUS_APBX:
132 r = HW_APBX_CTRL1_RD() & (1 << (channel % 16));
137 EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
139 void stmp3xxx_arch_dma_reset_channel(int channel)
141 int dmabus = channel / 16;
142 unsigned chbit = 1 << (channel % 16);
145 case STMP3XXX_BUS_APBH:
146 /* Reset channel and wait for it to complete */
147 HW_APBH_CTRL0_SET(chbit <<
148 BP_APBH_CTRL0_RESET_CHANNEL);
149 while (HW_APBH_CTRL0_RD() &
150 (chbit << BP_APBH_CTRL0_RESET_CHANNEL))
154 case STMP3XXX_BUS_APBX:
155 /* Reset channel and wait for it to complete */
156 HW_APBX_CHANNEL_CTRL_SET(
157 BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(chbit));
158 while (HW_APBX_CHANNEL_CTRL_RD() &
159 BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(chbit))
164 EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
166 void stmp3xxx_arch_dma_freeze(int channel)
168 int dmabus = channel / 16;
169 unsigned chbit = 1 << (channel % 16);
172 case STMP3XXX_BUS_APBH:
173 HW_APBH_CTRL0_SET(1<<chbit);
175 case STMP3XXX_BUS_APBX:
176 HW_APBX_CHANNEL_CTRL_SET(1<<chbit);
180 EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
182 void stmp3xxx_arch_dma_unfreeze(int channel)
184 int dmabus = channel / 16;
185 unsigned chbit = 1 << (channel % 16);
188 case STMP3XXX_BUS_APBH:
189 HW_APBH_CTRL0_CLR(1<<chbit);
191 case STMP3XXX_BUS_APBX:
192 HW_APBX_CHANNEL_CTRL_CLR(1<<chbit);
196 EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
199 * The registers are all very closely mapped, so we might as well map them all
200 * with a single mapping
203 * f0000000 80000000 On-chip registers
204 * f1000000 00000000 256k on-chip SRAM
207 static struct map_desc stmp378x_io_desc[] __initdata = {
209 .virtual = (u32)STMP3XXX_REGS_BASE,
210 .pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE),
211 .length = STMP3XXX_REGS_SIZE,
215 .virtual = (u32)STMP3XXX_OCRAM_BASE,
216 .pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE),
217 .length = STMP3XXX_OCRAM_SIZE,
222 void __init stmp378x_map_io(void)
224 iotable_init(stmp378x_io_desc, ARRAY_SIZE(stmp378x_io_desc));