1 /* linux/arch/arm/mach-s5pv210/clock.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5PV210 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
25 #include <plat/cpu-freq.h>
26 #include <mach/regs-clock.h>
27 #include <plat/clock.h>
30 #include <plat/s5p-clock.h>
31 #include <plat/clock-clksrc.h>
32 #include <plat/s5pv210.h>
34 static struct clksrc_clk clk_mout_apll = {
39 .sources = &clk_src_apll,
40 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
43 static struct clksrc_clk clk_mout_epll = {
48 .sources = &clk_src_epll,
49 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
52 static struct clksrc_clk clk_mout_mpll = {
57 .sources = &clk_src_mpll,
58 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
61 static struct clk *clkset_armclk_list[] = {
62 [0] = &clk_mout_apll.clk,
63 [1] = &clk_mout_mpll.clk,
66 static struct clksrc_sources clkset_armclk = {
67 .sources = clkset_armclk_list,
68 .nr_sources = ARRAY_SIZE(clkset_armclk_list),
71 static struct clksrc_clk clk_armclk = {
76 .sources = &clkset_armclk,
77 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
78 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
81 static struct clksrc_clk clk_hclk_msys = {
85 .parent = &clk_armclk.clk,
87 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
90 static struct clksrc_clk clk_pclk_msys = {
94 .parent = &clk_hclk_msys.clk,
96 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
99 static struct clksrc_clk clk_sclk_a2m = {
103 .parent = &clk_mout_apll.clk,
105 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
108 static struct clk *clkset_hclk_sys_list[] = {
109 [0] = &clk_mout_mpll.clk,
110 [1] = &clk_sclk_a2m.clk,
113 static struct clksrc_sources clkset_hclk_sys = {
114 .sources = clkset_hclk_sys_list,
115 .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list),
118 static struct clksrc_clk clk_hclk_dsys = {
123 .sources = &clkset_hclk_sys,
124 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
125 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
128 static struct clksrc_clk clk_pclk_dsys = {
132 .parent = &clk_hclk_dsys.clk,
134 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
137 static struct clksrc_clk clk_hclk_psys = {
142 .sources = &clkset_hclk_sys,
143 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
144 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
147 static struct clksrc_clk clk_pclk_psys = {
151 .parent = &clk_hclk_psys.clk,
153 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
156 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
158 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
161 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
163 return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
166 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
168 return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
171 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
173 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
176 static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
178 return clk_get_rate(clk->parent) / 2;
181 static struct clk_ops clk_hclk_imem_ops = {
182 .get_rate = s5pv210_clk_imem_get_rate,
185 static struct clk init_clocks_disable[] = {
189 .parent = &clk_hclk_dsys.clk,
190 .enable = s5pv210_clk_ip0_ctrl,
195 .parent = &clk_hclk_psys.clk,
196 .enable = s5pv210_clk_ip1_ctrl,
201 .parent = &clk_hclk_psys.clk,
202 .enable = s5pv210_clk_ip1_ctrl,
207 .parent = &clk_hclk_dsys.clk,
208 .enable = s5pv210_clk_ip1_ctrl,
213 .parent = &clk_hclk_psys.clk,
214 .enable = s5pv210_clk_ip1_ctrl,
219 .parent = &clk_hclk_psys.clk,
220 .enable = s5pv210_clk_ip2_ctrl,
225 .parent = &clk_hclk_psys.clk,
226 .enable = s5pv210_clk_ip2_ctrl,
231 .parent = &clk_hclk_psys.clk,
232 .enable = s5pv210_clk_ip2_ctrl,
237 .parent = &clk_hclk_psys.clk,
238 .enable = s5pv210_clk_ip2_ctrl,
243 .parent = &clk_pclk_psys.clk,
244 .enable = s5pv210_clk_ip3_ctrl,
249 .parent = &clk_pclk_psys.clk,
250 .enable = s5pv210_clk_ip3_ctrl,
255 .parent = &clk_pclk_psys.clk,
256 .enable = s5pv210_clk_ip3_ctrl,
261 .parent = &clk_pclk_psys.clk,
262 .enable = s5pv210_clk_ip3_ctrl,
267 .parent = &clk_pclk_psys.clk,
268 .enable = s5pv210_clk_ip3_ctrl,
273 .parent = &clk_pclk_psys.clk,
274 .enable = s5pv210_clk_ip3_ctrl,
279 .parent = &clk_pclk_psys.clk,
280 .enable = s5pv210_clk_ip3_ctrl,
285 .parent = &clk_pclk_psys.clk,
286 .enable = s5pv210_clk_ip3_ctrl,
291 .parent = &clk_pclk_psys.clk,
292 .enable = s5pv210_clk_ip3_ctrl,
297 .parent = &clk_pclk_psys.clk,
298 .enable = s5pv210_clk_ip3_ctrl,
303 .parent = &clk_pclk_psys.clk,
304 .enable = s5pv210_clk_ip3_ctrl,
309 .parent = &clk_pclk_psys.clk,
310 .enable = s5pv210_clk_ip3_ctrl,
316 .enable = s5pv210_clk_ip3_ctrl,
322 .enable = s5pv210_clk_ip3_ctrl,
328 .enable = s5pv210_clk_ip3_ctrl,
333 static struct clk init_clocks[] = {
337 .parent = &clk_hclk_msys.clk,
339 .enable = s5pv210_clk_ip0_ctrl,
340 .ops = &clk_hclk_imem_ops,
344 .parent = &clk_pclk_psys.clk,
345 .enable = s5pv210_clk_ip3_ctrl,
350 .parent = &clk_pclk_psys.clk,
351 .enable = s5pv210_clk_ip3_ctrl,
356 .parent = &clk_pclk_psys.clk,
357 .enable = s5pv210_clk_ip3_ctrl,
362 .parent = &clk_pclk_psys.clk,
363 .enable = s5pv210_clk_ip3_ctrl,
368 static struct clk *clkset_uart_list[] = {
369 [6] = &clk_mout_mpll.clk,
370 [7] = &clk_mout_epll.clk,
373 static struct clksrc_sources clkset_uart = {
374 .sources = clkset_uart_list,
375 .nr_sources = ARRAY_SIZE(clkset_uart_list),
378 static struct clksrc_clk clksrcs[] = {
384 .enable = s5pv210_clk_ip3_ctrl,
386 .sources = &clkset_uart,
387 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
388 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
392 /* Clock initialisation code */
393 static struct clksrc_clk *sysclks[] = {
407 void __init_or_cpufreq s5pv210_setup_clocks(void)
409 struct clk *xtal_clk;
411 unsigned long armclk;
412 unsigned long hclk_msys;
413 unsigned long hclk_dsys;
414 unsigned long hclk_psys;
415 unsigned long pclk_msys;
416 unsigned long pclk_dsys;
417 unsigned long pclk_psys;
422 u32 clkdiv0, clkdiv1;
424 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
426 clkdiv0 = __raw_readl(S5P_CLK_DIV0);
427 clkdiv1 = __raw_readl(S5P_CLK_DIV1);
429 printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
430 __func__, clkdiv0, clkdiv1);
432 xtal_clk = clk_get(NULL, "xtal");
433 BUG_ON(IS_ERR(xtal_clk));
435 xtal = clk_get_rate(xtal_clk);
438 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
440 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
441 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
442 epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
444 clk_fout_apll.rate = apll;
445 clk_fout_mpll.rate = mpll;
446 clk_fout_epll.rate = epll;
448 printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld",
451 armclk = clk_get_rate(&clk_armclk.clk);
452 hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
453 hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
454 hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
455 pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
456 pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
457 pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
459 printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
460 "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
461 armclk, hclk_msys, hclk_dsys, hclk_psys,
462 pclk_msys, pclk_dsys, pclk_psys);
465 clk_h.rate = hclk_psys;
466 clk_p.rate = pclk_psys;
468 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
469 s3c_set_clksrc(&clksrcs[ptr], true);
472 static struct clk *clks[] __initdata = {
475 void __init s5pv210_register_clocks(void)
481 ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
483 printk(KERN_ERR "Failed to register %u clocks\n", ret);
485 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
486 s3c_register_clksrc(sysclks[ptr], 1);
488 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
489 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
491 clkp = init_clocks_disable;
492 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
493 ret = s3c24xx_register_clock(clkp);
495 printk(KERN_ERR "Failed to register clock %s (%d)\n",
498 (clkp->enable)(clkp, 0);