SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/arm/mach-s5pv210/clock.c

   1 /* linux/arch/arm/mach-s5pv210/clock.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5PV210 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/map.h>
  24
  25 #include <plat/cpu-freq.h>
  26 #include <mach/regs-clock.h>
  27 #include <plat/clock.h>
  28 #include <plat/cpu.h>
  29 #include <plat/pll.h>
  30 #include <plat/s5p-clock.h>
  31 #include <plat/clock-clksrc.h>
  32 #include <plat/s5pv210.h>
  33
  34 static struct clksrc_clk clk_mout_apll = {
  35         .clk    = {
  36                 .name           = "mout_apll",
  37                 .id             = -1,
  38         },
  39         .sources        = &clk_src_apll,
  40         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
  41 };
  42
  43 static struct clksrc_clk clk_mout_epll = {
  44         .clk    = {
  45                 .name           = "mout_epll",
  46                 .id             = -1,
  47         },
  48         .sources        = &clk_src_epll,
  49         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
  50 };
  51
  52 static struct clksrc_clk clk_mout_mpll = {
  53         .clk = {
  54                 .name           = "mout_mpll",
  55                 .id             = -1,
  56         },
  57         .sources        = &clk_src_mpll,
  58         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
  59 };
  60
  61 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
  62 {
  63         return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
  64 }
  65
  66 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
  67 {
  68         return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
  69 }
  70
  71 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
  72 {
  73         return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
  74 }
  75
  76 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
  77 {
  78         return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
  79 }
  80
  81 static struct clk clk_h200 = {
  82         .name           = "hclk200",
  83         .id             = -1,
  84 };
  85
  86 static struct clk clk_h100 = {
  87         .name           = "hclk100",
  88         .id             = -1,
  89 };
  90
  91 static struct clk clk_h166 = {
  92         .name           = "hclk166",
  93         .id             = -1,
  94 };
  95
  96 static struct clk clk_h133 = {
  97         .name           = "hclk133",
  98         .id             = -1,
  99 };
 100
 101 static struct clk clk_p100 = {
 102         .name           = "pclk100",
 103         .id             = -1,
 104 };
 105
 106 static struct clk clk_p83 = {
 107         .name           = "pclk83",
 108         .id             = -1,
 109 };
 110
 111 static struct clk clk_p66 = {
 112         .name           = "pclk66",
 113         .id             = -1,
 114 };
 115
 116 static struct clk *sys_clks[] = {
 117         &clk_h200,
 118         &clk_h100,
 119         &clk_h166,
 120         &clk_h133,
 121         &clk_p100,
 122         &clk_p83,
 123         &clk_p66
 124 };
 125
 126 static struct clk init_clocks_disable[] = {
 127         {
 128                 .name           = "rot",
 129                 .id             = -1,
 130                 .parent         = &clk_h166,
 131                 .enable         = s5pv210_clk_ip0_ctrl,
 132                 .ctrlbit        = (1<<29),
 133         }, {
 134                 .name           = "otg",
 135                 .id             = -1,
 136                 .parent         = &clk_h133,
 137                 .enable         = s5pv210_clk_ip1_ctrl,
 138                 .ctrlbit        = (1<<16),
 139         }, {
 140                 .name           = "usb-host",
 141                 .id             = -1,
 142                 .parent         = &clk_h133,
 143                 .enable         = s5pv210_clk_ip1_ctrl,
 144                 .ctrlbit        = (1<<17),
 145         }, {
 146                 .name           = "lcd",
 147                 .id             = -1,
 148                 .parent         = &clk_h166,
 149                 .enable         = s5pv210_clk_ip1_ctrl,
 150                 .ctrlbit        = (1<<0),
 151         }, {
 152                 .name           = "cfcon",
 153                 .id             = 0,
 154                 .parent         = &clk_h133,
 155                 .enable         = s5pv210_clk_ip1_ctrl,
 156                 .ctrlbit        = (1<<25),
 157         }, {
 158                 .name           = "hsmmc",
 159                 .id             = 0,
 160                 .parent         = &clk_h133,
 161                 .enable         = s5pv210_clk_ip2_ctrl,
 162                 .ctrlbit        = (1<<16),
 163         }, {
 164                 .name           = "hsmmc",
 165                 .id             = 1,
 166                 .parent         = &clk_h133,
 167                 .enable         = s5pv210_clk_ip2_ctrl,
 168                 .ctrlbit        = (1<<17),
 169         }, {
 170                 .name           = "hsmmc",
 171                 .id             = 2,
 172                 .parent         = &clk_h133,
 173                 .enable         = s5pv210_clk_ip2_ctrl,
 174                 .ctrlbit        = (1<<18),
 175         }, {
 176                 .name           = "hsmmc",
 177                 .id             = 3,
 178                 .parent         = &clk_h133,
 179                 .enable         = s5pv210_clk_ip2_ctrl,
 180                 .ctrlbit        = (1<<19),
 181         }, {
 182                 .name           = "systimer",
 183                 .id             = -1,
 184                 .parent         = &clk_p66,
 185                 .enable         = s5pv210_clk_ip3_ctrl,
 186                 .ctrlbit        = (1<<16),
 187         }, {
 188                 .name           = "watchdog",
 189                 .id             = -1,
 190                 .parent         = &clk_p66,
 191                 .enable         = s5pv210_clk_ip3_ctrl,
 192                 .ctrlbit        = (1<<22),
 193         }, {
 194                 .name           = "rtc",
 195                 .id             = -1,
 196                 .parent         = &clk_p66,
 197                 .enable         = s5pv210_clk_ip3_ctrl,
 198                 .ctrlbit        = (1<<15),
 199         }, {
 200                 .name           = "i2c",
 201                 .id             = 0,
 202                 .parent         = &clk_p66,
 203                 .enable         = s5pv210_clk_ip3_ctrl,
 204                 .ctrlbit        = (1<<7),
 205         }, {
 206                 .name           = "i2c",
 207                 .id             = 1,
 208                 .parent         = &clk_p66,
 209                 .enable         = s5pv210_clk_ip3_ctrl,
 210                 .ctrlbit        = (1<<8),
 211         }, {
 212                 .name           = "i2c",
 213                 .id             = 2,
 214                 .parent         = &clk_p66,
 215                 .enable         = s5pv210_clk_ip3_ctrl,
 216                 .ctrlbit        = (1<<9),
 217         }, {
 218                 .name           = "spi",
 219                 .id             = 0,
 220                 .parent         = &clk_p66,
 221                 .enable         = s5pv210_clk_ip3_ctrl,
 222                 .ctrlbit        = (1<<12),
 223         }, {
 224                 .name           = "spi",
 225                 .id             = 1,
 226                 .parent         = &clk_p66,
 227                 .enable         = s5pv210_clk_ip3_ctrl,
 228                 .ctrlbit        = (1<<13),
 229         }, {
 230                 .name           = "spi",
 231                 .id             = 2,
 232                 .parent         = &clk_p66,
 233                 .enable         = s5pv210_clk_ip3_ctrl,
 234                 .ctrlbit        = (1<<14),
 235         }, {
 236                 .name           = "timers",
 237                 .id             = -1,
 238                 .parent         = &clk_p66,
 239                 .enable         = s5pv210_clk_ip3_ctrl,
 240                 .ctrlbit        = (1<<23),
 241         }, {
 242                 .name           = "adc",
 243                 .id             = -1,
 244                 .parent         = &clk_p66,
 245                 .enable         = s5pv210_clk_ip3_ctrl,
 246                 .ctrlbit        = (1<<24),
 247         }, {
 248                 .name           = "keypad",
 249                 .id             = -1,
 250                 .parent         = &clk_p66,
 251                 .enable         = s5pv210_clk_ip3_ctrl,
 252                 .ctrlbit        = (1<<21),
 253         }, {
 254                 .name           = "i2s_v50",
 255                 .id             = 0,
 256                 .parent         = &clk_p,
 257                 .enable         = s5pv210_clk_ip3_ctrl,
 258                 .ctrlbit        = (1<<4),
 259         }, {
 260                 .name           = "i2s_v32",
 261                 .id             = 0,
 262                 .parent         = &clk_p,
 263                 .enable         = s5pv210_clk_ip3_ctrl,
 264                 .ctrlbit        = (1<<4),
 265         }, {
 266                 .name           = "i2s_v32",
 267                 .id             = 1,
 268                 .parent         = &clk_p,
 269                 .enable         = s5pv210_clk_ip3_ctrl,
 270                 .ctrlbit        = (1<<4),
 271         }
 272 };
 273
 274 static struct clk init_clocks[] = {
 275         {
 276                 .name           = "uart",
 277                 .id             = 0,
 278                 .parent         = &clk_p66,
 279                 .enable         = s5pv210_clk_ip3_ctrl,
 280                 .ctrlbit        = (1<<7),
 281         }, {
 282                 .name           = "uart",
 283                 .id             = 1,
 284                 .parent         = &clk_p66,
 285                 .enable         = s5pv210_clk_ip3_ctrl,
 286                 .ctrlbit        = (1<<8),
 287         }, {
 288                 .name           = "uart",
 289                 .id             = 2,
 290                 .parent         = &clk_p66,
 291                 .enable         = s5pv210_clk_ip3_ctrl,
 292                 .ctrlbit        = (1<<9),
 293         }, {
 294                 .name           = "uart",
 295                 .id             = 3,
 296                 .parent         = &clk_p66,
 297                 .enable         = s5pv210_clk_ip3_ctrl,
 298                 .ctrlbit        = (1<<10),
 299         },
 300 };
 301
 302 static struct clk *clkset_uart_list[] = {
 303         [6] = &clk_mout_mpll.clk,
 304         [7] = &clk_mout_epll.clk,
 305 };
 306
 307 static struct clksrc_sources clkset_uart = {
 308         .sources        = clkset_uart_list,
 309         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 310 };
 311
 312 static struct clksrc_clk clksrcs[] = {
 313         {
 314                 .clk    = {
 315                         .name           = "uclk1",
 316                         .id             = -1,
 317                         .ctrlbit        = (1<<17),
 318                         .enable         = s5pv210_clk_ip3_ctrl,
 319                 },
 320                 .sources = &clkset_uart,
 321                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
 322                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
 323         }
 324 };
 325
 326 /* Clock initialisation code */
 327 static struct clksrc_clk *sysclks[] = {
 328         &clk_mout_apll,
 329         &clk_mout_epll,
 330         &clk_mout_mpll,
 331 };
 332
 333 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
 334
 335 void __init_or_cpufreq s5pv210_setup_clocks(void)
 336 {
 337         struct clk *xtal_clk;
 338         unsigned long xtal;
 339         unsigned long armclk;
 340         unsigned long hclk200;
 341         unsigned long hclk166;
 342         unsigned long hclk133;
 343         unsigned long pclk100;
 344         unsigned long pclk83;
 345         unsigned long pclk66;
 346         unsigned long apll;
 347         unsigned long mpll;
 348         unsigned long epll;
 349         unsigned int ptr;
 350         u32 clkdiv0, clkdiv1;
 351
 352         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
 353
 354         clkdiv0 = __raw_readl(S5P_CLK_DIV0);
 355         clkdiv1 = __raw_readl(S5P_CLK_DIV1);
 356
 357         printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
 358                                 __func__, clkdiv0, clkdiv1);
 359
 360         xtal_clk = clk_get(NULL, "xtal");
 361         BUG_ON(IS_ERR(xtal_clk));
 362
 363         xtal = clk_get_rate(xtal_clk);
 364         clk_put(xtal_clk);
 365
 366         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
 367
 368         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
 369         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
 370         epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
 371
 372         clk_fout_apll.rate = apll;
 373         clk_fout_mpll.rate = mpll;
 374         clk_fout_epll.rate = epll;
 375
 376         printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld",
 377                         apll, mpll, epll);
 378
 379         armclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_APLL);
 380         if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX200_MASK)
 381                 hclk200 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200);
 382         else
 383                 hclk200 = armclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200);
 384
 385         if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX166_MASK) {
 386                 hclk166 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M);
 387                 hclk166 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK166);
 388         } else
 389                 hclk166 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK166);
 390
 391         if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX133_MASK) {
 392                 hclk133 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M);
 393                 hclk133 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133);
 394         } else
 395                 hclk133 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133);
 396
 397         pclk100 = hclk200 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK100);
 398         pclk83 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83);
 399         pclk66 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66);
 400
 401         printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld, \
 402                         HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
 403                armclk, hclk200, hclk166, hclk133, pclk100, pclk83, pclk66);
 404
 405         clk_f.rate = armclk;
 406         clk_h.rate = hclk133;
 407         clk_p.rate = pclk66;
 408         clk_p66.rate = pclk66;
 409         clk_p83.rate = pclk83;
 410         clk_h133.rate = hclk133;
 411         clk_h166.rate = hclk166;
 412         clk_h200.rate = hclk200;
 413
 414         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 415                 s3c_set_clksrc(&clksrcs[ptr], true);
 416 }
 417
 418 static struct clk *clks[] __initdata = {
 419 };
 420
 421 void __init s5pv210_register_clocks(void)
 422 {
 423         struct clk *clkp;
 424         int ret;
 425         int ptr;
 426
 427         ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 428         if (ret > 0)
 429                 printk(KERN_ERR "Failed to register %u clocks\n", ret);
 430
 431         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 432                 s3c_register_clksrc(sysclks[ptr], 1);
 433
 434         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 435         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 436
 437         ret = s3c24xx_register_clocks(sys_clks, ARRAY_SIZE(sys_clks));
 438         if (ret > 0)
 439                 printk(KERN_ERR "Failed to register system clocks\n");
 440
 441         clkp = init_clocks_disable;
 442         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
 443                 ret = s3c24xx_register_clock(clkp);
 444                 if (ret < 0) {
 445                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 446                                clkp->name, ret);
 447                 }
 448                 (clkp->enable)(clkp, 0);
 449         }
 450
 451         s3c_pwmclk_init();
 452 }