1 /* linux/arch/arm/mach-s3c2410/mach-jive.c
3 * Copyright 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/timer.h>
18 #include <linux/init.h>
19 #include <linux/sysdev.h>
20 #include <linux/delay.h>
21 #include <linux/serial_core.h>
22 #include <linux/platform_device.h>
23 #include <linux/i2c.h>
25 #include <video/ili9320.h>
27 #include <linux/spi/spi.h>
29 #include <asm/mach/arch.h>
30 #include <asm/mach/map.h>
31 #include <asm/mach/irq.h>
33 #include <plat/regs-serial.h>
34 #include <plat/nand.h>
37 #include <mach/regs-power.h>
38 #include <mach/regs-gpio.h>
39 #include <mach/regs-mem.h>
40 #include <mach/regs-lcd.h>
41 #include <mach/spi-gpio.h>
44 #include <asm/mach-types.h>
46 #include <linux/mtd/mtd.h>
47 #include <linux/mtd/nand.h>
48 #include <linux/mtd/nand_ecc.h>
49 #include <linux/mtd/partitions.h>
51 #include <plat/clock.h>
52 #include <plat/devs.h>
58 static struct map_desc jive_iodesc[] __initdata = {
61 #define UCON S3C2410_UCON_DEFAULT
62 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
63 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
65 static struct s3c2410_uartcfg jive_uartcfgs[] = {
89 /* Jive flash assignment
91 * 0x00000000-0x00028000 : uboot
92 * 0x00028000-0x0002c000 : uboot env
93 * 0x0002c000-0x00030000 : spare
94 * 0x00030000-0x00200000 : zimage A
95 * 0x00200000-0x01600000 : cramfs A
96 * 0x01600000-0x017d0000 : zimage B
97 * 0x017d0000-0x02bd0000 : cramfs B
98 * 0x02bd0000-0x03fd0000 : yaffs
100 static struct mtd_partition jive_imageA_nand_part[] = {
102 #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
103 /* Don't allow access to the bootloader from linux */
107 .size = (160 * SZ_1K),
108 .mask_flags = MTD_WRITEABLE, /* force read-only */
114 .offset = (176 * SZ_1K),
115 .size = (16 * SZ_1K),
121 .name = "kernel (ro)",
122 .offset = (192 * SZ_1K),
123 .size = (SZ_2M) - (192 * SZ_1K),
124 .mask_flags = MTD_WRITEABLE, /* force read-only */
128 .size = (20 * SZ_1M),
129 .mask_flags = MTD_WRITEABLE, /* force read-only */
135 .offset = (44 * SZ_1M),
136 .size = (20 * SZ_1M),
139 /* bootloader environment */
142 .offset = (160 * SZ_1K),
143 .size = (16 * SZ_1K),
149 .offset = (22 * SZ_1M),
150 .size = (2 * SZ_1M) - (192 * SZ_1K),
153 .offset = (24 * SZ_1M) - (192*SZ_1K),
154 .size = (20 * SZ_1M),
158 static struct mtd_partition jive_imageB_nand_part[] = {
160 #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
161 /* Don't allow access to the bootloader from linux */
165 .size = (160 * SZ_1K),
166 .mask_flags = MTD_WRITEABLE, /* force read-only */
172 .offset = (176 * SZ_1K),
173 .size = (16 * SZ_1K),
179 .name = "kernel (ro)",
180 .offset = (22 * SZ_1M),
181 .size = (2 * SZ_1M) - (192 * SZ_1K),
182 .mask_flags = MTD_WRITEABLE, /* force read-only */
186 .offset = (24 * SZ_1M) - (192 * SZ_1K),
187 .size = (20 * SZ_1M),
188 .mask_flags = MTD_WRITEABLE, /* force read-only */
194 .offset = (44 * SZ_1M),
195 .size = (20 * SZ_1M),
198 /* bootloader environment */
201 .offset = (160 * SZ_1K),
202 .size = (16 * SZ_1K),
208 .offset = (192 * SZ_1K),
209 .size = (2 * SZ_1M) - (192 * SZ_1K),
212 .offset = (2 * SZ_1M),
213 .size = (20 * SZ_1M),
217 static struct s3c2410_nand_set jive_nand_sets[] = {
221 .nr_partitions = ARRAY_SIZE(jive_imageA_nand_part),
222 .partitions = jive_imageA_nand_part,
226 static struct s3c2410_platform_nand jive_nand_info = {
227 /* set taken from osiris nand timings, possibly still conservative */
231 .sets = jive_nand_sets,
232 .nr_sets = ARRAY_SIZE(jive_nand_sets),
235 static int __init jive_mtdset(char *options)
237 struct s3c2410_nand_set *nand = &jive_nand_sets[0];
240 if (options == NULL || options[0] == '\0')
243 if (strict_strtoul(options, 10, &set)) {
244 printk(KERN_ERR "failed to parse mtdset=%s\n", options);
250 nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
251 nand->partitions = jive_imageB_nand_part;
253 /* this is already setup in the nand info */
256 printk(KERN_ERR "Unknown mtd set %ld specified,"
257 "using default.", set);
263 /* parse the mtdset= option given to the kernel command line */
264 __setup("mtdset=", jive_mtdset);
266 /* LCD timing and setup */
268 #define LCD_XRES (240)
269 #define LCD_YRES (320)
270 #define LCD_LEFT_MARGIN (12)
271 #define LCD_RIGHT_MARGIN (12)
272 #define LCD_LOWER_MARGIN (12)
273 #define LCD_UPPER_MARGIN (12)
274 #define LCD_VSYNC (2)
275 #define LCD_HSYNC (2)
277 #define LCD_REFRESH (60)
279 #define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
280 #define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)
282 struct s3c2410fb_display jive_vgg2432a4_display[] = {
288 .left_margin = LCD_LEFT_MARGIN,
289 .right_margin = LCD_RIGHT_MARGIN,
290 .upper_margin = LCD_UPPER_MARGIN,
291 .lower_margin = LCD_LOWER_MARGIN,
292 .hsync_len = LCD_HSYNC,
293 .vsync_len = LCD_VSYNC,
295 .pixclock = (1000000000000LL /
296 (LCD_REFRESH * LCD_HTOT * LCD_VTOT)),
299 .type = (S3C2410_LCDCON1_TFT16BPP |
300 S3C2410_LCDCON1_TFT),
302 .lcdcon5 = (S3C2410_LCDCON5_FRM565 |
303 S3C2410_LCDCON5_INVVLINE |
304 S3C2410_LCDCON5_INVVFRAME |
305 S3C2410_LCDCON5_INVVDEN |
306 S3C2410_LCDCON5_PWREN),
310 /* todo - put into gpio header */
312 #define S3C2410_GPCCON_MASK(x) (3 << ((x) * 2))
313 #define S3C2410_GPDCON_MASK(x) (3 << ((x) * 2))
315 struct s3c2410fb_mach_info jive_lcd_config = {
316 .displays = jive_vgg2432a4_display,
317 .num_displays = ARRAY_SIZE(jive_vgg2432a4_display),
318 .default_display = 0,
320 /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
321 * and disable the pull down resistors on pins we are using for LCD
324 .gpcup = (0xf << 1) | (0x3f << 10),
326 .gpccon = (S3C2410_GPC1_VCLK | S3C2410_GPC2_VLINE |
327 S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
328 S3C2410_GPC10_VD2 | S3C2410_GPC11_VD3 |
329 S3C2410_GPC12_VD4 | S3C2410_GPC13_VD5 |
330 S3C2410_GPC14_VD6 | S3C2410_GPC15_VD7),
332 .gpccon_mask = (S3C2410_GPCCON_MASK(1) | S3C2410_GPCCON_MASK(2) |
333 S3C2410_GPCCON_MASK(3) | S3C2410_GPCCON_MASK(4) |
334 S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
335 S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
336 S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
338 .gpdup = (0x3f << 2) | (0x3f << 10),
340 .gpdcon = (S3C2410_GPD2_VD10 | S3C2410_GPD3_VD11 |
341 S3C2410_GPD4_VD12 | S3C2410_GPD5_VD13 |
342 S3C2410_GPD6_VD14 | S3C2410_GPD7_VD15 |
343 S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
344 S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
345 S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),
347 .gpdcon_mask = (S3C2410_GPDCON_MASK(2) | S3C2410_GPDCON_MASK(3) |
348 S3C2410_GPDCON_MASK(4) | S3C2410_GPDCON_MASK(5) |
349 S3C2410_GPDCON_MASK(6) | S3C2410_GPDCON_MASK(7) |
350 S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
351 S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
352 S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
355 /* ILI9320 support. */
357 static void jive_lcm_reset(unsigned int set)
359 printk(KERN_DEBUG "%s(%d)\n", __func__, set);
361 s3c2410_gpio_setpin(S3C2410_GPG13, set);
362 s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
365 #undef LCD_UPPER_MARGIN
366 #define LCD_UPPER_MARGIN 2
368 static struct ili9320_platdata jive_lcm_config = {
372 .reset = jive_lcm_reset,
373 .suspend = ILI9320_SUSPEND_DEEP,
375 .entry_mode = ILI9320_ENTRYMODE_ID(3) | ILI9320_ENTRYMODE_BGR,
376 .display2 = (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) |
377 ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)),
380 .rgb_if1 = (ILI9320_RGBIF1_RIM_RGB18 |
381 ILI9320_RGBIF1_RM | ILI9320_RGBIF1_CLK_RGBIF),
382 .rgb_if2 = ILI9320_RGBIF2_DPL,
385 .interface4 = (ILI9320_INTERFACE4_RTNE(16) |
386 ILI9320_INTERFACE4_DIVE(1)),
391 /* LCD SPI support */
393 static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs)
395 s3c2410_gpio_setpin(S3C2410_GPB7, cs ? 0 : 1);
398 static struct s3c2410_spigpio_info jive_lcd_spi = {
400 .pin_clk = S3C2410_GPG8,
401 .pin_mosi = S3C2410_GPB8,
403 .chip_select = jive_lcd_spi_chipselect,
406 static struct platform_device jive_device_lcdspi = {
407 .name = "spi_s3c24xx_gpio",
410 .dev.platform_data = &jive_lcd_spi,
413 /* WM8750 audio code SPI definition */
415 static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs)
417 s3c2410_gpio_setpin(S3C2410_GPH10, cs ? 0 : 1);
420 static struct s3c2410_spigpio_info jive_wm8750_spi = {
422 .pin_clk = S3C2410_GPB4,
423 .pin_mosi = S3C2410_GPB9,
425 .chip_select = jive_wm8750_chipselect,
428 static struct platform_device jive_device_wm8750 = {
429 .name = "spi_s3c24xx_gpio",
432 .dev.platform_data = &jive_wm8750_spi,
435 /* JIVE SPI devices. */
437 static struct spi_board_info __initdata jive_spi_devs[] = {
439 .modalias = "VGG2432A4",
442 .mode = SPI_MODE_3, /* CPOL=1, CPHA=1 */
443 .max_speed_hz = 100000,
444 .platform_data = &jive_lcm_config,
446 .modalias = "WM8750",
449 .mode = SPI_MODE_0, /* CPOL=0, CPHA=0 */
450 .max_speed_hz = 100000,
454 /* I2C bus and device configuration. */
456 static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
457 .max_freq = 80 * 1000,
458 .bus_freq = 50 * 1000,
459 .flags = S3C_IICFLG_FILTER,
463 static struct i2c_board_info jive_i2c_devs[] __initdata = {
465 I2C_BOARD_INFO("lis302dl", 0x1c),
470 /* The platform devices being used. */
472 static struct platform_device *jive_devices[] __initdata = {
481 &s3c_device_usbgadget,
484 static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
485 .vbus_pin = S3C2410_GPG1, /* detect is on GPG1 */
488 /* Jive power management device */
491 static int jive_pm_suspend(struct sys_device *sd, pm_message_t state)
493 /* Write the magic value u-boot uses to check for resume into
494 * the INFORM0 register, and ensure INFORM1 is set to the
495 * correct address to resume from. */
497 __raw_writel(0x2BED, S3C2412_INFORM0);
498 __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2412_INFORM1);
503 static int jive_pm_resume(struct sys_device *sd)
505 __raw_writel(0x0, S3C2412_INFORM0);
510 #define jive_pm_suspend NULL
511 #define jive_pm_resume NULL
514 static struct sysdev_class jive_pm_sysclass = {
516 .suspend = jive_pm_suspend,
517 .resume = jive_pm_resume,
520 static struct sys_device jive_pm_sysdev = {
521 .cls = &jive_pm_sysclass,
524 static void __init jive_map_io(void)
526 s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
527 s3c24xx_init_clocks(12000000);
528 s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
531 static void jive_power_off(void)
533 printk(KERN_INFO "powering system down...\n");
535 s3c2410_gpio_setpin(S3C2410_GPC5, 1);
536 s3c2410_gpio_cfgpin(S3C2410_GPC5, S3C2410_GPIO_OUTPUT);
539 static void __init jive_machine_init(void)
541 /* register system devices for managing low level suspend */
543 sysdev_class_register(&jive_pm_sysclass);
544 sysdev_register(&jive_pm_sysdev);
546 /* write our sleep configurations for the IO. Pull down all unused
547 * IO, ensure that we have turned off all peripherals we do not
548 * need, and configure the ones we do need. */
552 __raw_writel(S3C2412_SLPCON_IN(0) |
553 S3C2412_SLPCON_PULL(1) |
554 S3C2412_SLPCON_HIGH(2) |
555 S3C2412_SLPCON_PULL(3) |
556 S3C2412_SLPCON_PULL(4) |
557 S3C2412_SLPCON_PULL(5) |
558 S3C2412_SLPCON_PULL(6) |
559 S3C2412_SLPCON_HIGH(7) |
560 S3C2412_SLPCON_PULL(8) |
561 S3C2412_SLPCON_PULL(9) |
562 S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);
566 __raw_writel(S3C2412_SLPCON_PULL(0) |
567 S3C2412_SLPCON_PULL(1) |
568 S3C2412_SLPCON_PULL(2) |
569 S3C2412_SLPCON_PULL(3) |
570 S3C2412_SLPCON_PULL(4) |
571 S3C2412_SLPCON_PULL(5) |
572 S3C2412_SLPCON_LOW(6) |
573 S3C2412_SLPCON_PULL(6) |
574 S3C2412_SLPCON_PULL(7) |
575 S3C2412_SLPCON_PULL(8) |
576 S3C2412_SLPCON_PULL(9) |
577 S3C2412_SLPCON_PULL(10) |
578 S3C2412_SLPCON_PULL(11) |
579 S3C2412_SLPCON_PULL(12) |
580 S3C2412_SLPCON_PULL(13) |
581 S3C2412_SLPCON_PULL(14) |
582 S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);
586 __raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);
590 __raw_writel(S3C2412_SLPCON_LOW(0) |
591 S3C2412_SLPCON_LOW(1) |
592 S3C2412_SLPCON_LOW(2) |
593 S3C2412_SLPCON_EINT(3) |
594 S3C2412_SLPCON_EINT(4) |
595 S3C2412_SLPCON_EINT(5) |
596 S3C2412_SLPCON_EINT(6) |
597 S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);
601 __raw_writel(S3C2412_SLPCON_IN(0) |
602 S3C2412_SLPCON_IN(1) |
603 S3C2412_SLPCON_IN(2) |
604 S3C2412_SLPCON_IN(3) |
605 S3C2412_SLPCON_IN(4) |
606 S3C2412_SLPCON_IN(5) |
607 S3C2412_SLPCON_IN(6) |
608 S3C2412_SLPCON_IN(7) |
609 S3C2412_SLPCON_PULL(8) |
610 S3C2412_SLPCON_PULL(9) |
611 S3C2412_SLPCON_IN(10) |
612 S3C2412_SLPCON_PULL(11) |
613 S3C2412_SLPCON_PULL(12) |
614 S3C2412_SLPCON_PULL(13) |
615 S3C2412_SLPCON_IN(14) |
616 S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);
620 __raw_writel(S3C2412_SLPCON_PULL(0) |
621 S3C2412_SLPCON_PULL(1) |
622 S3C2412_SLPCON_PULL(2) |
623 S3C2412_SLPCON_PULL(3) |
624 S3C2412_SLPCON_PULL(4) |
625 S3C2412_SLPCON_PULL(5) |
626 S3C2412_SLPCON_PULL(6) |
627 S3C2412_SLPCON_IN(7) |
628 S3C2412_SLPCON_IN(8) |
629 S3C2412_SLPCON_PULL(9) |
630 S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);
632 /* initialise the power management now we've setup everything. */
636 s3c_device_nand.dev.platform_data = &jive_nand_info;
638 /* initialise the spi */
640 s3c2410_gpio_setpin(S3C2410_GPG13, 0);
641 s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
643 s3c2410_gpio_setpin(S3C2410_GPB7, 1);
644 s3c2410_gpio_cfgpin(S3C2410_GPB7, S3C2410_GPIO_OUTPUT);
646 s3c2410_gpio_setpin(S3C2410_GPB6, 0);
647 s3c2410_gpio_cfgpin(S3C2410_GPB6, S3C2410_GPIO_OUTPUT);
649 s3c2410_gpio_setpin(S3C2410_GPG8, 1);
650 s3c2410_gpio_cfgpin(S3C2410_GPG8, S3C2410_GPIO_OUTPUT);
652 /* initialise the WM8750 spi */
654 s3c2410_gpio_setpin(S3C2410_GPH10, 1);
655 s3c2410_gpio_cfgpin(S3C2410_GPH10, S3C2410_GPIO_OUTPUT);
657 /* Turn off suspend on both USB ports, and switch the
658 * selectable USB port to USB device mode. */
660 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
661 S3C2410_MISCCR_USBSUSPND0 |
662 S3C2410_MISCCR_USBSUSPND1, 0x0);
664 s3c24xx_udc_set_platdata(&jive_udc_cfg);
665 s3c24xx_fb_set_platdata(&jive_lcd_config);
667 spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
669 s3c_i2c0_set_platdata(&jive_i2c_cfg);
670 i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
672 pm_power_off = jive_power_off;
674 platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
677 MACHINE_START(JIVE, "JIVE")
678 /* Maintainer: Ben Dooks <ben@fluff.org> */
679 .phys_io = S3C2410_PA_UART,
680 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
681 .boot_params = S3C2410_SDRAM_PA + 0x100,
683 .init_irq = s3c24xx_init_irq,
684 .map_io = jive_map_io,
685 .init_machine = jive_machine_init,
686 .timer = &s3c24xx_timer,