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   1 /* linux/arch/arm/mach-s3c2410/clock.c
   2  *
   3  * Copyright (c) 2004-2005 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 Clock control support
   7  *
   8  * Based on, and code from linux/arch/arm/mach-versatile/clock.c
   9  **
  10  **  Copyright (C) 2004 ARM Limited.
  11  **  Written by Deep Blue Solutions Limited.
  12  *
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  27 */
  28
  29 #include <linux/init.h>
  30 #include <linux/module.h>
  31 #include <linux/kernel.h>
  32 #include <linux/list.h>
  33 #include <linux/errno.h>
  34 #include <linux/err.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/sysdev.h>
  37
  38 #include <linux/interrupt.h>
  39 #include <linux/ioport.h>
  40
  41 #include <asm/hardware.h>
  42 #include <asm/atomic.h>
  43 #include <asm/irq.h>
  44 #include <asm/io.h>
  45
  46 #include <asm/hardware/clock.h>
  47 #include <asm/arch/regs-clock.h>
  48
  49 #include "clock.h"
  50 #include "cpu.h"
  51
  52 /* clock information */
  53
  54 static LIST_HEAD(clocks);
  55 static DECLARE_MUTEX(clocks_sem);
  56
  57 /* old functions */
  58
  59 void inline s3c24xx_clk_enable(unsigned int clocks, unsigned int enable)
  60 {
  61         unsigned long clkcon;
  62         unsigned long flags;
  63
  64         local_irq_save(flags);
  65
  66         clkcon = __raw_readl(S3C2410_CLKCON);
  67         clkcon &= ~clocks;
  68
  69         if (enable)
  70                 clkcon |= clocks;
  71
  72         /* ensure none of the special function bits set */
  73         clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
  74
  75         __raw_writel(clkcon, S3C2410_CLKCON);
  76
  77         local_irq_restore(flags);
  78 }
  79
  80 /* enable and disable calls for use with the clk struct */
  81
  82 static int clk_null_enable(struct clk *clk, int enable)
  83 {
  84         return 0;
  85 }
  86
  87 int s3c24xx_clkcon_enable(struct clk *clk, int enable)
  88 {
  89         s3c24xx_clk_enable(clk->ctrlbit, enable);
  90         return 0;
  91 }
  92
  93 /* Clock API calls */
  94
  95 struct clk *clk_get(struct device *dev, const char *id)
  96 {
  97         struct clk *p;
  98         struct clk *clk = ERR_PTR(-ENOENT);
  99         int idno;
 100
 101         if (dev == NULL || dev->bus != &platform_bus_type)
 102                 idno = -1;
 103         else
 104                 idno = to_platform_device(dev)->id;
 105
 106         down(&clocks_sem);
 107
 108         list_for_each_entry(p, &clocks, list) {
 109                 if (p->id == idno &&
 110                     strcmp(id, p->name) == 0 &&
 111                     try_module_get(p->owner)) {
 112                         clk = p;
 113                         break;
 114                 }
 115         }
 116
 117         /* check for the case where a device was supplied, but the
 118          * clock that was being searched for is not device specific */
 119
 120         if (IS_ERR(clk)) {
 121                 list_for_each_entry(p, &clocks, list) {
 122                         if (p->id == -1 && strcmp(id, p->name) == 0 &&
 123                             try_module_get(p->owner)) {
 124                                 clk = p;
 125                                 break;
 126                         }
 127                 }
 128         }
 129
 130         up(&clocks_sem);
 131         return clk;
 132 }
 133
 134 void clk_put(struct clk *clk)
 135 {
 136         module_put(clk->owner);
 137 }
 138
 139 int clk_enable(struct clk *clk)
 140 {
 141         if (IS_ERR(clk))
 142                 return -EINVAL;
 143
 144         return (clk->enable)(clk, 1);
 145 }
 146
 147 void clk_disable(struct clk *clk)
 148 {
 149         if (!IS_ERR(clk))
 150                 (clk->enable)(clk, 0);
 151 }
 152
 153
 154 unsigned long clk_get_rate(struct clk *clk)
 155 {
 156         if (IS_ERR(clk))
 157                 return 0;
 158
 159         if (clk->rate != 0)
 160                 return clk->rate;
 161
 162         while (clk->parent != NULL && clk->rate == 0)
 163                 clk = clk->parent;
 164
 165         return clk->rate;
 166 }
 167
 168 long clk_round_rate(struct clk *clk, unsigned long rate)
 169 {
 170         return rate;
 171 }
 172
 173 int clk_set_rate(struct clk *clk, unsigned long rate)
 174 {
 175         return -EINVAL;
 176 }
 177
 178 struct clk *clk_get_parent(struct clk *clk)
 179 {
 180         return clk->parent;
 181 }
 182
 183 EXPORT_SYMBOL(clk_get);
 184 EXPORT_SYMBOL(clk_put);
 185 EXPORT_SYMBOL(clk_enable);
 186 EXPORT_SYMBOL(clk_disable);
 187 EXPORT_SYMBOL(clk_get_rate);
 188 EXPORT_SYMBOL(clk_round_rate);
 189 EXPORT_SYMBOL(clk_set_rate);
 190 EXPORT_SYMBOL(clk_get_parent);
 191
 192 /* base clocks */
 193
 194 static struct clk clk_xtal = {
 195         .name           = "xtal",
 196         .id             = -1,
 197         .rate           = 0,
 198         .parent         = NULL,
 199         .ctrlbit        = 0,
 200 };
 201
 202 static struct clk clk_f = {
 203         .name           = "fclk",
 204         .id             = -1,
 205         .rate           = 0,
 206         .parent         = NULL,
 207         .ctrlbit        = 0,
 208 };
 209
 210 static struct clk clk_h = {
 211         .name           = "hclk",
 212         .id             = -1,
 213         .rate           = 0,
 214         .parent         = NULL,
 215         .ctrlbit        = 0,
 216 };
 217
 218 static struct clk clk_p = {
 219         .name           = "pclk",
 220         .id             = -1,
 221         .rate           = 0,
 222         .parent         = NULL,
 223         .ctrlbit        = 0,
 224 };
 225
 226 /* clocks that could be registered by external code */
 227
 228 struct clk s3c24xx_dclk0 = {
 229         .name           = "dclk0",
 230         .id             = -1,
 231 };
 232
 233 struct clk s3c24xx_dclk1 = {
 234         .name           = "dclk1",
 235         .id             = -1,
 236 };
 237
 238 struct clk s3c24xx_clkout0 = {
 239         .name           = "clkout0",
 240         .id             = -1,
 241 };
 242
 243 struct clk s3c24xx_clkout1 = {
 244         .name           = "clkout1",
 245         .id             = -1,
 246 };
 247
 248 struct clk s3c24xx_uclk = {
 249         .name           = "uclk",
 250         .id             = -1,
 251 };
 252
 253
 254 /* clock definitions */
 255
 256 static struct clk init_clocks[] = {
 257         { .name    = "nand",
 258           .id      = -1,
 259           .parent  = &clk_h,
 260           .enable  = s3c24xx_clkcon_enable,
 261           .ctrlbit = S3C2410_CLKCON_NAND
 262         },
 263         { .name    = "lcd",
 264           .id      = -1,
 265           .parent  = &clk_h,
 266           .enable  = s3c24xx_clkcon_enable,
 267           .ctrlbit = S3C2410_CLKCON_LCDC
 268         },
 269         { .name    = "usb-host",
 270           .id      = -1,
 271           .parent  = &clk_h,
 272           .enable  = s3c24xx_clkcon_enable,
 273           .ctrlbit = S3C2410_CLKCON_USBH
 274         },
 275         { .name    = "usb-device",
 276           .id      = -1,
 277           .parent  = &clk_h,
 278           .enable  = s3c24xx_clkcon_enable,
 279           .ctrlbit = S3C2410_CLKCON_USBD
 280         },
 281         { .name    = "timers",
 282           .id      = -1,
 283           .parent  = &clk_p,
 284           .enable  = s3c24xx_clkcon_enable,
 285           .ctrlbit = S3C2410_CLKCON_PWMT
 286         },
 287         { .name    = "sdi",
 288           .id      = -1,
 289           .parent  = &clk_p,
 290           .enable  = s3c24xx_clkcon_enable,
 291           .ctrlbit = S3C2410_CLKCON_SDI
 292         },
 293         { .name    = "uart",
 294           .id      = 0,
 295           .parent  = &clk_p,
 296           .enable  = s3c24xx_clkcon_enable,
 297           .ctrlbit = S3C2410_CLKCON_UART0
 298         },
 299         { .name    = "uart",
 300           .id      = 1,
 301           .parent  = &clk_p,
 302           .enable  = s3c24xx_clkcon_enable,
 303           .ctrlbit = S3C2410_CLKCON_UART1
 304         },
 305         { .name    = "uart",
 306           .id      = 2,
 307           .parent  = &clk_p,
 308           .enable  = s3c24xx_clkcon_enable,
 309           .ctrlbit = S3C2410_CLKCON_UART2
 310         },
 311         { .name    = "gpio",
 312           .id      = -1,
 313           .parent  = &clk_p,
 314           .enable  = s3c24xx_clkcon_enable,
 315           .ctrlbit = S3C2410_CLKCON_GPIO
 316         },
 317         { .name    = "rtc",
 318           .id      = -1,
 319           .parent  = &clk_p,
 320           .enable  = s3c24xx_clkcon_enable,
 321           .ctrlbit = S3C2410_CLKCON_RTC
 322         },
 323         { .name    = "adc",
 324           .id      = -1,
 325           .parent  = &clk_p,
 326           .enable  = s3c24xx_clkcon_enable,
 327           .ctrlbit = S3C2410_CLKCON_ADC
 328         },
 329         { .name    = "i2c",
 330           .id      = -1,
 331           .parent  = &clk_p,
 332           .enable  = s3c24xx_clkcon_enable,
 333           .ctrlbit = S3C2410_CLKCON_IIC
 334         },
 335         { .name    = "iis",
 336           .id      = -1,
 337           .parent  = &clk_p,
 338           .enable  = s3c24xx_clkcon_enable,
 339           .ctrlbit = S3C2410_CLKCON_IIS
 340         },
 341         { .name    = "spi",
 342           .id      = -1,
 343           .parent  = &clk_p,
 344           .enable  = s3c24xx_clkcon_enable,
 345           .ctrlbit = S3C2410_CLKCON_SPI
 346         },
 347         { .name    = "watchdog",
 348           .id      = -1,
 349           .parent  = &clk_p,
 350           .ctrlbit = 0
 351         }
 352 };
 353
 354 /* initialise the clock system */
 355
 356 int s3c24xx_register_clock(struct clk *clk)
 357 {
 358         clk->owner = THIS_MODULE;
 359
 360         if (clk->enable == NULL)
 361                 clk->enable = clk_null_enable;
 362
 363         /* add to the list of available clocks */
 364
 365         down(&clocks_sem);
 366         list_add(&clk->list, &clocks);
 367         up(&clocks_sem);
 368
 369         return 0;
 370 }
 371
 372 /* initalise all the clocks */
 373
 374 int __init s3c24xx_setup_clocks(unsigned long xtal,
 375                                 unsigned long fclk,
 376                                 unsigned long hclk,
 377                                 unsigned long pclk)
 378 {
 379         unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
 380         struct clk *clkp = init_clocks;
 381         int ptr;
 382         int ret;
 383
 384         printk(KERN_INFO "S3C2410 Clocks, (c) 2004 Simtec Electronics\n");
 385
 386         /* initialise the main system clocks */
 387
 388         clk_xtal.rate = xtal;
 389
 390         clk_h.rate = hclk;
 391         clk_p.rate = pclk;
 392         clk_f.rate = fclk;
 393
 394         /* it looks like just setting the register here is not good
 395          * enough, and causes the odd hang at initial boot time, so
 396          * do all of them indivdually.
 397          *
 398          * I think disabling the LCD clock if the LCD is active is
 399          * very dangerous, and therefore the bootloader should be
 400          * careful to not enable the LCD clock if it is not needed.
 401          *
 402          * and of course, this looks neater
 403          */
 404
 405         s3c24xx_clk_enable(S3C2410_CLKCON_NAND, 0);
 406         s3c24xx_clk_enable(S3C2410_CLKCON_USBH, 0);
 407         s3c24xx_clk_enable(S3C2410_CLKCON_USBD, 0);
 408         s3c24xx_clk_enable(S3C2410_CLKCON_ADC, 0);
 409         s3c24xx_clk_enable(S3C2410_CLKCON_IIC, 0);
 410         s3c24xx_clk_enable(S3C2410_CLKCON_SPI, 0);
 411
 412         /* assume uart clocks are correctly setup */
 413
 414         /* register our clocks */
 415
 416         if (s3c24xx_register_clock(&clk_xtal) < 0)
 417                 printk(KERN_ERR "failed to register master xtal\n");
 418
 419         if (s3c24xx_register_clock(&clk_f) < 0)
 420                 printk(KERN_ERR "failed to register cpu fclk\n");
 421
 422         if (s3c24xx_register_clock(&clk_h) < 0)
 423                 printk(KERN_ERR "failed to register cpu hclk\n");
 424
 425         if (s3c24xx_register_clock(&clk_p) < 0)
 426                 printk(KERN_ERR "failed to register cpu pclk\n");
 427
 428         /* register clocks from clock array */
 429
 430         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
 431                 ret = s3c24xx_register_clock(clkp);
 432                 if (ret < 0) {
 433                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 434                                clkp->name, ret);
 435                 }
 436         }
 437
 438         /* show the clock-slow value */
 439
 440         printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
 441                print_mhz(xtal / ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
 442                (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
 443                (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
 444                (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
 445
 446         return 0;
 447 }