2 * linux/arch/arm/mach-realview/core.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/amba/bus.h>
27 #include <linux/amba/clcd.h>
29 #include <linux/smsc911x.h>
30 #include <linux/ata_platform.h>
31 #include <linux/amba/mmci.h>
33 #include <asm/clkdev.h>
34 #include <asm/system.h>
35 #include <mach/hardware.h>
38 #include <asm/mach-types.h>
39 #include <asm/hardware/arm_timer.h>
40 #include <asm/hardware/icst.h>
42 #include <asm/mach/arch.h>
43 #include <asm/mach/flash.h>
44 #include <asm/mach/irq.h>
45 #include <asm/mach/map.h>
47 #include <asm/hardware/gic.h>
49 #include <mach/clkdev.h>
50 #include <mach/platform.h>
51 #include <mach/irqs.h>
52 #include <plat/timer-sp.h>
56 /* used by entry-macro.S and platsmp.c */
57 void __iomem *gic_cpu_base_addr;
59 #ifdef CONFIG_ZONE_DMA
61 * Adjust the zones if there are restrictions for DMA access.
63 void __init realview_adjust_zones(int node, unsigned long *size,
66 unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
68 if (!machine_is_realview_pbx() || node || (size[0] <= dma_size))
71 size[ZONE_NORMAL] = size[0] - dma_size;
72 size[ZONE_DMA] = dma_size;
73 hole[ZONE_NORMAL] = hole[0];
79 #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
81 static int realview_flash_init(void)
85 val = __raw_readl(REALVIEW_FLASHCTRL);
86 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
87 __raw_writel(val, REALVIEW_FLASHCTRL);
92 static void realview_flash_exit(void)
96 val = __raw_readl(REALVIEW_FLASHCTRL);
97 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
98 __raw_writel(val, REALVIEW_FLASHCTRL);
101 static void realview_flash_set_vpp(int on)
105 val = __raw_readl(REALVIEW_FLASHCTRL);
107 val |= REALVIEW_FLASHPROG_FLVPPEN;
109 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
110 __raw_writel(val, REALVIEW_FLASHCTRL);
113 static struct flash_platform_data realview_flash_data = {
114 .map_name = "cfi_probe",
116 .init = realview_flash_init,
117 .exit = realview_flash_exit,
118 .set_vpp = realview_flash_set_vpp,
121 struct platform_device realview_flash_device = {
125 .platform_data = &realview_flash_data,
129 int realview_flash_register(struct resource *res, u32 num)
131 realview_flash_device.resource = res;
132 realview_flash_device.num_resources = num;
133 return platform_device_register(&realview_flash_device);
136 static struct smsc911x_platform_config smsc911x_config = {
137 .flags = SMSC911X_USE_32BIT,
138 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
139 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
140 .phy_interface = PHY_INTERFACE_MODE_MII,
143 static struct platform_device realview_eth_device = {
149 int realview_eth_register(const char *name, struct resource *res)
152 realview_eth_device.name = name;
153 realview_eth_device.resource = res;
154 if (strcmp(realview_eth_device.name, "smsc911x") == 0)
155 realview_eth_device.dev.platform_data = &smsc911x_config;
157 return platform_device_register(&realview_eth_device);
160 struct platform_device realview_usb_device = {
165 int realview_usb_register(struct resource *res)
167 realview_usb_device.resource = res;
168 return platform_device_register(&realview_usb_device);
171 static struct pata_platform_info pata_platform_data = {
175 static struct resource pata_resources[] = {
177 .start = REALVIEW_CF_BASE,
178 .end = REALVIEW_CF_BASE + 0xff,
179 .flags = IORESOURCE_MEM,
182 .start = REALVIEW_CF_BASE + 0x100,
183 .end = REALVIEW_CF_BASE + SZ_4K - 1,
184 .flags = IORESOURCE_MEM,
188 struct platform_device realview_cf_device = {
189 .name = "pata_platform",
191 .num_resources = ARRAY_SIZE(pata_resources),
192 .resource = pata_resources,
194 .platform_data = &pata_platform_data,
198 static struct resource realview_i2c_resource = {
199 .start = REALVIEW_I2C_BASE,
200 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
201 .flags = IORESOURCE_MEM,
204 struct platform_device realview_i2c_device = {
205 .name = "versatile-i2c",
208 .resource = &realview_i2c_resource,
211 static struct i2c_board_info realview_i2c_board_info[] = {
213 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
217 static int __init realview_i2c_init(void)
219 return i2c_register_board_info(0, realview_i2c_board_info,
220 ARRAY_SIZE(realview_i2c_board_info));
222 arch_initcall(realview_i2c_init);
224 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
227 * This is only used if GPIOLIB support is disabled
229 static unsigned int realview_mmc_status(struct device *dev)
231 struct amba_device *adev = container_of(dev, struct amba_device, dev);
234 if (adev->res.start == REALVIEW_MMCI0_BASE)
239 return readl(REALVIEW_SYSMCI) & mask;
242 struct mmci_platform_data realview_mmc0_plat_data = {
243 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
244 .status = realview_mmc_status,
249 struct mmci_platform_data realview_mmc1_plat_data = {
250 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
251 .status = realview_mmc_status,
259 static const struct icst_params realview_oscvco_params = {
261 .vco_max = ICST307_VCO_MAX,
262 .vco_min = ICST307_VCO_MIN,
267 .s2div = icst307_s2div,
268 .idx2s = icst307_idx2s,
271 static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
273 void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
276 val = readl(clk->vcoreg) & ~0x7ffff;
277 val |= vco.v | (vco.r << 9) | (vco.s << 16);
279 writel(0xa05f, sys_lock);
280 writel(val, clk->vcoreg);
284 static const struct clk_ops oscvco_clk_ops = {
285 .round = icst_clk_round,
287 .setvco = realview_oscvco_set,
290 static struct clk oscvco_clk = {
291 .ops = &oscvco_clk_ops,
292 .params = &realview_oscvco_params,
296 * These are fixed clocks.
298 static struct clk ref24_clk = {
302 static struct clk_lookup lookups[] = {
304 .dev_id = "dev:uart0",
307 .dev_id = "dev:uart1",
310 .dev_id = "dev:uart2",
313 .dev_id = "fpga:uart3",
316 .dev_id = "fpga:kmi0",
319 .dev_id = "fpga:kmi1",
322 .dev_id = "fpga:mmc0",
325 .dev_id = "dev:clcd",
328 .dev_id = "issp:clcd",
333 static int __init clk_init(void)
335 if (machine_is_realview_pb1176())
336 oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
338 oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
340 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
344 arch_initcall(clk_init);
349 #define SYS_CLCD_NLCDIOON (1 << 2)
350 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
351 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
352 #define SYS_CLCD_ID_MASK (0x1f << 8)
353 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
354 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
355 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
356 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
357 #define SYS_CLCD_ID_VGA (0x1f << 8)
359 static struct clcd_panel vga = {
373 .vmode = FB_VMODE_NONINTERLACED,
377 .tim2 = TIM2_BCD | TIM2_IPC,
378 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
382 static struct clcd_panel xvga = {
396 .vmode = FB_VMODE_NONINTERLACED,
400 .tim2 = TIM2_BCD | TIM2_IPC,
401 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
405 static struct clcd_panel sanyo_3_8_in = {
407 .name = "Sanyo QVGA",
419 .vmode = FB_VMODE_NONINTERLACED,
424 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
428 static struct clcd_panel sanyo_2_5_in = {
430 .name = "Sanyo QVGA Portrait",
441 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
442 .vmode = FB_VMODE_NONINTERLACED,
446 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
447 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
451 static struct clcd_panel epson_2_2_in = {
453 .name = "Epson QCIF",
465 .vmode = FB_VMODE_NONINTERLACED,
469 .tim2 = TIM2_BCD | TIM2_IPC,
470 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
475 * Detect which LCD panel is connected, and return the appropriate
476 * clcd_panel structure. Note: we do not have any information on
477 * the required timings for the 8.4in panel, so we presently assume
480 static struct clcd_panel *realview_clcd_panel(void)
482 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
483 struct clcd_panel *vga_panel;
484 struct clcd_panel *panel;
487 if (machine_is_realview_eb())
492 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
493 if (val == SYS_CLCD_ID_SANYO_3_8)
494 panel = &sanyo_3_8_in;
495 else if (val == SYS_CLCD_ID_SANYO_2_5)
496 panel = &sanyo_2_5_in;
497 else if (val == SYS_CLCD_ID_EPSON_2_2)
498 panel = &epson_2_2_in;
499 else if (val == SYS_CLCD_ID_VGA)
502 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
511 * Disable all display connectors on the interface module.
513 static void realview_clcd_disable(struct clcd_fb *fb)
515 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
518 val = readl(sys_clcd);
519 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
520 writel(val, sys_clcd);
524 * Enable the relevant connector on the interface module.
526 static void realview_clcd_enable(struct clcd_fb *fb)
528 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
534 val = readl(sys_clcd);
535 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
536 writel(val, sys_clcd);
539 static int realview_clcd_setup(struct clcd_fb *fb)
541 unsigned long framesize;
544 if (machine_is_realview_eb())
546 framesize = 640 * 480 * 2;
549 framesize = 1024 * 768 * 2;
551 fb->panel = realview_clcd_panel();
553 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
554 &dma, GFP_KERNEL | GFP_DMA);
555 if (!fb->fb.screen_base) {
556 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
560 fb->fb.fix.smem_start = dma;
561 fb->fb.fix.smem_len = framesize;
566 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
568 return dma_mmap_writecombine(&fb->dev->dev, vma,
570 fb->fb.fix.smem_start,
571 fb->fb.fix.smem_len);
574 static void realview_clcd_remove(struct clcd_fb *fb)
576 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
577 fb->fb.screen_base, fb->fb.fix.smem_start);
580 struct clcd_board clcd_plat_data = {
582 .check = clcdfb_check,
583 .decode = clcdfb_decode,
584 .disable = realview_clcd_disable,
585 .enable = realview_clcd_enable,
586 .setup = realview_clcd_setup,
587 .mmap = realview_clcd_mmap,
588 .remove = realview_clcd_remove,
592 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
594 void realview_leds_event(led_event_t ledevt)
598 u32 led = 1 << smp_processor_id();
600 local_irq_save(flags);
601 val = readl(VA_LEDS_BASE);
613 val = val ^ REALVIEW_SYS_LED7;
624 writel(val, VA_LEDS_BASE);
625 local_irq_restore(flags);
627 #endif /* CONFIG_LEDS */
630 * Where is the timer (VA)?
632 void __iomem *timer0_va_base;
633 void __iomem *timer1_va_base;
634 void __iomem *timer2_va_base;
635 void __iomem *timer3_va_base;
638 * Set up the clock source and clock events devices
640 void __init realview_timer_init(unsigned int timer_irq)
645 * set clock frequency:
646 * REALVIEW_REFCLK is 32KHz
647 * REALVIEW_TIMCLK is 1MHz
649 val = readl(__io_address(REALVIEW_SCTL_BASE));
650 writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
651 (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
652 (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
653 (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
654 __io_address(REALVIEW_SCTL_BASE));
657 * Initialise to a known state (all timers off)
659 writel(0, timer0_va_base + TIMER_CTRL);
660 writel(0, timer1_va_base + TIMER_CTRL);
661 writel(0, timer2_va_base + TIMER_CTRL);
662 writel(0, timer3_va_base + TIMER_CTRL);
664 sp804_clocksource_init(timer3_va_base);
665 sp804_clockevents_init(timer0_va_base, timer_irq);
669 * Setup the memory banks.
671 void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from,
672 struct meminfo *meminfo)
675 * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
676 * Half of this is mirrored at 0.
678 #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
679 meminfo->bank[0].start = 0x70000000;
680 meminfo->bank[0].size = SZ_512M;
681 meminfo->nr_banks = 1;
683 meminfo->bank[0].start = 0;
684 meminfo->bank[0].size = SZ_256M;
685 meminfo->nr_banks = 1;