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   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28
  29 #include <plat/sram.h>
  30 #include <plat/clockdomain.h>
  31 #include <plat/powerdomain.h>
  32 #include <plat/control.h>
  33 #include <plat/serial.h>
  34 #include <plat/sdrc.h>
  35 #include <plat/prcm.h>
  36 #include <plat/gpmc.h>
  37 #include <plat/dma.h>
  38
  39 #include <asm/tlbflush.h>
  40
  41 #include "cm.h"
  42 #include "cm-regbits-34xx.h"
  43 #include "prm-regbits-34xx.h"
  44
  45 #include "prm.h"
  46 #include "pm.h"
  47 #include "sdrc.h"
  48
  49 #define SDRC_POWER_AUTOCOUNT_SHIFT 8
  50 #define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
  51 #define SDRC_POWER_CLKCTRL_SHIFT 4
  52 #define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
  53 #define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
  54
  55 /* Scratchpad offsets */
  56 #define OMAP343X_TABLE_ADDRESS_OFFSET      0x31
  57 #define OMAP343X_TABLE_VALUE_OFFSET        0x30
  58 #define OMAP343X_CONTROL_REG_VALUE_OFFSET  0x32
  59
  60 struct power_state {
  61         struct powerdomain *pwrdm;
  62         u32 next_state;
  63 #ifdef CONFIG_SUSPEND
  64         u32 saved_state;
  65 #endif
  66         struct list_head node;
  67 };
  68
  69 static LIST_HEAD(pwrst_list);
  70
  71 static void (*_omap_sram_idle)(u32 *addr, int save_state);
  72
  73 static int (*_omap_save_secure_sram)(u32 *addr);
  74
  75 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  76 static struct powerdomain *core_pwrdm, *per_pwrdm;
  77
  78 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
  79
  80 static inline void omap3_per_save_context(void)
  81 {
  82         omap_gpio_save_context();
  83 }
  84
  85 static inline void omap3_per_restore_context(void)
  86 {
  87         omap_gpio_restore_context();
  88 }
  89
  90 static void omap3_core_save_context(void)
  91 {
  92         u32 control_padconf_off;
  93
  94         /* Save the padconf registers */
  95         control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
  96         control_padconf_off |= START_PADCONF_SAVE;
  97         omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
  98         /* wait for the save to complete */
  99         while (!omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
 100                         & PADCONF_SAVE_DONE)
 101                 ;
 102         /* Save the Interrupt controller context */
 103         omap_intc_save_context();
 104         /* Save the GPMC context */
 105         omap3_gpmc_save_context();
 106         /* Save the system control module context, padconf already save above*/
 107         omap3_control_save_context();
 108         omap_dma_global_context_save();
 109 }
 110
 111 static void omap3_core_restore_context(void)
 112 {
 113         /* Restore the control module context, padconf restored by h/w */
 114         omap3_control_restore_context();
 115         /* Restore the GPMC context */
 116         omap3_gpmc_restore_context();
 117         /* Restore the interrupt controller context */
 118         omap_intc_restore_context();
 119         omap_dma_global_context_restore();
 120 }
 121
 122 /*
 123  * FIXME: This function should be called before entering off-mode after
 124  * OMAP3 secure services have been accessed. Currently it is only called
 125  * once during boot sequence, but this works as we are not using secure
 126  * services.
 127  */
 128 static void omap3_save_secure_ram_context(u32 target_mpu_state)
 129 {
 130         u32 ret;
 131
 132         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 133                 /*
 134                  * MPU next state must be set to POWER_ON temporarily,
 135                  * otherwise the WFI executed inside the ROM code
 136                  * will hang the system.
 137                  */
 138                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 139                 ret = _omap_save_secure_sram((u32 *)
 140                                 __pa(omap3_secure_ram_storage));
 141                 pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
 142                 /* Following is for error tracking, it should not happen */
 143                 if (ret) {
 144                         printk(KERN_ERR "save_secure_sram() returns %08x\n",
 145                                 ret);
 146                         while (1)
 147                                 ;
 148                 }
 149         }
 150 }
 151
 152 /*
 153  * PRCM Interrupt Handler Helper Function
 154  *
 155  * The purpose of this function is to clear any wake-up events latched
 156  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 157  * may occur whilst attempting to clear a PM_WKST_x register and thus
 158  * set another bit in this register. A while loop is used to ensure
 159  * that any peripheral wake-up events occurring while attempting to
 160  * clear the PM_WKST_x are detected and cleared.
 161  */
 162 static int prcm_clear_mod_irqs(s16 module, u8 regs)
 163 {
 164         u32 wkst, fclk, iclk, clken;
 165         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 166         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 167         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 168         u16 grpsel_off = (regs == 3) ?
 169                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 170         int c = 0;
 171
 172         wkst = prm_read_mod_reg(module, wkst_off);
 173         wkst &= prm_read_mod_reg(module, grpsel_off);
 174         if (wkst) {
 175                 iclk = cm_read_mod_reg(module, iclk_off);
 176                 fclk = cm_read_mod_reg(module, fclk_off);
 177                 while (wkst) {
 178                         clken = wkst;
 179                         cm_set_mod_reg_bits(clken, module, iclk_off);
 180                         /*
 181                          * For USBHOST, we don't know whether HOST1 or
 182                          * HOST2 woke us up, so enable both f-clocks
 183                          */
 184                         if (module == OMAP3430ES2_USBHOST_MOD)
 185                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 186                         cm_set_mod_reg_bits(clken, module, fclk_off);
 187                         prm_write_mod_reg(wkst, module, wkst_off);
 188                         wkst = prm_read_mod_reg(module, wkst_off);
 189                         c++;
 190                 }
 191                 cm_write_mod_reg(iclk, module, iclk_off);
 192                 cm_write_mod_reg(fclk, module, fclk_off);
 193         }
 194
 195         return c;
 196 }
 197
 198 static int _prcm_int_handle_wakeup(void)
 199 {
 200         int c;
 201
 202         c = prcm_clear_mod_irqs(WKUP_MOD, 1);
 203         c += prcm_clear_mod_irqs(CORE_MOD, 1);
 204         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
 205         if (omap_rev() > OMAP3430_REV_ES1_0) {
 206                 c += prcm_clear_mod_irqs(CORE_MOD, 3);
 207                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
 208         }
 209
 210         return c;
 211 }
 212
 213 /*
 214  * PRCM Interrupt Handler
 215  *
 216  * The PRM_IRQSTATUS_MPU register indicates if there are any pending
 217  * interrupts from the PRCM for the MPU. These bits must be cleared in
 218  * order to clear the PRCM interrupt. The PRCM interrupt handler is
 219  * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
 220  * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
 221  * register indicates that a wake-up event is pending for the MPU and
 222  * this bit can only be cleared if the all the wake-up events latched
 223  * in the various PM_WKST_x registers have been cleared. The interrupt
 224  * handler is implemented using a do-while loop so that if a wake-up
 225  * event occurred during the processing of the prcm interrupt handler
 226  * (setting a bit in the corresponding PM_WKST_x register and thus
 227  * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
 228  * this would be handled.
 229  */
 230 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 231 {
 232         u32 irqstatus_mpu;
 233         int c = 0;
 234
 235         do {
 236                 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
 237                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 238
 239                 if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) {
 240                         c = _prcm_int_handle_wakeup();
 241
 242                         /*
 243                          * Is the MPU PRCM interrupt handler racing with the
 244                          * IVA2 PRCM interrupt handler ?
 245                          */
 246                         WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
 247                              "but no wakeup sources are marked\n");
 248                 } else {
 249                         /* XXX we need to expand our PRCM interrupt handler */
 250                         WARN(1, "prcm: WARNING: PRCM interrupt received, but "
 251                              "no code to handle it (%08x)\n", irqstatus_mpu);
 252                 }
 253
 254                 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 255                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 256
 257         } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
 258
 259         return IRQ_HANDLED;
 260 }
 261
 262 static void restore_control_register(u32 val)
 263 {
 264         __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
 265 }
 266
 267 /* Function to restore the table entry that was modified for enabling MMU */
 268 static void restore_table_entry(void)
 269 {
 270         u32 *scratchpad_address;
 271         u32 previous_value, control_reg_value;
 272         u32 *address;
 273
 274         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
 275
 276         /* Get address of entry that was modified */
 277         address = (u32 *)__raw_readl(scratchpad_address +
 278                                      OMAP343X_TABLE_ADDRESS_OFFSET);
 279         /* Get the previous value which needs to be restored */
 280         previous_value = __raw_readl(scratchpad_address +
 281                                      OMAP343X_TABLE_VALUE_OFFSET);
 282         address = __va(address);
 283         *address = previous_value;
 284         flush_tlb_all();
 285         control_reg_value = __raw_readl(scratchpad_address
 286                                         + OMAP343X_CONTROL_REG_VALUE_OFFSET);
 287         /* This will enable caches and prediction */
 288         restore_control_register(control_reg_value);
 289 }
 290
 291 static void omap_sram_idle(void)
 292 {
 293         /* Variable to tell what needs to be saved and restored
 294          * in omap_sram_idle*/
 295         /* save_state = 0 => Nothing to save and restored */
 296         /* save_state = 1 => Only L1 and logic lost */
 297         /* save_state = 2 => Only L2 lost */
 298         /* save_state = 3 => L1, L2 and logic lost */
 299         int save_state = 0;
 300         int mpu_next_state = PWRDM_POWER_ON;
 301         int per_next_state = PWRDM_POWER_ON;
 302         int core_next_state = PWRDM_POWER_ON;
 303         int core_prev_state, per_prev_state;
 304         u32 sdrc_pwr = 0;
 305
 306         if (!_omap_sram_idle)
 307                 return;
 308
 309         pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
 310         pwrdm_clear_all_prev_pwrst(neon_pwrdm);
 311         pwrdm_clear_all_prev_pwrst(core_pwrdm);
 312         pwrdm_clear_all_prev_pwrst(per_pwrdm);
 313
 314         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 315         switch (mpu_next_state) {
 316         case PWRDM_POWER_ON:
 317         case PWRDM_POWER_RET:
 318                 /* No need to save context */
 319                 save_state = 0;
 320                 break;
 321         case PWRDM_POWER_OFF:
 322                 save_state = 3;
 323                 break;
 324         default:
 325                 /* Invalid state */
 326                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 327                 return;
 328         }
 329         pwrdm_pre_transition();
 330
 331         /* NEON control */
 332         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 333                 set_pwrdm_state(neon_pwrdm, mpu_next_state);
 334
 335         /* CORE & PER */
 336         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 337         if (core_next_state < PWRDM_POWER_ON) {
 338                 omap2_gpio_prepare_for_retention();
 339                 omap_uart_prepare_idle(0);
 340                 omap_uart_prepare_idle(1);
 341                 /* PER changes only with core */
 342                 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 343                 if (per_next_state < PWRDM_POWER_ON) {
 344                         omap_uart_prepare_idle(2);
 345                         if (per_next_state == PWRDM_POWER_OFF)
 346                                 omap3_per_save_context();
 347                 }
 348                 if (core_next_state == PWRDM_POWER_OFF) {
 349                         omap3_core_save_context();
 350                         omap3_prcm_save_context();
 351                 }
 352                 /* Enable IO-PAD wakeup */
 353                 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
 354         }
 355
 356         /*
 357          * Force SDRAM controller to self-refresh mode after timeout on
 358          * autocount. This is needed on ES3.0 to avoid SDRAM controller
 359          * hang-ups.
 360          */
 361         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 362             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 363             core_next_state == PWRDM_POWER_OFF) {
 364                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 365                 sdrc_write_reg((sdrc_pwr &
 366                         ~(SDRC_POWER_AUTOCOUNT_MASK|SDRC_POWER_CLKCTRL_MASK)) |
 367                         (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
 368                         SDRC_SELF_REFRESH_ON_AUTOCOUNT, SDRC_POWER);
 369         }
 370
 371         /*
 372          * omap3_arm_context is the location where ARM registers
 373          * get saved. The restore path then reads from this
 374          * location and restores them back.
 375          */
 376         _omap_sram_idle(omap3_arm_context, save_state);
 377         cpu_init();
 378
 379         /* Restore normal SDRAM settings */
 380         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 381             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 382             core_next_state == PWRDM_POWER_OFF)
 383                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 384
 385         /* Restore table entry modified during MMU restoration */
 386         if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
 387                 restore_table_entry();
 388
 389         if (core_next_state < PWRDM_POWER_ON) {
 390                 if (per_next_state < PWRDM_POWER_ON)
 391                         omap_uart_resume_idle(2);
 392                 omap_uart_resume_idle(1);
 393                 omap_uart_resume_idle(0);
 394
 395                 /* Disable IO-PAD wakeup */
 396                 prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
 397                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 398                 if (core_prev_state == PWRDM_POWER_OFF) {
 399                         omap3_core_restore_context();
 400                         omap3_prcm_restore_context();
 401                         omap3_sram_restore_context();
 402                 }
 403                 if (per_next_state < PWRDM_POWER_ON) {
 404                         per_prev_state =
 405                                 pwrdm_read_prev_pwrst(per_pwrdm);
 406                         if (per_prev_state == PWRDM_POWER_OFF)
 407                                 omap3_per_restore_context();
 408                 }
 409                 omap2_gpio_resume_after_retention();
 410         }
 411
 412         pwrdm_post_transition();
 413
 414 }
 415
 416 /*
 417  * Check if functional clocks are enabled before entering
 418  * sleep. This function could be behind CONFIG_PM_DEBUG
 419  * when all drivers are configuring their sysconfig registers
 420  * properly and using their clocks properly.
 421  */
 422 static int omap3_fclks_active(void)
 423 {
 424         u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
 425                 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
 426
 427         fck_core1 = cm_read_mod_reg(CORE_MOD,
 428                                     CM_FCLKEN1);
 429         if (omap_rev() > OMAP3430_REV_ES1_0) {
 430                 fck_core3 = cm_read_mod_reg(CORE_MOD,
 431                                             OMAP3430ES2_CM_FCLKEN3);
 432                 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
 433                                           CM_FCLKEN);
 434                 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 435                                               CM_FCLKEN);
 436         } else
 437                 fck_sgx = cm_read_mod_reg(GFX_MOD,
 438                                           OMAP3430ES2_CM_FCLKEN3);
 439         fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
 440                                   CM_FCLKEN);
 441         fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
 442                                   CM_FCLKEN);
 443         fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
 444                                   CM_FCLKEN);
 445
 446         /* Ignore UART clocks.  These are handled by UART core (serial.c) */
 447         fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
 448         fck_per &= ~OMAP3430_EN_UART3;
 449
 450         if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
 451             fck_cam | fck_per | fck_usbhost)
 452                 return 1;
 453         return 0;
 454 }
 455
 456 static int omap3_can_sleep(void)
 457 {
 458         if (!omap_uart_can_sleep())
 459                 return 0;
 460         if (omap3_fclks_active())
 461                 return 0;
 462         return 1;
 463 }
 464
 465 /* This sets pwrdm state (other than mpu & core. Currently only ON &
 466  * RET are supported. Function is assuming that clkdm doesn't have
 467  * hw_sup mode enabled. */
 468 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 469 {
 470         u32 cur_state;
 471         int sleep_switch = 0;
 472         int ret = 0;
 473
 474         if (pwrdm == NULL || IS_ERR(pwrdm))
 475                 return -EINVAL;
 476
 477         while (!(pwrdm->pwrsts & (1 << state))) {
 478                 if (state == PWRDM_POWER_OFF)
 479                         return ret;
 480                 state--;
 481         }
 482
 483         cur_state = pwrdm_read_next_pwrst(pwrdm);
 484         if (cur_state == state)
 485                 return ret;
 486
 487         if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
 488                 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
 489                 sleep_switch = 1;
 490                 pwrdm_wait_transition(pwrdm);
 491         }
 492
 493         ret = pwrdm_set_next_pwrst(pwrdm, state);
 494         if (ret) {
 495                 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
 496                        pwrdm->name);
 497                 goto err;
 498         }
 499
 500         if (sleep_switch) {
 501                 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
 502                 pwrdm_wait_transition(pwrdm);
 503                 pwrdm_state_switch(pwrdm);
 504         }
 505
 506 err:
 507         return ret;
 508 }
 509
 510 static void omap3_pm_idle(void)
 511 {
 512         local_irq_disable();
 513         local_fiq_disable();
 514
 515         if (!omap3_can_sleep())
 516                 goto out;
 517
 518         if (omap_irq_pending())
 519                 goto out;
 520
 521         omap_sram_idle();
 522
 523 out:
 524         local_fiq_enable();
 525         local_irq_enable();
 526 }
 527
 528 #ifdef CONFIG_SUSPEND
 529 static suspend_state_t suspend_state;
 530
 531 static int omap3_pm_prepare(void)
 532 {
 533         disable_hlt();
 534         return 0;
 535 }
 536
 537 static int omap3_pm_suspend(void)
 538 {
 539         struct power_state *pwrst;
 540         int state, ret = 0;
 541
 542         /* Read current next_pwrsts */
 543         list_for_each_entry(pwrst, &pwrst_list, node)
 544                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 545         /* Set ones wanted by suspend */
 546         list_for_each_entry(pwrst, &pwrst_list, node) {
 547                 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 548                         goto restore;
 549                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 550                         goto restore;
 551         }
 552
 553         omap_uart_prepare_suspend();
 554         omap_sram_idle();
 555
 556 restore:
 557         /* Restore next_pwrsts */
 558         list_for_each_entry(pwrst, &pwrst_list, node) {
 559                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 560                 if (state > pwrst->next_state) {
 561                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 562                                "target state %d\n",
 563                                pwrst->pwrdm->name, pwrst->next_state);
 564                         ret = -1;
 565                 }
 566                 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 567         }
 568         if (ret)
 569                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 570         else
 571                 printk(KERN_INFO "Successfully put all powerdomains "
 572                        "to target state\n");
 573
 574         return ret;
 575 }
 576
 577 static int omap3_pm_enter(suspend_state_t unused)
 578 {
 579         int ret = 0;
 580
 581         switch (suspend_state) {
 582         case PM_SUSPEND_STANDBY:
 583         case PM_SUSPEND_MEM:
 584                 ret = omap3_pm_suspend();
 585                 break;
 586         default:
 587                 ret = -EINVAL;
 588         }
 589
 590         return ret;
 591 }
 592
 593 static void omap3_pm_finish(void)
 594 {
 595         enable_hlt();
 596 }
 597
 598 /* Hooks to enable / disable UART interrupts during suspend */
 599 static int omap3_pm_begin(suspend_state_t state)
 600 {
 601         suspend_state = state;
 602         omap_uart_enable_irqs(0);
 603         return 0;
 604 }
 605
 606 static void omap3_pm_end(void)
 607 {
 608         suspend_state = PM_SUSPEND_ON;
 609         omap_uart_enable_irqs(1);
 610         return;
 611 }
 612
 613 static struct platform_suspend_ops omap_pm_ops = {
 614         .begin          = omap3_pm_begin,
 615         .end            = omap3_pm_end,
 616         .prepare        = omap3_pm_prepare,
 617         .enter          = omap3_pm_enter,
 618         .finish         = omap3_pm_finish,
 619         .valid          = suspend_valid_only_mem,
 620 };
 621 #endif /* CONFIG_SUSPEND */
 622
 623
 624 /**
 625  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 626  *                   retention
 627  *
 628  * In cases where IVA2 is activated by bootcode, it may prevent
 629  * full-chip retention or off-mode because it is not idle.  This
 630  * function forces the IVA2 into idle state so it can go
 631  * into retention/off and thus allow full-chip retention/off.
 632  *
 633  **/
 634 static void __init omap3_iva_idle(void)
 635 {
 636         /* ensure IVA2 clock is disabled */
 637         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 638
 639         /* if no clock activity, nothing else to do */
 640         if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 641               OMAP3430_CLKACTIVITY_IVA2_MASK))
 642                 return;
 643
 644         /* Reset IVA2 */
 645         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
 646                           OMAP3430_RST2_IVA2 |
 647                           OMAP3430_RST3_IVA2,
 648                           OMAP3430_IVA2_MOD, RM_RSTCTRL);
 649
 650         /* Enable IVA2 clock */
 651         cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
 652                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 653
 654         /* Set IVA2 boot mode to 'idle' */
 655         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 656                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 657
 658         /* Un-reset IVA2 */
 659         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
 660
 661         /* Disable IVA2 clock */
 662         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 663
 664         /* Reset IVA2 */
 665         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
 666                           OMAP3430_RST2_IVA2 |
 667                           OMAP3430_RST3_IVA2,
 668                           OMAP3430_IVA2_MOD, RM_RSTCTRL);
 669 }
 670
 671 static void __init omap3_d2d_idle(void)
 672 {
 673         u16 mask, padconf;
 674
 675         /* In a stand alone OMAP3430 where there is not a stacked
 676          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 677          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 678          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 679         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 680         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 681         padconf |= mask;
 682         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 683
 684         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 685         padconf |= mask;
 686         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 687
 688         /* reset modem */
 689         prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
 690                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
 691                           CORE_MOD, RM_RSTCTRL);
 692         prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
 693 }
 694
 695 static void __init prcm_setup_regs(void)
 696 {
 697         /* XXX Reset all wkdeps. This should be done when initializing
 698          * powerdomains */
 699         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
 700         prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
 701         prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
 702         prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
 703         prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
 704         prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
 705         if (omap_rev() > OMAP3430_REV_ES1_0) {
 706                 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
 707                 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 708         } else
 709                 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 710
 711         /*
 712          * Enable interface clock autoidle for all modules.
 713          * Note that in the long run this should be done by clockfw
 714          */
 715         cm_write_mod_reg(
 716                 OMAP3430_AUTO_MODEM |
 717                 OMAP3430ES2_AUTO_MMC3 |
 718                 OMAP3430ES2_AUTO_ICR |
 719                 OMAP3430_AUTO_AES2 |
 720                 OMAP3430_AUTO_SHA12 |
 721                 OMAP3430_AUTO_DES2 |
 722                 OMAP3430_AUTO_MMC2 |
 723                 OMAP3430_AUTO_MMC1 |
 724                 OMAP3430_AUTO_MSPRO |
 725                 OMAP3430_AUTO_HDQ |
 726                 OMAP3430_AUTO_MCSPI4 |
 727                 OMAP3430_AUTO_MCSPI3 |
 728                 OMAP3430_AUTO_MCSPI2 |
 729                 OMAP3430_AUTO_MCSPI1 |
 730                 OMAP3430_AUTO_I2C3 |
 731                 OMAP3430_AUTO_I2C2 |
 732                 OMAP3430_AUTO_I2C1 |
 733                 OMAP3430_AUTO_UART2 |
 734                 OMAP3430_AUTO_UART1 |
 735                 OMAP3430_AUTO_GPT11 |
 736                 OMAP3430_AUTO_GPT10 |
 737                 OMAP3430_AUTO_MCBSP5 |
 738                 OMAP3430_AUTO_MCBSP1 |
 739                 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
 740                 OMAP3430_AUTO_MAILBOXES |
 741                 OMAP3430_AUTO_OMAPCTRL |
 742                 OMAP3430ES1_AUTO_FSHOSTUSB |
 743                 OMAP3430_AUTO_HSOTGUSB |
 744                 OMAP3430_AUTO_SAD2D |
 745                 OMAP3430_AUTO_SSI,
 746                 CORE_MOD, CM_AUTOIDLE1);
 747
 748         cm_write_mod_reg(
 749                 OMAP3430_AUTO_PKA |
 750                 OMAP3430_AUTO_AES1 |
 751                 OMAP3430_AUTO_RNG |
 752                 OMAP3430_AUTO_SHA11 |
 753                 OMAP3430_AUTO_DES1,
 754                 CORE_MOD, CM_AUTOIDLE2);
 755
 756         if (omap_rev() > OMAP3430_REV_ES1_0) {
 757                 cm_write_mod_reg(
 758                         OMAP3430_AUTO_MAD2D |
 759                         OMAP3430ES2_AUTO_USBTLL,
 760                         CORE_MOD, CM_AUTOIDLE3);
 761         }
 762
 763         cm_write_mod_reg(
 764                 OMAP3430_AUTO_WDT2 |
 765                 OMAP3430_AUTO_WDT1 |
 766                 OMAP3430_AUTO_GPIO1 |
 767                 OMAP3430_AUTO_32KSYNC |
 768                 OMAP3430_AUTO_GPT12 |
 769                 OMAP3430_AUTO_GPT1 ,
 770                 WKUP_MOD, CM_AUTOIDLE);
 771
 772         cm_write_mod_reg(
 773                 OMAP3430_AUTO_DSS,
 774                 OMAP3430_DSS_MOD,
 775                 CM_AUTOIDLE);
 776
 777         cm_write_mod_reg(
 778                 OMAP3430_AUTO_CAM,
 779                 OMAP3430_CAM_MOD,
 780                 CM_AUTOIDLE);
 781
 782         cm_write_mod_reg(
 783                 OMAP3430_AUTO_GPIO6 |
 784                 OMAP3430_AUTO_GPIO5 |
 785                 OMAP3430_AUTO_GPIO4 |
 786                 OMAP3430_AUTO_GPIO3 |
 787                 OMAP3430_AUTO_GPIO2 |
 788                 OMAP3430_AUTO_WDT3 |
 789                 OMAP3430_AUTO_UART3 |
 790                 OMAP3430_AUTO_GPT9 |
 791                 OMAP3430_AUTO_GPT8 |
 792                 OMAP3430_AUTO_GPT7 |
 793                 OMAP3430_AUTO_GPT6 |
 794                 OMAP3430_AUTO_GPT5 |
 795                 OMAP3430_AUTO_GPT4 |
 796                 OMAP3430_AUTO_GPT3 |
 797                 OMAP3430_AUTO_GPT2 |
 798                 OMAP3430_AUTO_MCBSP4 |
 799                 OMAP3430_AUTO_MCBSP3 |
 800                 OMAP3430_AUTO_MCBSP2,
 801                 OMAP3430_PER_MOD,
 802                 CM_AUTOIDLE);
 803
 804         if (omap_rev() > OMAP3430_REV_ES1_0) {
 805                 cm_write_mod_reg(
 806                         OMAP3430ES2_AUTO_USBHOST,
 807                         OMAP3430ES2_USBHOST_MOD,
 808                         CM_AUTOIDLE);
 809         }
 810
 811         /*
 812          * Set all plls to autoidle. This is needed until autoidle is
 813          * enabled by clockfw
 814          */
 815         cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
 816                          OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
 817         cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
 818                          MPU_MOD,
 819                          CM_AUTOIDLE2);
 820         cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
 821                          (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
 822                          PLL_MOD,
 823                          CM_AUTOIDLE);
 824         cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
 825                          PLL_MOD,
 826                          CM_AUTOIDLE2);
 827
 828         /*
 829          * Enable control of expternal oscillator through
 830          * sys_clkreq. In the long run clock framework should
 831          * take care of this.
 832          */
 833         prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 834                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 835                              OMAP3430_GR_MOD,
 836                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 837
 838         /* setup wakup source */
 839         prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
 840                           OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
 841                           WKUP_MOD, PM_WKEN);
 842         /* No need to write EN_IO, that is always enabled */
 843         prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
 844                           OMAP3430_EN_GPT12,
 845                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 846         /* For some reason IO doesn't generate wakeup event even if
 847          * it is selected to mpu wakeup goup */
 848         prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
 849                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 850
 851         /* Enable wakeups in PER */
 852         prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
 853                           OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
 854                           OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3,
 855                           OMAP3430_PER_MOD, PM_WKEN);
 856         /* and allow them to wake up MPU */
 857         prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
 858                           OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
 859                           OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3,
 860                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 861
 862         /* Don't attach IVA interrupts */
 863         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 864         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 865         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 866         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 867
 868         /* Clear any pending 'reset' flags */
 869         prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
 870         prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
 871         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
 872         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
 873         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
 874         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
 875         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
 876
 877         /* Clear any pending PRCM interrupts */
 878         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 879
 880         /* Don't attach IVA interrupts */
 881         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 882         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 883         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 884         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 885
 886         /* Clear any pending 'reset' flags */
 887         prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
 888         prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
 889         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
 890         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
 891         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
 892         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
 893         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
 894
 895         /* Clear any pending PRCM interrupts */
 896         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 897
 898         omap3_iva_idle();
 899         omap3_d2d_idle();
 900 }
 901
 902 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 903 {
 904         struct power_state *pwrst;
 905
 906         list_for_each_entry(pwrst, &pwrst_list, node) {
 907                 if (pwrst->pwrdm == pwrdm)
 908                         return pwrst->next_state;
 909         }
 910         return -EINVAL;
 911 }
 912
 913 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 914 {
 915         struct power_state *pwrst;
 916
 917         list_for_each_entry(pwrst, &pwrst_list, node) {
 918                 if (pwrst->pwrdm == pwrdm) {
 919                         pwrst->next_state = state;
 920                         return 0;
 921                 }
 922         }
 923         return -EINVAL;
 924 }
 925
 926 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 927 {
 928         struct power_state *pwrst;
 929
 930         if (!pwrdm->pwrsts)
 931                 return 0;
 932
 933         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 934         if (!pwrst)
 935                 return -ENOMEM;
 936         pwrst->pwrdm = pwrdm;
 937         pwrst->next_state = PWRDM_POWER_RET;
 938         list_add(&pwrst->node, &pwrst_list);
 939
 940         if (pwrdm_has_hdwr_sar(pwrdm))
 941                 pwrdm_enable_hdwr_sar(pwrdm);
 942
 943         return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 944 }
 945
 946 /*
 947  * Enable hw supervised mode for all clockdomains if it's
 948  * supported. Initiate sleep transition for other clockdomains, if
 949  * they are not used
 950  */
 951 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 952 {
 953         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 954                 omap2_clkdm_allow_idle(clkdm);
 955         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 956                  atomic_read(&clkdm->usecount) == 0)
 957                 omap2_clkdm_sleep(clkdm);
 958         return 0;
 959 }
 960
 961 void omap_push_sram_idle(void)
 962 {
 963         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
 964                                         omap34xx_cpu_suspend_sz);
 965         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
 966                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
 967                                 save_secure_ram_context_sz);
 968 }
 969
 970 static int __init omap3_pm_init(void)
 971 {
 972         struct power_state *pwrst, *tmp;
 973         int ret;
 974
 975         if (!cpu_is_omap34xx())
 976                 return -ENODEV;
 977
 978         printk(KERN_ERR "Power Management for TI OMAP3.\n");
 979
 980         /* XXX prcm_setup_regs needs to be before enabling hw
 981          * supervised mode for powerdomains */
 982         prcm_setup_regs();
 983
 984         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
 985                           (irq_handler_t)prcm_interrupt_handler,
 986                           IRQF_DISABLED, "prcm", NULL);
 987         if (ret) {
 988                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
 989                        INT_34XX_PRCM_MPU_IRQ);
 990                 goto err1;
 991         }
 992
 993         ret = pwrdm_for_each(pwrdms_setup, NULL);
 994         if (ret) {
 995                 printk(KERN_ERR "Failed to setup powerdomains\n");
 996                 goto err2;
 997         }
 998
 999         (void) clkdm_for_each(clkdms_setup, NULL);
1000
1001         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
1002         if (mpu_pwrdm == NULL) {
1003                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
1004                 goto err2;
1005         }
1006
1007         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
1008         per_pwrdm = pwrdm_lookup("per_pwrdm");
1009         core_pwrdm = pwrdm_lookup("core_pwrdm");
1010
1011         omap_push_sram_idle();
1012 #ifdef CONFIG_SUSPEND
1013         suspend_set_ops(&omap_pm_ops);
1014 #endif /* CONFIG_SUSPEND */
1015
1016         pm_idle = omap3_pm_idle;
1017
1018         pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm);
1019         /*
1020          * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
1021          * IO-pad wakeup.  Otherwise it will unnecessarily waste power
1022          * waking up PER with every CORE wakeup - see
1023          * http://marc.info/?l=linux-omap&m=121852150710062&w=2
1024         */
1025         pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
1026
1027         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
1028                 omap3_secure_ram_storage =
1029                         kmalloc(0x803F, GFP_KERNEL);
1030                 if (!omap3_secure_ram_storage)
1031                         printk(KERN_ERR "Memory allocation failed when"
1032                                         "allocating for secure sram context\n");
1033
1034                 local_irq_disable();
1035                 local_fiq_disable();
1036
1037                 omap_dma_global_context_save();
1038                 omap3_save_secure_ram_context(PWRDM_POWER_ON);
1039                 omap_dma_global_context_restore();
1040
1041                 local_irq_enable();
1042                 local_fiq_enable();
1043         }
1044
1045         omap3_save_scratchpad_contents();
1046 err1:
1047         return ret;
1048 err2:
1049         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
1050         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
1051                 list_del(&pwrst->node);
1052                 kfree(pwrst);
1053         }
1054         return ret;
1055 }
1056
1057 late_initcall(omap3_pm_init);