2 * OMAP4 SMP source file. It contains platform specific fucntions
3 * needed for the linux smp kernel.
5 * Copyright (C) 2009 Texas Instruments, Inc.
8 * Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * Platform file needed for the OMAP4 SMP. This file is based on arm
11 * realview smp platform.
12 * * Copyright (c) 2002 ARM Limited.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/device.h>
20 #include <linux/jiffies.h>
21 #include <linux/smp.h>
24 #include <asm/cacheflush.h>
25 #include <asm/localtimer.h>
26 #include <asm/smp_scu.h>
27 #include <mach/hardware.h>
28 #include <plat/common.h>
30 /* SCU base address */
31 static void __iomem *scu_base;
34 * Use SCU config register to count number of cores
36 static inline unsigned int get_core_count(void)
39 return scu_get_core_count(scu_base);
43 static DEFINE_SPINLOCK(boot_lock);
45 void __cpuinit platform_secondary_init(unsigned int cpu)
50 * If any interrupts are already enabled for the primary
51 * core (e.g. timer irq), then they will not have been enabled
54 gic_cpu_init(0, gic_cpu_base_addr);
57 * Synchronise with the boot thread.
59 spin_lock(&boot_lock);
60 spin_unlock(&boot_lock);
63 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
65 unsigned long timeout;
68 * Set synchronisation state between this boot processor
69 * and the secondary one
71 spin_lock(&boot_lock);
74 * Update the AuxCoreBoot0 with boot state for secondary core.
75 * omap_secondary_startup() routine will hold the secondary core till
76 * the AuxCoreBoot1 register is updated with cpu state
77 * A barrier is added to ensure that write buffer is drained
79 omap_modify_auxcoreboot0(0x200, 0x0);
83 timeout = jiffies + (1 * HZ);
84 while (time_before(jiffies, timeout))
88 * Now the secondary core is starting up let it run its
89 * calibrations, then wait for it to finish
91 spin_unlock(&boot_lock);
96 static void __init wakeup_secondary(void)
99 * Write the address of secondary startup routine into the
100 * AuxCoreBoot1 where ROM code will jump and start executing
101 * on secondary core once out of WFE
102 * A barrier is added to ensure that write buffer is drained
104 omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
108 * Send a 'sev' to wake the secondary core from WFE.
109 * Drain the outstanding writes to memory
117 * Initialise the CPU possible map early - this describes the CPUs
118 * which may be present or become present in the system.
120 void __init smp_init_cpus(void)
122 unsigned int i, ncores;
125 scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
128 ncores = get_core_count();
130 for (i = 0; i < ncores; i++)
131 set_cpu_possible(i, true);
134 void __init smp_prepare_cpus(unsigned int max_cpus)
136 unsigned int ncores = get_core_count();
137 unsigned int cpu = smp_processor_id();
143 "OMAP4: strange core count of 0? Default to 1\n");
147 if (ncores > NR_CPUS) {
149 "OMAP4: no. of cores (%d) greater than configured "
150 "maximum of %d - clipping\n",
154 smp_store_cpu_info(cpu);
157 * are we trying to boot more cores than exist?
159 if (max_cpus > ncores)
163 * Initialise the present map, which describes the set of CPUs
164 * actually populated at the present time.
166 for (i = 0; i < max_cpus; i++)
167 set_cpu_present(i, true);
171 * Enable the local timer or broadcast device for the
172 * boot CPU, but only if we have more than one CPU.
174 percpu_timer_setup();
177 * Initialise the SCU and wake up the secondary core using
178 * wakeup_secondary().
180 scu_enable(scu_base);