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   1 /*
   2  * arch/arm/plat-omap/include/mach/entry-macro.S
   3  *
   4  * Low-level IRQ helper macros for OMAP-based platforms
   5  *
   6  * Copyright (C) 2009 Texas Instruments
   7  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
   8  *
   9  * This file is licensed under  the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13 #include <mach/hardware.h>
  14 #include <mach/io.h>
  15 #include <mach/irqs.h>
  16 #include <asm/hardware/gic.h>
  17
  18 #include <plat/omap24xx.h>
  19 #include <plat/omap34xx.h>
  20 #include <plat/omap44xx.h>
  21
  22 #include <plat/multi.h>
  23
  24 #define OMAP2_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
  25 #define OMAP3_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
  26 #define OMAP4_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
  27 #define INTCPS_SIR_IRQ_OFFSET   0x0040  /* omap2/3 active interrupt offset */
  28 #define ACTIVEIRQ_MASK          0x7f    /* omap2/3 active interrupt bits */
  29
  30                 .macro  disable_fiq
  31                 .endm
  32
  33                 .macro  arch_ret_to_user, tmp1, tmp2
  34                 .endm
  35
  36 /*
  37  * Unoptimized irq functions for multi-omap2, 3 and 4
  38  */
  39
  40 #ifdef MULTI_OMAP2
  41                 .pushsection .data
  42 omap_irq_base:  .word   0
  43                 .popsection
  44
  45                 /* Configure the interrupt base on the first interrupt */
  46                 .macro  get_irqnr_preamble, base, tmp
  47 9:
  48                 ldr     \base, =omap_irq_base   @ irq base address
  49                 ldr     \base, [\base, #0]      @ irq base value
  50                 cmp     \base, #0               @ already configured?
  51                 bne     9998f                   @ nothing to do
  52
  53                 mrc     p15, 0, \tmp, c0, c0, 0 @ get processor revision
  54                 and     \tmp, \tmp, #0x000f0000 @ only check architecture
  55                 cmp     \tmp, #0x00060000       @ is v6?
  56                 beq     2400f                   @ found v6 so it's omap24xx
  57                 cmp     \tmp, #0x000f0000       @ is cortex?
  58                 beq     3400f                   @ found v7 so it's omap34xx
  59 2400:           ldr     \base, =OMAP2_IRQ_BASE
  60                 ldr     \tmp, =omap_irq_base
  61                 str     \base, [\tmp, #0]
  62                 b       9b
  63 3400:           ldr     \base, =OMAP3_IRQ_BASE
  64                 ldr     \tmp, =omap_irq_base
  65                 str     \base, [\tmp, #0]
  66                 b       9b
  67 9998:
  68                 .endm
  69
  70                 /* Check the pending interrupts. Note that base already set */
  71                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
  72                 ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
  73                 cmp     \irqnr, #0x0
  74                 bne     9999f
  75                 ldr     \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
  76                 cmp     \irqnr, #0x0
  77                 bne     9999f
  78                 ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
  79                 cmp     \irqnr, #0x0
  80 9999:
  81                 ldrne   \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
  82                 and     \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
  83
  84                 .endm
  85
  86
  87 #else   /* MULTI_OMAP2 */
  88
  89
  90 /*
  91  * Optimized irq functions for omap2, 3 and 4
  92  */
  93
  94 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  95                 .macro  get_irqnr_preamble, base, tmp
  96 #ifdef CONFIG_ARCH_OMAP2
  97                 ldr     \base, =OMAP2_IRQ_BASE
  98 #else
  99                 ldr     \base, =OMAP3_IRQ_BASE
 100 #endif
 101                 .endm
 102
 103                 /* Check the pending interrupts. Note that base already set */
 104                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 105                 ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
 106                 cmp     \irqnr, #0x0
 107                 bne     9999f
 108                 ldr     \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
 109                 cmp     \irqnr, #0x0
 110                 bne     9999f
 111                 ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
 112                 cmp     \irqnr, #0x0
 113 9999:
 114                 ldrne   \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
 115                 and     \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
 116
 117                 .endm
 118 #endif
 119
 120
 121 #ifdef CONFIG_ARCH_OMAP4
 122
 123                 .macro  get_irqnr_preamble, base, tmp
 124                 ldr     \base, =OMAP4_IRQ_BASE
 125                 .endm
 126
 127                 /*
 128                  * The interrupt numbering scheme is defined in the
 129                  * interrupt controller spec.  To wit:
 130                  *
 131                  * Interrupts 0-15 are IPI
 132                  * 16-28 are reserved
 133                  * 29-31 are local.  We allow 30 to be used for the watchdog.
 134                  * 32-1020 are global
 135                  * 1021-1022 are reserved
 136                  * 1023 is "spurious" (no interrupt)
 137                  *
 138                  * For now, we ignore all local interrupts so only return an
 139                  * interrupt if it's between 30 and 1020.  The test_for_ipi
 140                  * routine below will pick up on IPIs.
 141                  * A simple read from the controller will tell us the number
 142                  * of the highest priority enabled interrupt.
 143                  * We then just need to check whether it is in the
 144                  * valid range for an IRQ (30-1020 inclusive).
 145                  */
 146                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 147                 ldr     \irqstat, [\base, #GIC_CPU_INTACK]
 148
 149                 ldr     \tmp, =1021
 150
 151                 bic     \irqnr, \irqstat, #0x1c00
 152
 153                 cmp     \irqnr, #29
 154                 cmpcc   \irqnr, \irqnr
 155                 cmpne   \irqnr, \tmp
 156                 cmpcs   \irqnr, \irqnr
 157                 .endm
 158
 159                 /* We assume that irqstat (the raw value of the IRQ acknowledge
 160                  * register) is preserved from the macro above.
 161                  * If there is an IPI, we immediately signal end of interrupt
 162                  * on the controller, since this requires the original irqstat
 163                  * value which we won't easily be able to recreate later.
 164                  */
 165
 166                 .macro test_for_ipi, irqnr, irqstat, base, tmp
 167                 bic     \irqnr, \irqstat, #0x1c00
 168                 cmp     \irqnr, #16
 169                 it      cc
 170                 strcc   \irqstat, [\base, #GIC_CPU_EOI]
 171                 it      cs
 172                 cmpcs   \irqnr, \irqnr
 173                 .endm
 174
 175                 /* As above, this assumes that irqstat and base are preserved */
 176
 177                 .macro test_for_ltirq, irqnr, irqstat, base, tmp
 178                 bic     \irqnr, \irqstat, #0x1c00
 179                 mov     \tmp, #0
 180                 cmp     \irqnr, #29
 181                 itt     eq
 182                 moveq   \tmp, #1
 183                 streq   \irqstat, [\base, #GIC_CPU_EOI]
 184                 cmp     \tmp, #0
 185                 .endm
 186 #endif
 187 #endif  /* MULTI_OMAP2 */
 188
 189                 .macro  irq_prio_table
 190                 .endm