2 * OMAP3-specific clock framework functions
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h>
22 #include <linux/list.h>
23 #include <linux/errno.h>
24 #include <linux/delay.h>
25 #include <linux/clk.h>
27 #include <linux/limits.h>
28 #include <linux/bitops.h>
30 #include <mach/clock.h>
31 #include <mach/sram.h>
32 #include <asm/div64.h>
33 #include <asm/clkdev.h>
35 #include <mach/sdrc.h>
38 #include "prm-regbits-34xx.h"
40 #include "cm-regbits-34xx.h"
42 static const struct clkops clkops_noncore_dpll_ops;
44 #include "clock34xx.h"
51 #define CLK(dev, con, ck, cp) \
61 #define CK_343X (1 << 0)
62 #define CK_3430ES1 (1 << 1)
63 #define CK_3430ES2 (1 << 2)
65 static struct omap_clk omap34xx_clks[] = {
66 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X),
67 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X),
68 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X),
69 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
70 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
71 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X),
72 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
73 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X),
74 CLK(NULL, "sys_ck", &sys_ck, CK_343X),
75 CLK(NULL, "sys_altclk", &sys_altclk, CK_343X),
76 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X),
77 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X),
78 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X),
79 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X),
80 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
81 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
82 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
83 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X),
84 CLK(NULL, "core_ck", &core_ck, CK_343X),
85 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X),
86 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X),
87 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
88 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X),
89 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
90 CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
91 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X),
92 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X),
93 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
94 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X),
95 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X),
96 CLK(NULL, "virt_omap_54m_fck", &virt_omap_54m_fck, CK_343X),
97 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X),
98 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X),
99 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X),
100 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X),
101 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
102 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X),
103 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
104 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X),
105 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
106 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X),
107 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
108 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X),
109 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
110 CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
111 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2),
112 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2),
113 CLK(NULL, "omap_120m_fck", &omap_120m_fck, CK_3430ES2),
114 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X),
115 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X),
116 CLK(NULL, "corex2_fck", &corex2_fck, CK_343X),
117 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X),
118 CLK(NULL, "mpu_ck", &mpu_ck, CK_343X),
119 CLK(NULL, "arm_fck", &arm_fck, CK_343X),
120 CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
121 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
122 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
123 CLK(NULL, "l3_ick", &l3_ick, CK_343X),
124 CLK(NULL, "l4_ick", &l4_ick, CK_343X),
125 CLK(NULL, "rm_ick", &rm_ick, CK_343X),
126 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
127 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
128 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
129 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
130 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
131 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2),
132 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2),
133 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
134 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X),
135 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X),
136 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2),
137 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2),
138 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2),
139 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X),
140 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2),
141 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X),
142 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
143 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X),
144 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X),
145 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X),
146 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X),
147 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X),
148 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X),
149 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X),
150 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X),
151 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X),
152 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X),
153 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X),
154 CLK(NULL, "uart2_fck", &uart2_fck, CK_343X),
155 CLK(NULL, "uart1_fck", &uart1_fck, CK_343X),
156 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
157 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
158 CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X),
159 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X),
160 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X),
161 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
162 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick, CK_343X),
163 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
164 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
165 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
166 CLK(NULL, "pka_ick", &pka_ick, CK_343X),
167 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X),
168 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2),
169 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2),
170 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
171 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
172 CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
173 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
174 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X),
175 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X),
176 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
177 CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X),
178 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X),
179 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X),
180 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X),
181 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X),
182 CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X),
183 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X),
184 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X),
185 CLK(NULL, "uart2_ick", &uart2_ick, CK_343X),
186 CLK(NULL, "uart1_ick", &uart1_ick, CK_343X),
187 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X),
188 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X),
189 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X),
190 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X),
191 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
192 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
193 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
194 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
195 CLK(NULL, "ssi_ick", &ssi_ick, CK_343X),
196 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
197 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
198 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
199 CLK("omap_rng", "ick", &rng_ick, CK_343X),
200 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
201 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
202 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck, CK_343X),
203 CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_343X),
204 CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_343X),
205 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_343X),
206 CLK(NULL, "dss_ick", &dss_ick, CK_343X),
207 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
208 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
209 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
210 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
211 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
212 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2),
213 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
214 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X),
215 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X),
216 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X),
217 CLK("omap_wdt", "fck", &wdt2_fck, CK_343X),
218 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
219 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
220 CLK("omap_wdt", "ick", &wdt2_ick, CK_343X),
221 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X),
222 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X),
223 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
224 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X),
225 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X),
226 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X),
227 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X),
228 CLK(NULL, "uart3_fck", &uart3_fck, CK_343X),
229 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X),
230 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X),
231 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X),
232 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X),
233 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X),
234 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X),
235 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X),
236 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X),
237 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
238 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X),
239 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X),
240 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X),
241 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X),
242 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X),
243 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X),
244 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X),
245 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X),
246 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X),
247 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X),
248 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X),
249 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X),
250 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X),
251 CLK(NULL, "uart3_ick", &uart3_ick, CK_343X),
252 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X),
253 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X),
254 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X),
255 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X),
256 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X),
257 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X),
258 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X),
259 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X),
260 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X),
261 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X),
262 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X),
263 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X),
264 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X),
265 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X),
266 CLK(NULL, "emu_src_ck", &emu_src_ck, CK_343X),
267 CLK(NULL, "pclk_fck", &pclk_fck, CK_343X),
268 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X),
269 CLK(NULL, "atclk_fck", &atclk_fck, CK_343X),
270 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X),
271 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X),
272 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
273 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
274 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
275 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X),
276 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X),
277 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X),
280 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
281 #define DPLL_AUTOIDLE_DISABLE 0x0
282 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
284 #define MAX_DPLL_WAIT_TRIES 1000000
287 * omap3_dpll_recalc - recalculate DPLL rate
288 * @clk: DPLL struct clk
290 * Recalculate and propagate the DPLL rate.
292 static void omap3_dpll_recalc(struct clk *clk)
294 clk->rate = omap2_get_dpll_rate(clk);
297 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
298 static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
300 const struct dpll_data *dd;
305 v = __raw_readl(dd->control_reg);
306 v &= ~dd->enable_mask;
307 v |= clken_bits << __ffs(dd->enable_mask);
308 __raw_writel(v, dd->control_reg);
311 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
312 static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
314 const struct dpll_data *dd;
320 state <<= __ffs(dd->idlest_mask);
322 while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
323 i < MAX_DPLL_WAIT_TRIES) {
328 if (i == MAX_DPLL_WAIT_TRIES) {
329 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
330 clk->name, (state) ? "locked" : "bypassed");
332 pr_debug("clock: %s transition to '%s' in %d loops\n",
333 clk->name, (state) ? "locked" : "bypassed", i);
341 /* From 3430 TRM ES2 4.7.6.2 */
342 static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
347 fint = clk->parent->rate / (n + 1);
349 pr_debug("clock: fint is %lu\n", fint);
351 if (fint >= 750000 && fint <= 1000000)
353 else if (fint > 1000000 && fint <= 1250000)
355 else if (fint > 1250000 && fint <= 1500000)
357 else if (fint > 1500000 && fint <= 1750000)
359 else if (fint > 1750000 && fint <= 2100000)
361 else if (fint > 7500000 && fint <= 10000000)
363 else if (fint > 10000000 && fint <= 12500000)
365 else if (fint > 12500000 && fint <= 15000000)
367 else if (fint > 15000000 && fint <= 17500000)
369 else if (fint > 17500000 && fint <= 21000000)
372 pr_debug("clock: unknown freqsel setting for %d\n", n);
377 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
380 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
381 * @clk: pointer to a DPLL struct clk
383 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
384 * readiness before returning. Will save and restore the DPLL's
385 * autoidle state across the enable, per the CDP code. If the DPLL
386 * locked successfully, return 0; if the DPLL did not lock in the time
387 * allotted, or DPLL3 was passed in, return -EINVAL.
389 static int _omap3_noncore_dpll_lock(struct clk *clk)
394 if (clk == &dpll3_ck)
397 pr_debug("clock: locking DPLL %s\n", clk->name);
399 ai = omap3_dpll_autoidle_read(clk);
401 omap3_dpll_deny_idle(clk);
403 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
405 r = _omap3_wait_dpll_status(clk, 1);
408 omap3_dpll_allow_idle(clk);
414 * omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
415 * @clk: pointer to a DPLL struct clk
417 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
418 * bypass mode, the DPLL's rate is set equal to its parent clock's
419 * rate. Waits for the DPLL to report readiness before returning.
420 * Will save and restore the DPLL's autoidle state across the enable,
421 * per the CDP code. If the DPLL entered bypass mode successfully,
422 * return 0; if the DPLL did not enter bypass in the time allotted, or
423 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
426 static int _omap3_noncore_dpll_bypass(struct clk *clk)
431 if (clk == &dpll3_ck)
434 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
437 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
440 ai = omap3_dpll_autoidle_read(clk);
442 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
444 r = _omap3_wait_dpll_status(clk, 0);
447 omap3_dpll_allow_idle(clk);
449 omap3_dpll_deny_idle(clk);
455 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
456 * @clk: pointer to a DPLL struct clk
458 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
459 * restore the DPLL's autoidle state across the stop, per the CDP
460 * code. If DPLL3 was passed in, or the DPLL does not support
461 * low-power stop, return -EINVAL; otherwise, return 0.
463 static int _omap3_noncore_dpll_stop(struct clk *clk)
467 if (clk == &dpll3_ck)
470 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
473 pr_debug("clock: stopping DPLL %s\n", clk->name);
475 ai = omap3_dpll_autoidle_read(clk);
477 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
480 omap3_dpll_allow_idle(clk);
482 omap3_dpll_deny_idle(clk);
488 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
489 * @clk: pointer to a DPLL struct clk
491 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
492 * The choice of modes depends on the DPLL's programmed rate: if it is
493 * the same as the DPLL's parent clock, it will enter bypass;
494 * otherwise, it will enter lock. This code will wait for the DPLL to
495 * indicate readiness before returning, unless the DPLL takes too long
496 * to enter the target state. Intended to be used as the struct clk's
497 * enable function. If DPLL3 was passed in, or the DPLL does not
498 * support low-power stop, or if the DPLL took too long to enter
499 * bypass or lock, return -EINVAL; otherwise, return 0.
501 static int omap3_noncore_dpll_enable(struct clk *clk)
505 if (clk == &dpll3_ck)
508 if (clk->parent->rate == omap2_get_dpll_rate(clk))
509 r = _omap3_noncore_dpll_bypass(clk);
511 r = _omap3_noncore_dpll_lock(clk);
517 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
518 * @clk: pointer to a DPLL struct clk
520 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
521 * The choice of modes depends on the DPLL's programmed rate: if it is
522 * the same as the DPLL's parent clock, it will enter bypass;
523 * otherwise, it will enter lock. This code will wait for the DPLL to
524 * indicate readiness before returning, unless the DPLL takes too long
525 * to enter the target state. Intended to be used as the struct clk's
526 * enable function. If DPLL3 was passed in, or the DPLL does not
527 * support low-power stop, or if the DPLL took too long to enter
528 * bypass or lock, return -EINVAL; otherwise, return 0.
530 static void omap3_noncore_dpll_disable(struct clk *clk)
532 if (clk == &dpll3_ck)
535 _omap3_noncore_dpll_stop(clk);
539 /* Non-CORE DPLL rate set code */
542 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
543 * @clk: struct clk * of DPLL to set
544 * @m: DPLL multiplier to set
545 * @n: DPLL divider to set
546 * @freqsel: FREQSEL value to set
548 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
549 * lock.. Returns -EINVAL upon error, or 0 upon success.
551 static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
553 struct dpll_data *dd = clk->dpll_data;
556 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
557 _omap3_noncore_dpll_bypass(clk);
559 /* Set jitter correction */
560 v = __raw_readl(dd->control_reg);
561 v &= ~dd->freqsel_mask;
562 v |= freqsel << __ffs(dd->freqsel_mask);
563 __raw_writel(v, dd->control_reg);
565 /* Set DPLL multiplier, divider */
566 v = __raw_readl(dd->mult_div1_reg);
567 v &= ~(dd->mult_mask | dd->div1_mask);
568 v |= m << __ffs(dd->mult_mask);
569 v |= (n - 1) << __ffs(dd->div1_mask);
570 __raw_writel(v, dd->mult_div1_reg);
572 /* We let the clock framework set the other output dividers later */
574 /* REVISIT: Set ramp-up delay? */
576 _omap3_noncore_dpll_lock(clk);
582 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
583 * @clk: struct clk * of DPLL to set
584 * @rate: rounded target rate
586 * Program the DPLL with the rounded target rate. Returns -EINVAL upon
587 * error, or 0 upon success.
589 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
592 struct dpll_data *dd;
601 if (rate == omap2_get_dpll_rate(clk))
604 if (dd->last_rounded_rate != rate)
605 omap2_dpll_round_rate(clk, rate);
607 if (dd->last_rounded_rate == 0)
610 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
614 omap3_noncore_dpll_program(clk, dd->last_rounded_m, dd->last_rounded_n,
617 omap3_dpll_recalc(clk);
622 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
625 * According to the 12-5 CDP code from TI, "Limitation 2.5"
626 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
629 if (omap_rev() == OMAP3430_REV_ES1_0) {
630 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
631 "silicon 'Limitation 2.5' on 3430ES1.\n");
634 return omap3_noncore_dpll_set_rate(clk, rate);
639 * CORE DPLL (DPLL3) rate programming functions
641 * These call into SRAM code to do the actual CM writes, since the SDRAM
642 * is clocked from DPLL3.
646 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
647 * @clk: struct clk * of DPLL to set
648 * @rate: rounded target rate
650 * Program the DPLL M2 divider with the rounded target rate. Returns
651 * -EINVAL upon error, or 0 upon success.
653 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
656 unsigned long validrate, sdrcrate;
657 struct omap_sdrc_params *sp;
662 if (clk != &dpll3_m2_ck)
665 if (rate == clk->rate)
668 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
669 if (validrate != rate)
672 sdrcrate = sdrc_ick.rate;
673 if (rate > clk->rate)
674 sdrcrate <<= ((rate / clk->rate) - 1);
676 sdrcrate >>= ((clk->rate / rate) - 1);
678 sp = omap2_sdrc_get_params(sdrcrate);
682 pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
684 pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
685 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
687 /* REVISIT: SRAM code doesn't support other M2 divisors yet */
688 WARN_ON(new_div != 1 && new_div != 2);
690 /* REVISIT: Add SDRC_MR changing to this code also */
692 omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
693 sp->actim_ctrlb, new_div);
696 omap2_clksel_recalc(clk);
702 static const struct clkops clkops_noncore_dpll_ops = {
703 .enable = &omap3_noncore_dpll_enable,
704 .disable = &omap3_noncore_dpll_disable,
707 /* DPLL autoidle read/set code */
711 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
712 * @clk: struct clk * of the DPLL to read
714 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
715 * -EINVAL if passed a null pointer or if the struct clk does not
716 * appear to refer to a DPLL.
718 static u32 omap3_dpll_autoidle_read(struct clk *clk)
720 const struct dpll_data *dd;
723 if (!clk || !clk->dpll_data)
728 v = __raw_readl(dd->autoidle_reg);
729 v &= dd->autoidle_mask;
730 v >>= __ffs(dd->autoidle_mask);
736 * omap3_dpll_allow_idle - enable DPLL autoidle bits
737 * @clk: struct clk * of the DPLL to operate on
739 * Enable DPLL automatic idle control. This automatic idle mode
740 * switching takes effect only when the DPLL is locked, at least on
741 * OMAP3430. The DPLL will enter low-power stop when its downstream
742 * clocks are gated. No return value.
744 static void omap3_dpll_allow_idle(struct clk *clk)
746 const struct dpll_data *dd;
749 if (!clk || !clk->dpll_data)
755 * REVISIT: CORE DPLL can optionally enter low-power bypass
756 * by writing 0x5 instead of 0x1. Add some mechanism to
757 * optionally enter this mode.
759 v = __raw_readl(dd->autoidle_reg);
760 v &= ~dd->autoidle_mask;
761 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
762 __raw_writel(v, dd->autoidle_reg);
766 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
767 * @clk: struct clk * of the DPLL to operate on
769 * Disable DPLL automatic idle control. No return value.
771 static void omap3_dpll_deny_idle(struct clk *clk)
773 const struct dpll_data *dd;
776 if (!clk || !clk->dpll_data)
781 v = __raw_readl(dd->autoidle_reg);
782 v &= ~dd->autoidle_mask;
783 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
784 __raw_writel(v, dd->autoidle_reg);
787 /* Clock control for DPLL outputs */
790 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
791 * @clk: DPLL output struct clk
793 * Using parent clock DPLL data, look up DPLL state. If locked, set our
794 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
796 static void omap3_clkoutx2_recalc(struct clk *clk)
798 const struct dpll_data *dd;
802 /* Walk up the parents of clk, looking for a DPLL */
804 while (pclk && !pclk->dpll_data)
807 /* clk does not have a DPLL as a parent? */
810 dd = pclk->dpll_data;
812 WARN_ON(!dd->control_reg || !dd->enable_mask);
814 v = __raw_readl(dd->control_reg) & dd->enable_mask;
815 v >>= __ffs(dd->enable_mask);
816 if (v != DPLL_LOCKED)
817 clk->rate = clk->parent->rate;
819 clk->rate = clk->parent->rate * 2;
822 /* Common clock code */
825 * As it is structured now, this will prevent an OMAP2/3 multiboot
826 * kernel from compiling. This will need further attention.
828 #if defined(CONFIG_ARCH_OMAP3)
830 static struct clk_functions omap2_clk_functions = {
831 .clk_enable = omap2_clk_enable,
832 .clk_disable = omap2_clk_disable,
833 .clk_round_rate = omap2_clk_round_rate,
834 .clk_set_rate = omap2_clk_set_rate,
835 .clk_set_parent = omap2_clk_set_parent,
836 .clk_disable_unused = omap2_clk_disable_unused,
840 * Set clocks for bypass mode for reboot to work.
842 void omap2_clk_prepare_for_reboot(void)
844 /* REVISIT: Not ready for 343x */
848 if (vclk == NULL || sclk == NULL)
851 rate = clk_get_rate(sclk);
852 clk_set_rate(vclk, rate);
856 /* REVISIT: Move this init stuff out into clock.c */
859 * Switch the MPU rate if specified on cmdline.
860 * We cannot do this early until cmdline is parsed.
862 static int __init omap2_clk_arch_init(void)
867 /* REVISIT: not yet ready for 343x */
869 if (clk_set_rate(&virt_prcm_set, mpurate))
870 printk(KERN_ERR "Could not find matching MPU rate\n");
873 recalculate_root_clocks();
875 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
876 "%ld.%01ld/%ld/%ld MHz\n",
877 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
878 (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
882 arch_initcall(omap2_clk_arch_init);
884 int __init omap2_clk_init(void)
886 /* struct prcm_config *prcm; */
891 if (cpu_is_omap34xx()) {
892 cpu_mask = RATE_IN_343X;
893 cpu_clkflg = CK_343X;
896 * Update this if there are further clock changes between ES2
897 * and production parts
899 if (omap_rev() == OMAP3430_REV_ES1_0) {
900 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
901 cpu_clkflg |= CK_3430ES1;
903 cpu_mask |= RATE_IN_3430ES2;
904 cpu_clkflg |= CK_3430ES2;
908 clk_init(&omap2_clk_functions);
910 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
911 if (c->cpu & cpu_clkflg) {
913 clk_register(c->lk.clk);
914 omap2_init_clk_clkdm(c->lk.clk);
917 /* REVISIT: Not yet ready for OMAP3 */
919 /* Check the MPU rate set by bootloader */
920 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
921 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
922 if (!(prcm->flags & cpu_mask))
924 if (prcm->xtal_speed != sys_ck.rate)
926 if (prcm->dpll_speed <= clkrate)
929 curr_prcm_set = prcm;
932 recalculate_root_clocks();
934 printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
935 "%ld.%01ld/%ld/%ld MHz\n",
936 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
937 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
940 * Only enable those clocks we will need, let the drivers
941 * enable other clocks as necessary
943 clk_enable_init_clocks();
945 /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
946 /* REVISIT: not yet ready for 343x */
948 vclk = clk_get(NULL, "virt_prcm_set");
949 sclk = clk_get(NULL, "sys_ck");