2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
25 #include <linux/bitops.h>
27 #include <mach/clock.h>
28 #include <mach/clockdomain.h>
30 #include <asm/div64.h>
36 #include "prm-regbits-24xx.h"
38 #include "cm-regbits-24xx.h"
39 #include "cm-regbits-34xx.h"
41 #define MAX_CLOCK_ENABLE_WAIT 100000
43 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
44 #define DPLL_MIN_MULTIPLIER 1
45 #define DPLL_MIN_DIVIDER 1
47 /* Possible error results from _dpll_test_mult */
48 #define DPLL_MULT_UNDERFLOW -1
51 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
52 * The higher the scale factor, the greater the risk of arithmetic overflow,
53 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
54 * must be a power of DPLL_SCALE_BASE.
56 #define DPLL_SCALE_FACTOR 64
57 #define DPLL_SCALE_BASE 2
58 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
59 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
63 /*-------------------------------------------------------------------------
64 * OMAP2/3 specific clock functions
65 *-------------------------------------------------------------------------*/
68 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
69 * @clk: OMAP clock struct ptr to use
71 * Convert a clockdomain name stored in a struct clk 'clk' into a
72 * clockdomain pointer, and save it into the struct clk. Intended to be
73 * called during clk_register(). No return value.
75 void omap2_init_clk_clkdm(struct clk *clk)
77 struct clockdomain *clkdm;
82 clkdm = clkdm_lookup(clk->clkdm_name);
84 pr_debug("clock: associated clk %s to clkdm %s\n",
85 clk->name, clk->clkdm_name);
88 pr_debug("clock: could not associate clk %s to "
89 "clkdm %s\n", clk->name, clk->clkdm_name);
94 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
95 * @clk: OMAP clock struct ptr to use
97 * Given a pointer to a source-selectable struct clk, read the hardware
98 * register and determine what its parent is currently set to. Update the
99 * clk->parent field with the appropriate clk ptr.
101 void omap2_init_clksel_parent(struct clk *clk)
103 const struct clksel *clks;
104 const struct clksel_rate *clkr;
110 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
111 r >>= __ffs(clk->clksel_mask);
113 for (clks = clk->clksel; clks->parent && !found; clks++) {
114 for (clkr = clks->rates; clkr->div && !found; clkr++) {
115 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
116 if (clk->parent != clks->parent) {
117 pr_debug("clock: inited %s parent "
119 clk->name, clks->parent->name,
121 clk->parent->name : "NULL"));
122 clk->parent = clks->parent;
130 printk(KERN_ERR "clock: init parent: could not find "
131 "regval %0x for clock %s\n", r, clk->name);
136 /* Returns the DPLL rate */
137 u32 omap2_get_dpll_rate(struct clk *clk)
140 u32 dpll_mult, dpll_div, dpll;
141 struct dpll_data *dd;
144 /* REVISIT: What do we return on error? */
148 dpll = __raw_readl(dd->mult_div1_reg);
149 dpll_mult = dpll & dd->mult_mask;
150 dpll_mult >>= __ffs(dd->mult_mask);
151 dpll_div = dpll & dd->div1_mask;
152 dpll_div >>= __ffs(dd->div1_mask);
154 dpll_clk = (long long)clk->parent->rate * dpll_mult;
155 do_div(dpll_clk, dpll_div + 1);
161 * Used for clocks that have the same value as the parent clock,
162 * divided by some factor
164 void omap2_fixed_divisor_recalc(struct clk *clk)
166 WARN_ON(!clk->fixed_div);
168 clk->rate = clk->parent->rate / clk->fixed_div;
172 * omap2_wait_clock_ready - wait for clock to enable
173 * @reg: physical address of clock IDLEST register
174 * @mask: value to mask against to determine if the clock is active
175 * @name: name of the clock (for printk)
177 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
178 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
180 int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
186 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
187 * 34xx reverses this, just to keep us on our toes
189 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
191 else if (cpu_mask & RATE_IN_343X)
195 while (((__raw_readl(reg) & mask) != ena) &&
196 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
200 if (i < MAX_CLOCK_ENABLE_WAIT)
201 pr_debug("Clock %s stable after %d loops\n", name, i);
203 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
204 name, MAX_CLOCK_ENABLE_WAIT);
207 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
212 * Note: We don't need special code here for INVERT_ENABLE
213 * for the time being since INVERT_ENABLE only applies to clocks enabled by
216 static void omap2_clk_wait_ready(struct clk *clk)
218 void __iomem *reg, *other_reg, *st_reg;
222 * REVISIT: This code is pretty ugly. It would be nice to generalize
223 * it and pull it into struct clk itself somehow.
225 reg = clk->enable_reg;
228 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
229 * it's just a matter of XORing the bits.
231 other_reg = (void __iomem *)((u32)reg ^ (CM_FCLKEN ^ CM_ICLKEN));
233 /* Check if both functional and interface clocks
235 bit = 1 << clk->enable_bit;
236 if (!(__raw_readl(other_reg) & bit))
238 st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
240 omap2_wait_clock_ready(st_reg, bit, clk->name);
243 static int omap2_dflt_clk_enable(struct clk *clk)
247 if (unlikely(clk->enable_reg == NULL)) {
248 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
250 return 0; /* REVISIT: -EINVAL */
253 regval32 = __raw_readl(clk->enable_reg);
254 if (clk->flags & INVERT_ENABLE)
255 regval32 &= ~(1 << clk->enable_bit);
257 regval32 |= (1 << clk->enable_bit);
258 __raw_writel(regval32, clk->enable_reg);
264 static int omap2_dflt_clk_enable_wait(struct clk *clk)
268 if (!clk->enable_reg) {
269 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
271 return 0; /* REVISIT: -EINVAL */
274 ret = omap2_dflt_clk_enable(clk);
276 omap2_clk_wait_ready(clk);
280 static void omap2_dflt_clk_disable(struct clk *clk)
284 if (!clk->enable_reg) {
286 * 'Independent' here refers to a clock which is not
287 * controlled by its parent.
289 printk(KERN_ERR "clock: clk_disable called on independent "
290 "clock %s which has no enable_reg\n", clk->name);
294 regval32 = __raw_readl(clk->enable_reg);
295 if (clk->flags & INVERT_ENABLE)
296 regval32 |= (1 << clk->enable_bit);
298 regval32 &= ~(1 << clk->enable_bit);
299 __raw_writel(regval32, clk->enable_reg);
303 const struct clkops clkops_omap2_dflt_wait = {
304 .enable = omap2_dflt_clk_enable_wait,
305 .disable = omap2_dflt_clk_disable,
308 const struct clkops clkops_omap2_dflt = {
309 .enable = omap2_dflt_clk_enable,
310 .disable = omap2_dflt_clk_disable,
313 /* Enables clock without considering parent dependencies or use count
314 * REVISIT: Maybe change this to use clk->enable like on omap1?
316 static int _omap2_clk_enable(struct clk *clk)
318 return clk->ops->enable(clk);
321 /* Disables clock without considering parent dependencies or use count */
322 static void _omap2_clk_disable(struct clk *clk)
324 clk->ops->disable(clk);
327 void omap2_clk_disable(struct clk *clk)
329 if (clk->usecount > 0 && !(--clk->usecount)) {
330 _omap2_clk_disable(clk);
332 omap2_clk_disable(clk->parent);
334 omap2_clkdm_clk_disable(clk->clkdm, clk);
339 int omap2_clk_enable(struct clk *clk)
343 if (clk->usecount++ == 0) {
345 ret = omap2_clk_enable(clk->parent);
353 omap2_clkdm_clk_enable(clk->clkdm, clk);
355 ret = _omap2_clk_enable(clk);
359 omap2_clkdm_clk_disable(clk->clkdm, clk);
362 omap2_clk_disable(clk->parent);
372 * Used for clocks that are part of CLKSEL_xyz governed clocks.
373 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
375 void omap2_clksel_recalc(struct clk *clk)
379 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
381 div = omap2_clksel_get_divisor(clk);
385 if (clk->rate == (clk->parent->rate / div))
387 clk->rate = clk->parent->rate / div;
389 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
393 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
394 * @clk: OMAP struct clk ptr to inspect
395 * @src_clk: OMAP struct clk ptr of the parent clk to search for
397 * Scan the struct clksel array associated with the clock to find
398 * the element associated with the supplied parent clock address.
399 * Returns a pointer to the struct clksel on success or NULL on error.
401 static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
404 const struct clksel *clks;
409 for (clks = clk->clksel; clks->parent; clks++) {
410 if (clks->parent == src_clk)
411 break; /* Found the requested parent */
415 printk(KERN_ERR "clock: Could not find parent clock %s in "
416 "clksel array of clock %s\n", src_clk->name,
425 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
426 * @clk: OMAP struct clk to use
427 * @target_rate: desired clock rate
428 * @new_div: ptr to where we should store the divisor
430 * Finds 'best' divider value in an array based on the source and target
431 * rates. The divider array must be sorted with smallest divider first.
432 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
433 * they are only settable as part of virtual_prcm set.
435 * Returns the rounded clock rate or returns 0xffffffff on error.
437 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
440 unsigned long test_rate;
441 const struct clksel *clks;
442 const struct clksel_rate *clkr;
445 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
446 clk->name, target_rate);
450 clks = omap2_get_clksel_by_parent(clk, clk->parent);
454 for (clkr = clks->rates; clkr->div; clkr++) {
455 if (!(clkr->flags & cpu_mask))
459 if (clkr->div <= last_div)
460 printk(KERN_ERR "clock: clksel_rate table not sorted "
461 "for clock %s", clk->name);
463 last_div = clkr->div;
465 test_rate = clk->parent->rate / clkr->div;
467 if (test_rate <= target_rate)
468 break; /* found it */
472 printk(KERN_ERR "clock: Could not find divisor for target "
473 "rate %ld for clock %s parent %s\n", target_rate,
474 clk->name, clk->parent->name);
478 *new_div = clkr->div;
480 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
481 (clk->parent->rate / clkr->div));
483 return (clk->parent->rate / clkr->div);
487 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
488 * @clk: OMAP struct clk to use
489 * @target_rate: desired clock rate
491 * Compatibility wrapper for OMAP clock framework
492 * Finds best target rate based on the source clock and possible dividers.
493 * rates. The divider array must be sorted with smallest divider first.
494 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
495 * they are only settable as part of virtual_prcm set.
497 * Returns the rounded clock rate or returns 0xffffffff on error.
499 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
503 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
507 /* Given a clock and a rate apply a clock specific rounding function */
508 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
511 return clk->round_rate(clk, rate);
513 if (clk->flags & RATE_FIXED)
514 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
515 "on fixed-rate clock %s\n", clk->name);
521 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
522 * @clk: OMAP struct clk to use
523 * @field_val: register field value to find
525 * Given a struct clk of a rate-selectable clksel clock, and a register field
526 * value to search for, find the corresponding clock divisor. The register
527 * field value should be pre-masked and shifted down so the LSB is at bit 0
528 * before calling. Returns 0 on error
530 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
532 const struct clksel *clks;
533 const struct clksel_rate *clkr;
535 clks = omap2_get_clksel_by_parent(clk, clk->parent);
539 for (clkr = clks->rates; clkr->div; clkr++) {
540 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
545 printk(KERN_ERR "clock: Could not find fieldval %d for "
546 "clock %s parent %s\n", field_val, clk->name,
555 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
556 * @clk: OMAP struct clk to use
557 * @div: integer divisor to search for
559 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
560 * find the corresponding register field value. The return register value is
561 * the value before left-shifting. Returns 0xffffffff on error
563 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
565 const struct clksel *clks;
566 const struct clksel_rate *clkr;
568 /* should never happen */
571 clks = omap2_get_clksel_by_parent(clk, clk->parent);
575 for (clkr = clks->rates; clkr->div; clkr++) {
576 if ((clkr->flags & cpu_mask) && (clkr->div == div))
581 printk(KERN_ERR "clock: Could not find divisor %d for "
582 "clock %s parent %s\n", div, clk->name,
591 * omap2_get_clksel - find clksel register addr & field mask for a clk
592 * @clk: struct clk to use
593 * @field_mask: ptr to u32 to store the register field mask
595 * Returns the address of the clksel register upon success or NULL on error.
597 static void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
599 if (!clk->clksel_reg || (clk->clksel_mask == 0))
602 *field_mask = clk->clksel_mask;
604 return clk->clksel_reg;
608 * omap2_clksel_get_divisor - get current divider applied to parent clock.
609 * @clk: OMAP struct clk to use.
611 * Returns the integer divisor upon success or 0 on error.
613 u32 omap2_clksel_get_divisor(struct clk *clk)
615 u32 field_mask, field_val;
616 void __iomem *div_addr;
618 div_addr = omap2_get_clksel(clk, &field_mask);
622 field_val = __raw_readl(div_addr) & field_mask;
623 field_val >>= __ffs(field_mask);
625 return omap2_clksel_to_divisor(clk, field_val);
628 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
630 u32 field_mask, field_val, reg_val, validrate, new_div = 0;
631 void __iomem *div_addr;
633 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
634 if (validrate != rate)
637 div_addr = omap2_get_clksel(clk, &field_mask);
641 field_val = omap2_divisor_to_clksel(clk, new_div);
645 reg_val = __raw_readl(div_addr);
646 reg_val &= ~field_mask;
647 reg_val |= (field_val << __ffs(field_mask));
648 __raw_writel(reg_val, div_addr);
651 clk->rate = clk->parent->rate / new_div;
653 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
654 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
655 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
663 /* Set the clock rate for a clock source */
664 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
668 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
670 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
671 rate table mechanism, driven by mpu_speed */
672 if (clk->flags & CONFIG_PARTICIPANT)
675 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
677 ret = clk->set_rate(clk, rate);
683 * Converts encoded control register address into a full address
684 * On error, *src_addr will be returned as 0.
686 static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
687 struct clk *src_clk, u32 *field_mask,
688 struct clk *clk, u32 *parent_div)
690 const struct clksel *clks;
691 const struct clksel_rate *clkr;
696 clks = omap2_get_clksel_by_parent(clk, src_clk);
700 for (clkr = clks->rates; clkr->div; clkr++) {
701 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
702 break; /* Found the default rate for this platform */
706 printk(KERN_ERR "clock: Could not find default rate for "
707 "clock %s parent %s\n", clk->name,
708 src_clk->parent->name);
712 /* Should never happen. Add a clksel mask to the struct clk. */
713 WARN_ON(clk->clksel_mask == 0);
715 *field_mask = clk->clksel_mask;
716 *src_addr = clk->clksel_reg;
717 *parent_div = clkr->div;
722 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
724 void __iomem *src_addr;
725 u32 field_val, field_mask, reg_val, parent_div;
727 if (clk->flags & CONFIG_PARTICIPANT)
733 field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
734 &field_mask, clk, &parent_div);
738 if (clk->usecount > 0)
739 _omap2_clk_disable(clk);
741 /* Set new source value (previous dividers if any in effect) */
742 reg_val = __raw_readl(src_addr) & ~field_mask;
743 reg_val |= (field_val << __ffs(field_mask));
744 __raw_writel(reg_val, src_addr);
747 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
748 __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
752 if (clk->usecount > 0)
753 _omap2_clk_enable(clk);
755 clk->parent = new_parent;
757 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
758 clk->rate = new_parent->rate;
761 clk->rate /= parent_div;
763 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
764 clk->name, clk->parent->name, clk->rate);
769 /* DPLL rate rounding code */
772 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
773 * @clk: struct clk * of the DPLL
774 * @tolerance: maximum rate error tolerance
776 * Set the maximum DPLL rate error tolerance for the rate rounding
777 * algorithm. The rate tolerance is an attempt to balance DPLL power
778 * saving (the least divider value "n") vs. rate fidelity (the least
779 * difference between the desired DPLL target rate and the rounded
780 * rate out of the algorithm). So, increasing the tolerance is likely
781 * to decrease DPLL power consumption and increase DPLL rate error.
782 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
783 * DPLL; or 0 upon success.
785 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
787 if (!clk || !clk->dpll_data)
790 clk->dpll_data->rate_tolerance = tolerance;
795 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
796 unsigned int m, unsigned int n)
798 unsigned long long num;
800 num = (unsigned long long)parent_rate * m;
806 * _dpll_test_mult - test a DPLL multiplier value
807 * @m: pointer to the DPLL m (multiplier) value under test
808 * @n: current DPLL n (divider) value under test
809 * @new_rate: pointer to storage for the resulting rounded rate
810 * @target_rate: the desired DPLL rate
811 * @parent_rate: the DPLL's parent clock rate
813 * This code tests a DPLL multiplier value, ensuring that the
814 * resulting rate will not be higher than the target_rate, and that
815 * the multiplier value itself is valid for the DPLL. Initially, the
816 * integer pointed to by the m argument should be prescaled by
817 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
818 * a non-scaled m upon return. This non-scaled m will result in a
819 * new_rate as close as possible to target_rate (but not greater than
820 * target_rate) given the current (parent_rate, n, prescaled m)
821 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
822 * non-scaled m attempted to underflow, which can allow the calling
823 * function to bail out early; or 0 upon success.
825 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
826 unsigned long target_rate,
827 unsigned long parent_rate)
829 int r = 0, carry = 0;
831 /* Unscale m and round if necessary */
832 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
834 *m = (*m / DPLL_SCALE_FACTOR) + carry;
837 * The new rate must be <= the target rate to avoid programming
838 * a rate that is impossible for the hardware to handle
840 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
841 if (*new_rate > target_rate) {
846 /* Guard against m underflow */
847 if (*m < DPLL_MIN_MULTIPLIER) {
848 *m = DPLL_MIN_MULTIPLIER;
850 r = DPLL_MULT_UNDERFLOW;
854 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
860 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
861 * @clk: struct clk * for a DPLL
862 * @target_rate: desired DPLL clock rate
864 * Given a DPLL, a desired target rate, and a rate tolerance, round
865 * the target rate to a possible, programmable rate for this DPLL.
866 * Rate tolerance is assumed to be set by the caller before this
867 * function is called. Attempts to select the minimum possible n
868 * within the tolerance to reduce power consumption. Stores the
869 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
870 * will not need to call this (expensive) function again. Returns ~0
871 * if the target rate cannot be rounded, either because the rate is
872 * too low or because the rate tolerance is set too tightly; or the
873 * rounded rate upon success.
875 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
877 int m, n, r, e, scaled_max_m;
878 unsigned long scaled_rt_rp, new_rate;
879 int min_e = -1, min_e_m = -1, min_e_n = -1;
880 struct dpll_data *dd;
882 if (!clk || !clk->dpll_data)
887 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
888 "%ld\n", clk->name, target_rate);
890 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
891 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
893 dd->last_rounded_rate = 0;
895 for (n = DPLL_MIN_DIVIDER; n <= dd->max_divider; n++) {
897 /* Compute the scaled DPLL multiplier, based on the divider */
898 m = scaled_rt_rp * n;
901 * Since we're counting n up, a m overflow means we
902 * can bail out completely (since as n increases in
903 * the next iteration, there's no way that m can
904 * increase beyond the current m)
906 if (m > scaled_max_m)
909 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
912 /* m can't be set low enough for this n - try with a larger n */
913 if (r == DPLL_MULT_UNDERFLOW)
916 e = target_rate - new_rate;
917 pr_debug("clock: n = %d: m = %d: rate error is %d "
918 "(new_rate = %ld)\n", n, m, e, new_rate);
921 min_e >= (int)(abs(e) - dd->rate_tolerance)) {
926 pr_debug("clock: found new least error %d\n", min_e);
928 /* We found good settings -- bail out now */
929 if (min_e <= clk->dpll_data->rate_tolerance)
935 pr_debug("clock: error: target rate or tolerance too low\n");
939 dd->last_rounded_m = min_e_m;
940 dd->last_rounded_n = min_e_n;
941 dd->last_rounded_rate = _dpll_compute_new_rate(clk->parent->rate,
944 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
945 min_e, min_e_m, min_e_n);
946 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
947 dd->last_rounded_rate, target_rate);
949 return dd->last_rounded_rate;
952 /*-------------------------------------------------------------------------
953 * Omap2 clock reset and init functions
954 *-------------------------------------------------------------------------*/
956 #ifdef CONFIG_OMAP_RESET_CLOCKS
957 void omap2_clk_disable_unused(struct clk *clk)
961 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
963 regval32 = __raw_readl(clk->enable_reg);
964 if ((regval32 & (1 << clk->enable_bit)) == v)
967 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
968 _omap2_clk_disable(clk);