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   1 /*
   2  *  linux/arch/arm/mach-omap1/clock.h
   3  *
   4  *  Copyright (C) 2004 - 2005 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
  14 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
  15
  16 static void omap1_ckctl_recalc(struct clk * clk);
  17 static void omap1_watchdog_recalc(struct clk * clk);
  18 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
  19 static void omap1_sossi_recalc(struct clk *clk);
  20 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk);
  21 static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
  22 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
  23 static void omap1_uart_recalc(struct clk * clk);
  24 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
  25 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
  26 static void omap1_init_ext_clk(struct clk * clk);
  27 static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
  28 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
  29
  30 static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
  31 static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
  32
  33 struct mpu_rate {
  34         unsigned long           rate;
  35         unsigned long           xtal;
  36         unsigned long           pll_rate;
  37         __u16                   ckctl_val;
  38         __u16                   dpllctl_val;
  39 };
  40
  41 struct uart_clk {
  42         struct clk      clk;
  43         unsigned long   sysc_addr;
  44 };
  45
  46 /* Provide a method for preventing idling some ARM IDLECT clocks */
  47 struct arm_idlect1_clk {
  48         struct clk      clk;
  49         unsigned long   no_idle_count;
  50         __u8            idlect_shift;
  51 };
  52
  53 /* ARM_CKCTL bit shifts */
  54 #define CKCTL_PERDIV_OFFSET     0
  55 #define CKCTL_LCDDIV_OFFSET     2
  56 #define CKCTL_ARMDIV_OFFSET     4
  57 #define CKCTL_DSPDIV_OFFSET     6
  58 #define CKCTL_TCDIV_OFFSET      8
  59 #define CKCTL_DSPMMUDIV_OFFSET  10
  60 /*#define ARM_TIMXO             12*/
  61 #define EN_DSPCK                13
  62 /*#define ARM_INTHCK_SEL        14*/ /* Divide-by-2 for mpu inth_ck */
  63 /* DSP_CKCTL bit shifts */
  64 #define CKCTL_DSPPERDIV_OFFSET  0
  65
  66 /* ARM_IDLECT2 bit shifts */
  67 #define EN_WDTCK        0
  68 #define EN_XORPCK       1
  69 #define EN_PERCK        2
  70 #define EN_LCDCK        3
  71 #define EN_LBCK         4 /* Not on 1610/1710 */
  72 /*#define EN_HSABCK     5*/
  73 #define EN_APICK        6
  74 #define EN_TIMCK        7
  75 #define DMACK_REQ       8
  76 #define EN_GPIOCK       9 /* Not on 1610/1710 */
  77 /*#define EN_LBFREECK   10*/
  78 #define EN_CKOUT_ARM    11
  79
  80 /* ARM_IDLECT3 bit shifts */
  81 #define EN_OCPI_CK      0
  82 #define EN_TC1_CK       2
  83 #define EN_TC2_CK       4
  84
  85 /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
  86 #define EN_DSPTIMCK     5
  87
  88 /* Various register defines for clock controls scattered around OMAP chip */
  89 #define SDW_MCLK_INV_BIT        2       /* In ULPD_CLKC_CTRL */
  90 #define USB_MCLK_EN_BIT         4       /* In ULPD_CLKC_CTRL */
  91 #define USB_HOST_HHC_UHOST_EN   9       /* In MOD_CONF_CTRL_0 */
  92 #define SWD_ULPD_PLL_CLK_REQ    1       /* In SWD_CLK_DIV_CTRL_SEL */
  93 #define COM_ULPD_PLL_CLK_REQ    1       /* In COM_CLK_DIV_CTRL_SEL */
  94 #define SWD_CLK_DIV_CTRL_SEL    0xfffe0874
  95 #define COM_CLK_DIV_CTRL_SEL    0xfffe0878
  96 #define SOFT_REQ_REG            0xfffe0834
  97 #define SOFT_REQ_REG2           0xfffe0880
  98
  99 /*-------------------------------------------------------------------------
 100  * Omap1 MPU rate table
 101  *-------------------------------------------------------------------------*/
 102 static struct mpu_rate rate_table[] = {
 103         /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
 104          * NOTE: Comment order here is different from bits in CKCTL value:
 105          * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
 106          */
 107 #if defined(CONFIG_OMAP_ARM_216MHZ)
 108         { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
 109 #endif
 110 #if defined(CONFIG_OMAP_ARM_195MHZ)
 111         { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
 112 #endif
 113 #if defined(CONFIG_OMAP_ARM_192MHZ)
 114         { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
 115         { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
 116         {  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
 117         {  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
 118         {  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
 119 #endif
 120 #if defined(CONFIG_OMAP_ARM_182MHZ)
 121         { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
 122 #endif
 123 #if defined(CONFIG_OMAP_ARM_168MHZ)
 124         { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
 125 #endif
 126 #if defined(CONFIG_OMAP_ARM_150MHZ)
 127         { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
 128 #endif
 129 #if defined(CONFIG_OMAP_ARM_120MHZ)
 130         { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
 131 #endif
 132 #if defined(CONFIG_OMAP_ARM_96MHZ)
 133         {  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
 134 #endif
 135 #if defined(CONFIG_OMAP_ARM_60MHZ)
 136         {  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
 137 #endif
 138 #if defined(CONFIG_OMAP_ARM_30MHZ)
 139         {  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
 140 #endif
 141         { 0, 0, 0, 0, 0 },
 142 };
 143
 144 /*-------------------------------------------------------------------------
 145  * Omap1 clocks
 146  *-------------------------------------------------------------------------*/
 147
 148 static struct clk ck_ref = {
 149         .name           = "ck_ref",
 150         .ops            = &clkops_null,
 151         .rate           = 12000000,
 152 };
 153
 154 static struct clk ck_dpll1 = {
 155         .name           = "ck_dpll1",
 156         .ops            = &clkops_null,
 157         .parent         = &ck_ref,
 158         .flags          = RATE_PROPAGATES,
 159 };
 160
 161 static struct arm_idlect1_clk ck_dpll1out = {
 162         .clk = {
 163                 .name           = "ck_dpll1out",
 164                 .ops            = &clkops_generic,
 165                 .parent         = &ck_dpll1,
 166                 .flags          = CLOCK_IDLE_CONTROL |
 167                                   ENABLE_REG_32BIT | RATE_PROPAGATES,
 168                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 169                 .enable_bit     = EN_CKOUT_ARM,
 170                 .recalc         = &followparent_recalc,
 171         },
 172         .idlect_shift   = 12,
 173 };
 174
 175 static struct clk sossi_ck = {
 176         .name           = "ck_sossi",
 177         .ops            = &clkops_generic,
 178         .parent         = &ck_dpll1out.clk,
 179         .flags          = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
 180         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
 181         .enable_bit     = 16,
 182         .recalc         = &omap1_sossi_recalc,
 183         .set_rate       = &omap1_set_sossi_rate,
 184 };
 185
 186 static struct clk arm_ck = {
 187         .name           = "arm_ck",
 188         .ops            = &clkops_null,
 189         .parent         = &ck_dpll1,
 190         .flags          = RATE_PROPAGATES,
 191         .rate_offset    = CKCTL_ARMDIV_OFFSET,
 192         .recalc         = &omap1_ckctl_recalc,
 193         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 194         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 195 };
 196
 197 static struct arm_idlect1_clk armper_ck = {
 198         .clk = {
 199                 .name           = "armper_ck",
 200                 .ops            = &clkops_generic,
 201                 .parent         = &ck_dpll1,
 202                 .flags          = CLOCK_IDLE_CONTROL,
 203                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 204                 .enable_bit     = EN_PERCK,
 205                 .rate_offset    = CKCTL_PERDIV_OFFSET,
 206                 .recalc         = &omap1_ckctl_recalc,
 207                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 208                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 209         },
 210         .idlect_shift   = 2,
 211 };
 212
 213 static struct clk arm_gpio_ck = {
 214         .name           = "arm_gpio_ck",
 215         .ops            = &clkops_generic,
 216         .parent         = &ck_dpll1,
 217         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 218         .enable_bit     = EN_GPIOCK,
 219         .recalc         = &followparent_recalc,
 220 };
 221
 222 static struct arm_idlect1_clk armxor_ck = {
 223         .clk = {
 224                 .name           = "armxor_ck",
 225                 .ops            = &clkops_generic,
 226                 .parent         = &ck_ref,
 227                 .flags          = CLOCK_IDLE_CONTROL,
 228                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 229                 .enable_bit     = EN_XORPCK,
 230                 .recalc         = &followparent_recalc,
 231         },
 232         .idlect_shift   = 1,
 233 };
 234
 235 static struct arm_idlect1_clk armtim_ck = {
 236         .clk = {
 237                 .name           = "armtim_ck",
 238                 .ops            = &clkops_generic,
 239                 .parent         = &ck_ref,
 240                 .flags          = CLOCK_IDLE_CONTROL,
 241                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 242                 .enable_bit     = EN_TIMCK,
 243                 .recalc         = &followparent_recalc,
 244         },
 245         .idlect_shift   = 9,
 246 };
 247
 248 static struct arm_idlect1_clk armwdt_ck = {
 249         .clk = {
 250                 .name           = "armwdt_ck",
 251                 .ops            = &clkops_generic,
 252                 .parent         = &ck_ref,
 253                 .flags          = CLOCK_IDLE_CONTROL,
 254                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 255                 .enable_bit     = EN_WDTCK,
 256                 .recalc         = &omap1_watchdog_recalc,
 257         },
 258         .idlect_shift   = 0,
 259 };
 260
 261 static struct clk arminth_ck16xx = {
 262         .name           = "arminth_ck",
 263         .ops            = &clkops_null,
 264         .parent         = &arm_ck,
 265         .recalc         = &followparent_recalc,
 266         /* Note: On 16xx the frequency can be divided by 2 by programming
 267          * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
 268          *
 269          * 1510 version is in TC clocks.
 270          */
 271 };
 272
 273 static struct clk dsp_ck = {
 274         .name           = "dsp_ck",
 275         .ops            = &clkops_generic,
 276         .parent         = &ck_dpll1,
 277         .enable_reg     = OMAP1_IO_ADDRESS(ARM_CKCTL),
 278         .enable_bit     = EN_DSPCK,
 279         .rate_offset    = CKCTL_DSPDIV_OFFSET,
 280         .recalc         = &omap1_ckctl_recalc,
 281         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 282         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 283 };
 284
 285 static struct clk dspmmu_ck = {
 286         .name           = "dspmmu_ck",
 287         .ops            = &clkops_null,
 288         .parent         = &ck_dpll1,
 289         .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
 290         .recalc         = &omap1_ckctl_recalc,
 291         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 292         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 293 };
 294
 295 static struct clk dspper_ck = {
 296         .name           = "dspper_ck",
 297         .ops            = &clkops_dspck,
 298         .parent         = &ck_dpll1,
 299         .enable_reg     = DSP_IDLECT2,
 300         .enable_bit     = EN_PERCK,
 301         .rate_offset    = CKCTL_PERDIV_OFFSET,
 302         .recalc         = &omap1_ckctl_recalc_dsp_domain,
 303         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 304         .set_rate       = &omap1_clk_set_rate_dsp_domain,
 305 };
 306
 307 static struct clk dspxor_ck = {
 308         .name           = "dspxor_ck",
 309         .ops            = &clkops_dspck,
 310         .parent         = &ck_ref,
 311         .enable_reg     = DSP_IDLECT2,
 312         .enable_bit     = EN_XORPCK,
 313         .recalc         = &followparent_recalc,
 314 };
 315
 316 static struct clk dsptim_ck = {
 317         .name           = "dsptim_ck",
 318         .ops            = &clkops_dspck,
 319         .parent         = &ck_ref,
 320         .enable_reg     = DSP_IDLECT2,
 321         .enable_bit     = EN_DSPTIMCK,
 322         .recalc         = &followparent_recalc,
 323 };
 324
 325 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
 326 static struct arm_idlect1_clk tc_ck = {
 327         .clk = {
 328                 .name           = "tc_ck",
 329                 .ops            = &clkops_null,
 330                 .parent         = &ck_dpll1,
 331                 .flags          = RATE_PROPAGATES | CLOCK_IDLE_CONTROL,
 332                 .rate_offset    = CKCTL_TCDIV_OFFSET,
 333                 .recalc         = &omap1_ckctl_recalc,
 334                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 335                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 336         },
 337         .idlect_shift   = 6,
 338 };
 339
 340 static struct clk arminth_ck1510 = {
 341         .name           = "arminth_ck",
 342         .ops            = &clkops_null,
 343         .parent         = &tc_ck.clk,
 344         .recalc         = &followparent_recalc,
 345         /* Note: On 1510 the frequency follows TC_CK
 346          *
 347          * 16xx version is in MPU clocks.
 348          */
 349 };
 350
 351 static struct clk tipb_ck = {
 352         /* No-idle controlled by "tc_ck" */
 353         .name           = "tipb_ck",
 354         .ops            = &clkops_null,
 355         .parent         = &tc_ck.clk,
 356         .recalc         = &followparent_recalc,
 357 };
 358
 359 static struct clk l3_ocpi_ck = {
 360         /* No-idle controlled by "tc_ck" */
 361         .name           = "l3_ocpi_ck",
 362         .ops            = &clkops_generic,
 363         .parent         = &tc_ck.clk,
 364         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 365         .enable_bit     = EN_OCPI_CK,
 366         .recalc         = &followparent_recalc,
 367 };
 368
 369 static struct clk tc1_ck = {
 370         .name           = "tc1_ck",
 371         .ops            = &clkops_generic,
 372         .parent         = &tc_ck.clk,
 373         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 374         .enable_bit     = EN_TC1_CK,
 375         .recalc         = &followparent_recalc,
 376 };
 377
 378 static struct clk tc2_ck = {
 379         .name           = "tc2_ck",
 380         .ops            = &clkops_generic,
 381         .parent         = &tc_ck.clk,
 382         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 383         .enable_bit     = EN_TC2_CK,
 384         .recalc         = &followparent_recalc,
 385 };
 386
 387 static struct clk dma_ck = {
 388         /* No-idle controlled by "tc_ck" */
 389         .name           = "dma_ck",
 390         .ops            = &clkops_null,
 391         .parent         = &tc_ck.clk,
 392         .recalc         = &followparent_recalc,
 393 };
 394
 395 static struct clk dma_lcdfree_ck = {
 396         .name           = "dma_lcdfree_ck",
 397         .ops            = &clkops_null,
 398         .parent         = &tc_ck.clk,
 399         .recalc         = &followparent_recalc,
 400 };
 401
 402 static struct arm_idlect1_clk api_ck = {
 403         .clk = {
 404                 .name           = "api_ck",
 405                 .ops            = &clkops_generic,
 406                 .parent         = &tc_ck.clk,
 407                 .flags          = CLOCK_IDLE_CONTROL,
 408                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 409                 .enable_bit     = EN_APICK,
 410                 .recalc         = &followparent_recalc,
 411         },
 412         .idlect_shift   = 8,
 413 };
 414
 415 static struct arm_idlect1_clk lb_ck = {
 416         .clk = {
 417                 .name           = "lb_ck",
 418                 .ops            = &clkops_generic,
 419                 .parent         = &tc_ck.clk,
 420                 .flags          = CLOCK_IDLE_CONTROL,
 421                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 422                 .enable_bit     = EN_LBCK,
 423                 .recalc         = &followparent_recalc,
 424         },
 425         .idlect_shift   = 4,
 426 };
 427
 428 static struct clk rhea1_ck = {
 429         .name           = "rhea1_ck",
 430         .ops            = &clkops_null,
 431         .parent         = &tc_ck.clk,
 432         .recalc         = &followparent_recalc,
 433 };
 434
 435 static struct clk rhea2_ck = {
 436         .name           = "rhea2_ck",
 437         .ops            = &clkops_null,
 438         .parent         = &tc_ck.clk,
 439         .recalc         = &followparent_recalc,
 440 };
 441
 442 static struct clk lcd_ck_16xx = {
 443         .name           = "lcd_ck",
 444         .ops            = &clkops_generic,
 445         .parent         = &ck_dpll1,
 446         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 447         .enable_bit     = EN_LCDCK,
 448         .rate_offset    = CKCTL_LCDDIV_OFFSET,
 449         .recalc         = &omap1_ckctl_recalc,
 450         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 451         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 452 };
 453
 454 static struct arm_idlect1_clk lcd_ck_1510 = {
 455         .clk = {
 456                 .name           = "lcd_ck",
 457                 .ops            = &clkops_generic,
 458                 .parent         = &ck_dpll1,
 459                 .flags          = CLOCK_IDLE_CONTROL,
 460                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 461                 .enable_bit     = EN_LCDCK,
 462                 .rate_offset    = CKCTL_LCDDIV_OFFSET,
 463                 .recalc         = &omap1_ckctl_recalc,
 464                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 465                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 466         },
 467         .idlect_shift   = 3,
 468 };
 469
 470 static struct clk uart1_1510 = {
 471         .name           = "uart1_ck",
 472         .ops            = &clkops_null,
 473         /* Direct from ULPD, no real parent */
 474         .parent         = &armper_ck.clk,
 475         .rate           = 12000000,
 476         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 477         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 478         .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
 479         .set_rate       = &omap1_set_uart_rate,
 480         .recalc         = &omap1_uart_recalc,
 481 };
 482
 483 static struct uart_clk uart1_16xx = {
 484         .clk    = {
 485                 .name           = "uart1_ck",
 486                 .ops            = &clkops_uart,
 487                 /* Direct from ULPD, no real parent */
 488                 .parent         = &armper_ck.clk,
 489                 .rate           = 48000000,
 490                 .flags          = RATE_FIXED | ENABLE_REG_32BIT |
 491                                   CLOCK_NO_IDLE_PARENT,
 492                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 493                 .enable_bit     = 29,
 494         },
 495         .sysc_addr      = 0xfffb0054,
 496 };
 497
 498 static struct clk uart2_ck = {
 499         .name           = "uart2_ck",
 500         .ops            = &clkops_null,
 501         /* Direct from ULPD, no real parent */
 502         .parent         = &armper_ck.clk,
 503         .rate           = 12000000,
 504         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 505         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 506         .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
 507         .set_rate       = &omap1_set_uart_rate,
 508         .recalc         = &omap1_uart_recalc,
 509 };
 510
 511 static struct clk uart3_1510 = {
 512         .name           = "uart3_ck",
 513         .ops            = &clkops_null,
 514         /* Direct from ULPD, no real parent */
 515         .parent         = &armper_ck.clk,
 516         .rate           = 12000000,
 517         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 518         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 519         .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
 520         .set_rate       = &omap1_set_uart_rate,
 521         .recalc         = &omap1_uart_recalc,
 522 };
 523
 524 static struct uart_clk uart3_16xx = {
 525         .clk    = {
 526                 .name           = "uart3_ck",
 527                 .ops            = &clkops_uart,
 528                 /* Direct from ULPD, no real parent */
 529                 .parent         = &armper_ck.clk,
 530                 .rate           = 48000000,
 531                 .flags          = RATE_FIXED | ENABLE_REG_32BIT |
 532                                   CLOCK_NO_IDLE_PARENT,
 533                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 534                 .enable_bit     = 31,
 535         },
 536         .sysc_addr      = 0xfffb9854,
 537 };
 538
 539 static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
 540         .name           = "usb_clko",
 541         .ops            = &clkops_generic,
 542         /* Direct from ULPD, no parent */
 543         .rate           = 6000000,
 544         .flags          = RATE_FIXED | ENABLE_REG_32BIT,
 545         .enable_reg     = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
 546         .enable_bit     = USB_MCLK_EN_BIT,
 547 };
 548
 549 static struct clk usb_hhc_ck1510 = {
 550         .name           = "usb_hhc_ck",
 551         .ops            = &clkops_generic,
 552         /* Direct from ULPD, no parent */
 553         .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
 554         .flags          = RATE_FIXED | ENABLE_REG_32BIT,
 555         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 556         .enable_bit     = USB_HOST_HHC_UHOST_EN,
 557 };
 558
 559 static struct clk usb_hhc_ck16xx = {
 560         .name           = "usb_hhc_ck",
 561         .ops            = &clkops_generic,
 562         /* Direct from ULPD, no parent */
 563         .rate           = 48000000,
 564         /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
 565         .flags          = RATE_FIXED | ENABLE_REG_32BIT,
 566         .enable_reg     = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
 567         .enable_bit     = 8 /* UHOST_EN */,
 568 };
 569
 570 static struct clk usb_dc_ck = {
 571         .name           = "usb_dc_ck",
 572         .ops            = &clkops_generic,
 573         /* Direct from ULPD, no parent */
 574         .rate           = 48000000,
 575         .flags          = RATE_FIXED,
 576         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 577         .enable_bit     = 4,
 578 };
 579
 580 static struct clk mclk_1510 = {
 581         .name           = "mclk",
 582         .ops            = &clkops_generic,
 583         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 584         .rate           = 12000000,
 585         .flags          = RATE_FIXED,
 586         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 587         .enable_bit     = 6,
 588 };
 589
 590 static struct clk mclk_16xx = {
 591         .name           = "mclk",
 592         .ops            = &clkops_generic,
 593         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 594         .enable_reg     = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
 595         .enable_bit     = COM_ULPD_PLL_CLK_REQ,
 596         .set_rate       = &omap1_set_ext_clk_rate,
 597         .round_rate     = &omap1_round_ext_clk_rate,
 598         .init           = &omap1_init_ext_clk,
 599 };
 600
 601 static struct clk bclk_1510 = {
 602         .name           = "bclk",
 603         .ops            = &clkops_generic,
 604         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 605         .rate           = 12000000,
 606         .flags          = RATE_FIXED,
 607 };
 608
 609 static struct clk bclk_16xx = {
 610         .name           = "bclk",
 611         .ops            = &clkops_generic,
 612         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 613         .enable_reg     = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
 614         .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
 615         .set_rate       = &omap1_set_ext_clk_rate,
 616         .round_rate     = &omap1_round_ext_clk_rate,
 617         .init           = &omap1_init_ext_clk,
 618 };
 619
 620 static struct clk mmc1_ck = {
 621         .name           = "mmc_ck",
 622         .ops            = &clkops_generic,
 623         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 624         .parent         = &armper_ck.clk,
 625         .rate           = 48000000,
 626         .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 627         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 628         .enable_bit     = 23,
 629 };
 630
 631 static struct clk mmc2_ck = {
 632         .name           = "mmc_ck",
 633         .id             = 1,
 634         .ops            = &clkops_generic,
 635         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 636         .parent         = &armper_ck.clk,
 637         .rate           = 48000000,
 638         .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 639         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 640         .enable_bit     = 20,
 641 };
 642
 643 static struct clk virtual_ck_mpu = {
 644         .name           = "mpu",
 645         .ops            = &clkops_null,
 646         .parent         = &arm_ck, /* Is smarter alias for */
 647         .recalc         = &followparent_recalc,
 648         .set_rate       = &omap1_select_table_rate,
 649         .round_rate     = &omap1_round_to_table_rate,
 650 };
 651
 652 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
 653 remains active during MPU idle whenever this is enabled */
 654 static struct clk i2c_fck = {
 655         .name           = "i2c_fck",
 656         .id             = 1,
 657         .ops            = &clkops_null,
 658         .flags          = CLOCK_NO_IDLE_PARENT,
 659         .parent         = &armxor_ck.clk,
 660         .recalc         = &followparent_recalc,
 661 };
 662
 663 static struct clk i2c_ick = {
 664         .name           = "i2c_ick",
 665         .id             = 1,
 666         .ops            = &clkops_null,
 667         .flags          = CLOCK_NO_IDLE_PARENT,
 668         .parent         = &armper_ck.clk,
 669         .recalc         = &followparent_recalc,
 670 };
 671
 672 #endif