SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/arm/mach-omap1/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock.h
   3  *
   4  *  Copyright (C) 2004 - 2005 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
  14 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
  15
  16 static unsigned long omap1_ckctl_recalc(struct clk *clk);
  17 static unsigned long omap1_watchdog_recalc(struct clk *clk);
  18 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
  19 static unsigned long omap1_sossi_recalc(struct clk *clk);
  20 static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
  21 static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
  22 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
  23 static unsigned long omap1_uart_recalc(struct clk *clk);
  24 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
  25 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
  26 static void omap1_init_ext_clk(struct clk * clk);
  27 static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
  28 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
  29
  30 static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
  31 static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
  32
  33 struct mpu_rate {
  34         unsigned long           rate;
  35         unsigned long           xtal;
  36         unsigned long           pll_rate;
  37         __u16                   ckctl_val;
  38         __u16                   dpllctl_val;
  39 };
  40
  41 struct uart_clk {
  42         struct clk      clk;
  43         unsigned long   sysc_addr;
  44 };
  45
  46 /* Provide a method for preventing idling some ARM IDLECT clocks */
  47 struct arm_idlect1_clk {
  48         struct clk      clk;
  49         unsigned long   no_idle_count;
  50         __u8            idlect_shift;
  51 };
  52
  53 /* ARM_CKCTL bit shifts */
  54 #define CKCTL_PERDIV_OFFSET     0
  55 #define CKCTL_LCDDIV_OFFSET     2
  56 #define CKCTL_ARMDIV_OFFSET     4
  57 #define CKCTL_DSPDIV_OFFSET     6
  58 #define CKCTL_TCDIV_OFFSET      8
  59 #define CKCTL_DSPMMUDIV_OFFSET  10
  60 /*#define ARM_TIMXO             12*/
  61 #define EN_DSPCK                13
  62 /*#define ARM_INTHCK_SEL        14*/ /* Divide-by-2 for mpu inth_ck */
  63 /* DSP_CKCTL bit shifts */
  64 #define CKCTL_DSPPERDIV_OFFSET  0
  65
  66 /* ARM_IDLECT2 bit shifts */
  67 #define EN_WDTCK        0
  68 #define EN_XORPCK       1
  69 #define EN_PERCK        2
  70 #define EN_LCDCK        3
  71 #define EN_LBCK         4 /* Not on 1610/1710 */
  72 /*#define EN_HSABCK     5*/
  73 #define EN_APICK        6
  74 #define EN_TIMCK        7
  75 #define DMACK_REQ       8
  76 #define EN_GPIOCK       9 /* Not on 1610/1710 */
  77 /*#define EN_LBFREECK   10*/
  78 #define EN_CKOUT_ARM    11
  79
  80 /* ARM_IDLECT3 bit shifts */
  81 #define EN_OCPI_CK      0
  82 #define EN_TC1_CK       2
  83 #define EN_TC2_CK       4
  84
  85 /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
  86 #define EN_DSPTIMCK     5
  87
  88 /* Various register defines for clock controls scattered around OMAP chip */
  89 #define SDW_MCLK_INV_BIT        2       /* In ULPD_CLKC_CTRL */
  90 #define USB_MCLK_EN_BIT         4       /* In ULPD_CLKC_CTRL */
  91 #define USB_HOST_HHC_UHOST_EN   9       /* In MOD_CONF_CTRL_0 */
  92 #define SWD_ULPD_PLL_CLK_REQ    1       /* In SWD_CLK_DIV_CTRL_SEL */
  93 #define COM_ULPD_PLL_CLK_REQ    1       /* In COM_CLK_DIV_CTRL_SEL */
  94 #define SWD_CLK_DIV_CTRL_SEL    0xfffe0874
  95 #define COM_CLK_DIV_CTRL_SEL    0xfffe0878
  96 #define SOFT_REQ_REG            0xfffe0834
  97 #define SOFT_REQ_REG2           0xfffe0880
  98
  99 /*-------------------------------------------------------------------------
 100  * Omap1 MPU rate table
 101  *-------------------------------------------------------------------------*/
 102 static struct mpu_rate rate_table[] = {
 103         /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
 104          * NOTE: Comment order here is different from bits in CKCTL value:
 105          * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
 106          */
 107 #if defined(CONFIG_OMAP_ARM_216MHZ)
 108         { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
 109 #endif
 110 #if defined(CONFIG_OMAP_ARM_195MHZ)
 111         { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
 112 #endif
 113 #if defined(CONFIG_OMAP_ARM_192MHZ)
 114         { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
 115         { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
 116         {  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
 117         {  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
 118         {  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
 119 #endif
 120 #if defined(CONFIG_OMAP_ARM_182MHZ)
 121         { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
 122 #endif
 123 #if defined(CONFIG_OMAP_ARM_168MHZ)
 124         { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
 125 #endif
 126 #if defined(CONFIG_OMAP_ARM_150MHZ)
 127         { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
 128 #endif
 129 #if defined(CONFIG_OMAP_ARM_120MHZ)
 130         { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
 131 #endif
 132 #if defined(CONFIG_OMAP_ARM_96MHZ)
 133         {  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
 134 #endif
 135 #if defined(CONFIG_OMAP_ARM_60MHZ)
 136         {  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
 137 #endif
 138 #if defined(CONFIG_OMAP_ARM_30MHZ)
 139         {  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
 140 #endif
 141         { 0, 0, 0, 0, 0 },
 142 };
 143
 144 /*-------------------------------------------------------------------------
 145  * Omap1 clocks
 146  *-------------------------------------------------------------------------*/
 147
 148 static struct clk ck_ref = {
 149         .name           = "ck_ref",
 150         .ops            = &clkops_null,
 151         .rate           = 12000000,
 152 };
 153
 154 static struct clk ck_dpll1 = {
 155         .name           = "ck_dpll1",
 156         .ops            = &clkops_null,
 157         .parent         = &ck_ref,
 158 };
 159
 160 /*
 161  * FIXME: This clock seems to be necessary but no-one has asked for its
 162  * activation.  [ FIX: SoSSI, SSR ]
 163  */
 164 static struct arm_idlect1_clk ck_dpll1out = {
 165         .clk = {
 166                 .name           = "ck_dpll1out",
 167                 .ops            = &clkops_generic,
 168                 .parent         = &ck_dpll1,
 169                 .flags          = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
 170                                   ENABLE_ON_INIT,
 171                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 172                 .enable_bit     = EN_CKOUT_ARM,
 173                 .recalc         = &followparent_recalc,
 174         },
 175         .idlect_shift   = 12,
 176 };
 177
 178 static struct clk sossi_ck = {
 179         .name           = "ck_sossi",
 180         .ops            = &clkops_generic,
 181         .parent         = &ck_dpll1out.clk,
 182         .flags          = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
 183         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
 184         .enable_bit     = 16,
 185         .recalc         = &omap1_sossi_recalc,
 186         .set_rate       = &omap1_set_sossi_rate,
 187 };
 188
 189 static struct clk arm_ck = {
 190         .name           = "arm_ck",
 191         .ops            = &clkops_null,
 192         .parent         = &ck_dpll1,
 193         .rate_offset    = CKCTL_ARMDIV_OFFSET,
 194         .recalc         = &omap1_ckctl_recalc,
 195         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 196         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 197 };
 198
 199 static struct arm_idlect1_clk armper_ck = {
 200         .clk = {
 201                 .name           = "armper_ck",
 202                 .ops            = &clkops_generic,
 203                 .parent         = &ck_dpll1,
 204                 .flags          = CLOCK_IDLE_CONTROL,
 205                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 206                 .enable_bit     = EN_PERCK,
 207                 .rate_offset    = CKCTL_PERDIV_OFFSET,
 208                 .recalc         = &omap1_ckctl_recalc,
 209                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 210                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 211         },
 212         .idlect_shift   = 2,
 213 };
 214
 215 /*
 216  * FIXME: This clock seems to be necessary but no-one has asked for its
 217  * activation.  [ GPIO code for 1510 ]
 218  */
 219 static struct clk arm_gpio_ck = {
 220         .name           = "arm_gpio_ck",
 221         .ops            = &clkops_generic,
 222         .parent         = &ck_dpll1,
 223         .flags          = ENABLE_ON_INIT,
 224         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 225         .enable_bit     = EN_GPIOCK,
 226         .recalc         = &followparent_recalc,
 227 };
 228
 229 static struct arm_idlect1_clk armxor_ck = {
 230         .clk = {
 231                 .name           = "armxor_ck",
 232                 .ops            = &clkops_generic,
 233                 .parent         = &ck_ref,
 234                 .flags          = CLOCK_IDLE_CONTROL,
 235                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 236                 .enable_bit     = EN_XORPCK,
 237                 .recalc         = &followparent_recalc,
 238         },
 239         .idlect_shift   = 1,
 240 };
 241
 242 static struct arm_idlect1_clk armtim_ck = {
 243         .clk = {
 244                 .name           = "armtim_ck",
 245                 .ops            = &clkops_generic,
 246                 .parent         = &ck_ref,
 247                 .flags          = CLOCK_IDLE_CONTROL,
 248                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 249                 .enable_bit     = EN_TIMCK,
 250                 .recalc         = &followparent_recalc,
 251         },
 252         .idlect_shift   = 9,
 253 };
 254
 255 static struct arm_idlect1_clk armwdt_ck = {
 256         .clk = {
 257                 .name           = "armwdt_ck",
 258                 .ops            = &clkops_generic,
 259                 .parent         = &ck_ref,
 260                 .flags          = CLOCK_IDLE_CONTROL,
 261                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 262                 .enable_bit     = EN_WDTCK,
 263                 .recalc         = &omap1_watchdog_recalc,
 264         },
 265         .idlect_shift   = 0,
 266 };
 267
 268 static struct clk arminth_ck16xx = {
 269         .name           = "arminth_ck",
 270         .ops            = &clkops_null,
 271         .parent         = &arm_ck,
 272         .recalc         = &followparent_recalc,
 273         /* Note: On 16xx the frequency can be divided by 2 by programming
 274          * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
 275          *
 276          * 1510 version is in TC clocks.
 277          */
 278 };
 279
 280 static struct clk dsp_ck = {
 281         .name           = "dsp_ck",
 282         .ops            = &clkops_generic,
 283         .parent         = &ck_dpll1,
 284         .enable_reg     = OMAP1_IO_ADDRESS(ARM_CKCTL),
 285         .enable_bit     = EN_DSPCK,
 286         .rate_offset    = CKCTL_DSPDIV_OFFSET,
 287         .recalc         = &omap1_ckctl_recalc,
 288         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 289         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 290 };
 291
 292 static struct clk dspmmu_ck = {
 293         .name           = "dspmmu_ck",
 294         .ops            = &clkops_null,
 295         .parent         = &ck_dpll1,
 296         .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
 297         .recalc         = &omap1_ckctl_recalc,
 298         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 299         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 300 };
 301
 302 static struct clk dspper_ck = {
 303         .name           = "dspper_ck",
 304         .ops            = &clkops_dspck,
 305         .parent         = &ck_dpll1,
 306         .enable_reg     = DSP_IDLECT2,
 307         .enable_bit     = EN_PERCK,
 308         .rate_offset    = CKCTL_PERDIV_OFFSET,
 309         .recalc         = &omap1_ckctl_recalc_dsp_domain,
 310         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 311         .set_rate       = &omap1_clk_set_rate_dsp_domain,
 312 };
 313
 314 static struct clk dspxor_ck = {
 315         .name           = "dspxor_ck",
 316         .ops            = &clkops_dspck,
 317         .parent         = &ck_ref,
 318         .enable_reg     = DSP_IDLECT2,
 319         .enable_bit     = EN_XORPCK,
 320         .recalc         = &followparent_recalc,
 321 };
 322
 323 static struct clk dsptim_ck = {
 324         .name           = "dsptim_ck",
 325         .ops            = &clkops_dspck,
 326         .parent         = &ck_ref,
 327         .enable_reg     = DSP_IDLECT2,
 328         .enable_bit     = EN_DSPTIMCK,
 329         .recalc         = &followparent_recalc,
 330 };
 331
 332 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
 333 static struct arm_idlect1_clk tc_ck = {
 334         .clk = {
 335                 .name           = "tc_ck",
 336                 .ops            = &clkops_null,
 337                 .parent         = &ck_dpll1,
 338                 .flags          = CLOCK_IDLE_CONTROL,
 339                 .rate_offset    = CKCTL_TCDIV_OFFSET,
 340                 .recalc         = &omap1_ckctl_recalc,
 341                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 342                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 343         },
 344         .idlect_shift   = 6,
 345 };
 346
 347 static struct clk arminth_ck1510 = {
 348         .name           = "arminth_ck",
 349         .ops            = &clkops_null,
 350         .parent         = &tc_ck.clk,
 351         .recalc         = &followparent_recalc,
 352         /* Note: On 1510 the frequency follows TC_CK
 353          *
 354          * 16xx version is in MPU clocks.
 355          */
 356 };
 357
 358 static struct clk tipb_ck = {
 359         /* No-idle controlled by "tc_ck" */
 360         .name           = "tipb_ck",
 361         .ops            = &clkops_null,
 362         .parent         = &tc_ck.clk,
 363         .recalc         = &followparent_recalc,
 364 };
 365
 366 static struct clk l3_ocpi_ck = {
 367         /* No-idle controlled by "tc_ck" */
 368         .name           = "l3_ocpi_ck",
 369         .ops            = &clkops_generic,
 370         .parent         = &tc_ck.clk,
 371         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 372         .enable_bit     = EN_OCPI_CK,
 373         .recalc         = &followparent_recalc,
 374 };
 375
 376 static struct clk tc1_ck = {
 377         .name           = "tc1_ck",
 378         .ops            = &clkops_generic,
 379         .parent         = &tc_ck.clk,
 380         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 381         .enable_bit     = EN_TC1_CK,
 382         .recalc         = &followparent_recalc,
 383 };
 384
 385 /*
 386  * FIXME: This clock seems to be necessary but no-one has asked for its
 387  * activation.  [ pm.c (SRAM), CCP, Camera ]
 388  */
 389 static struct clk tc2_ck = {
 390         .name           = "tc2_ck",
 391         .ops            = &clkops_generic,
 392         .parent         = &tc_ck.clk,
 393         .flags          = ENABLE_ON_INIT,
 394         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 395         .enable_bit     = EN_TC2_CK,
 396         .recalc         = &followparent_recalc,
 397 };
 398
 399 static struct clk dma_ck = {
 400         /* No-idle controlled by "tc_ck" */
 401         .name           = "dma_ck",
 402         .ops            = &clkops_null,
 403         .parent         = &tc_ck.clk,
 404         .recalc         = &followparent_recalc,
 405 };
 406
 407 static struct clk dma_lcdfree_ck = {
 408         .name           = "dma_lcdfree_ck",
 409         .ops            = &clkops_null,
 410         .parent         = &tc_ck.clk,
 411         .recalc         = &followparent_recalc,
 412 };
 413
 414 static struct arm_idlect1_clk api_ck = {
 415         .clk = {
 416                 .name           = "api_ck",
 417                 .ops            = &clkops_generic,
 418                 .parent         = &tc_ck.clk,
 419                 .flags          = CLOCK_IDLE_CONTROL,
 420                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 421                 .enable_bit     = EN_APICK,
 422                 .recalc         = &followparent_recalc,
 423         },
 424         .idlect_shift   = 8,
 425 };
 426
 427 static struct arm_idlect1_clk lb_ck = {
 428         .clk = {
 429                 .name           = "lb_ck",
 430                 .ops            = &clkops_generic,
 431                 .parent         = &tc_ck.clk,
 432                 .flags          = CLOCK_IDLE_CONTROL,
 433                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 434                 .enable_bit     = EN_LBCK,
 435                 .recalc         = &followparent_recalc,
 436         },
 437         .idlect_shift   = 4,
 438 };
 439
 440 static struct clk rhea1_ck = {
 441         .name           = "rhea1_ck",
 442         .ops            = &clkops_null,
 443         .parent         = &tc_ck.clk,
 444         .recalc         = &followparent_recalc,
 445 };
 446
 447 static struct clk rhea2_ck = {
 448         .name           = "rhea2_ck",
 449         .ops            = &clkops_null,
 450         .parent         = &tc_ck.clk,
 451         .recalc         = &followparent_recalc,
 452 };
 453
 454 static struct clk lcd_ck_16xx = {
 455         .name           = "lcd_ck",
 456         .ops            = &clkops_generic,
 457         .parent         = &ck_dpll1,
 458         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 459         .enable_bit     = EN_LCDCK,
 460         .rate_offset    = CKCTL_LCDDIV_OFFSET,
 461         .recalc         = &omap1_ckctl_recalc,
 462         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 463         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 464 };
 465
 466 static struct arm_idlect1_clk lcd_ck_1510 = {
 467         .clk = {
 468                 .name           = "lcd_ck",
 469                 .ops            = &clkops_generic,
 470                 .parent         = &ck_dpll1,
 471                 .flags          = CLOCK_IDLE_CONTROL,
 472                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 473                 .enable_bit     = EN_LCDCK,
 474                 .rate_offset    = CKCTL_LCDDIV_OFFSET,
 475                 .recalc         = &omap1_ckctl_recalc,
 476                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 477                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 478         },
 479         .idlect_shift   = 3,
 480 };
 481
 482 static struct clk uart1_1510 = {
 483         .name           = "uart1_ck",
 484         .ops            = &clkops_null,
 485         /* Direct from ULPD, no real parent */
 486         .parent         = &armper_ck.clk,
 487         .rate           = 12000000,
 488         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 489         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 490         .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
 491         .set_rate       = &omap1_set_uart_rate,
 492         .recalc         = &omap1_uart_recalc,
 493 };
 494
 495 static struct uart_clk uart1_16xx = {
 496         .clk    = {
 497                 .name           = "uart1_ck",
 498                 .ops            = &clkops_uart,
 499                 /* Direct from ULPD, no real parent */
 500                 .parent         = &armper_ck.clk,
 501                 .rate           = 48000000,
 502                 .flags          = RATE_FIXED | ENABLE_REG_32BIT |
 503                                   CLOCK_NO_IDLE_PARENT,
 504                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 505                 .enable_bit     = 29,
 506         },
 507         .sysc_addr      = 0xfffb0054,
 508 };
 509
 510 static struct clk uart2_ck = {
 511         .name           = "uart2_ck",
 512         .ops            = &clkops_null,
 513         /* Direct from ULPD, no real parent */
 514         .parent         = &armper_ck.clk,
 515         .rate           = 12000000,
 516         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 517         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 518         .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
 519         .set_rate       = &omap1_set_uart_rate,
 520         .recalc         = &omap1_uart_recalc,
 521 };
 522
 523 static struct clk uart3_1510 = {
 524         .name           = "uart3_ck",
 525         .ops            = &clkops_null,
 526         /* Direct from ULPD, no real parent */
 527         .parent         = &armper_ck.clk,
 528         .rate           = 12000000,
 529         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 530         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 531         .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
 532         .set_rate       = &omap1_set_uart_rate,
 533         .recalc         = &omap1_uart_recalc,
 534 };
 535
 536 static struct uart_clk uart3_16xx = {
 537         .clk    = {
 538                 .name           = "uart3_ck",
 539                 .ops            = &clkops_uart,
 540                 /* Direct from ULPD, no real parent */
 541                 .parent         = &armper_ck.clk,
 542                 .rate           = 48000000,
 543                 .flags          = RATE_FIXED | ENABLE_REG_32BIT |
 544                                   CLOCK_NO_IDLE_PARENT,
 545                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 546                 .enable_bit     = 31,
 547         },
 548         .sysc_addr      = 0xfffb9854,
 549 };
 550
 551 static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
 552         .name           = "usb_clko",
 553         .ops            = &clkops_generic,
 554         /* Direct from ULPD, no parent */
 555         .rate           = 6000000,
 556         .flags          = RATE_FIXED | ENABLE_REG_32BIT,
 557         .enable_reg     = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
 558         .enable_bit     = USB_MCLK_EN_BIT,
 559 };
 560
 561 static struct clk usb_hhc_ck1510 = {
 562         .name           = "usb_hhc_ck",
 563         .ops            = &clkops_generic,
 564         /* Direct from ULPD, no parent */
 565         .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
 566         .flags          = RATE_FIXED | ENABLE_REG_32BIT,
 567         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 568         .enable_bit     = USB_HOST_HHC_UHOST_EN,
 569 };
 570
 571 static struct clk usb_hhc_ck16xx = {
 572         .name           = "usb_hhc_ck",
 573         .ops            = &clkops_generic,
 574         /* Direct from ULPD, no parent */
 575         .rate           = 48000000,
 576         /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
 577         .flags          = RATE_FIXED | ENABLE_REG_32BIT,
 578         .enable_reg     = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
 579         .enable_bit     = 8 /* UHOST_EN */,
 580 };
 581
 582 static struct clk usb_dc_ck = {
 583         .name           = "usb_dc_ck",
 584         .ops            = &clkops_generic,
 585         /* Direct from ULPD, no parent */
 586         .rate           = 48000000,
 587         .flags          = RATE_FIXED,
 588         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 589         .enable_bit     = 4,
 590 };
 591
 592 static struct clk usb_dc_ck7xx = {
 593         .name           = "usb_dc_ck",
 594         .ops            = &clkops_generic,
 595         /* Direct from ULPD, no parent */
 596         .rate           = 48000000,
 597         .flags          = RATE_FIXED,
 598         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 599         .enable_bit     = 8,
 600 };
 601
 602 static struct clk mclk_1510 = {
 603         .name           = "mclk",
 604         .ops            = &clkops_generic,
 605         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 606         .rate           = 12000000,
 607         .flags          = RATE_FIXED,
 608         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 609         .enable_bit     = 6,
 610 };
 611
 612 static struct clk mclk_16xx = {
 613         .name           = "mclk",
 614         .ops            = &clkops_generic,
 615         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 616         .enable_reg     = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
 617         .enable_bit     = COM_ULPD_PLL_CLK_REQ,
 618         .set_rate       = &omap1_set_ext_clk_rate,
 619         .round_rate     = &omap1_round_ext_clk_rate,
 620         .init           = &omap1_init_ext_clk,
 621 };
 622
 623 static struct clk bclk_1510 = {
 624         .name           = "bclk",
 625         .ops            = &clkops_generic,
 626         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 627         .rate           = 12000000,
 628         .flags          = RATE_FIXED,
 629 };
 630
 631 static struct clk bclk_16xx = {
 632         .name           = "bclk",
 633         .ops            = &clkops_generic,
 634         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 635         .enable_reg     = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
 636         .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
 637         .set_rate       = &omap1_set_ext_clk_rate,
 638         .round_rate     = &omap1_round_ext_clk_rate,
 639         .init           = &omap1_init_ext_clk,
 640 };
 641
 642 static struct clk mmc1_ck = {
 643         .name           = "mmc_ck",
 644         .ops            = &clkops_generic,
 645         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 646         .parent         = &armper_ck.clk,
 647         .rate           = 48000000,
 648         .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 649         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 650         .enable_bit     = 23,
 651 };
 652
 653 static struct clk mmc2_ck = {
 654         .name           = "mmc_ck",
 655         .id             = 1,
 656         .ops            = &clkops_generic,
 657         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 658         .parent         = &armper_ck.clk,
 659         .rate           = 48000000,
 660         .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 661         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 662         .enable_bit     = 20,
 663 };
 664
 665 static struct clk mmc3_ck = {
 666         .name           = "mmc_ck",
 667         .id             = 2,
 668         .ops            = &clkops_generic,
 669         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 670         .parent         = &armper_ck.clk,
 671         .rate           = 48000000,
 672         .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 673         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 674         .enable_bit     = 12,
 675 };
 676
 677 static struct clk virtual_ck_mpu = {
 678         .name           = "mpu",
 679         .ops            = &clkops_null,
 680         .parent         = &arm_ck, /* Is smarter alias for */
 681         .recalc         = &followparent_recalc,
 682         .set_rate       = &omap1_select_table_rate,
 683         .round_rate     = &omap1_round_to_table_rate,
 684 };
 685
 686 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
 687 remains active during MPU idle whenever this is enabled */
 688 static struct clk i2c_fck = {
 689         .name           = "i2c_fck",
 690         .id             = 1,
 691         .ops            = &clkops_null,
 692         .flags          = CLOCK_NO_IDLE_PARENT,
 693         .parent         = &armxor_ck.clk,
 694         .recalc         = &followparent_recalc,
 695 };
 696
 697 static struct clk i2c_ick = {
 698         .name           = "i2c_ick",
 699         .id             = 1,
 700         .ops            = &clkops_null,
 701         .flags          = CLOCK_NO_IDLE_PARENT,
 702         .parent         = &armper_ck.clk,
 703         .recalc         = &followparent_recalc,
 704 };
 705
 706 #endif