2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/delay.h>
20 #include <linux/types.h>
21 #include <linux/init.h>
22 #include <linux/clk.h>
23 #include <linux/irq.h>
24 #include <linux/gpio.h>
25 #include <linux/smsc911x.h>
26 #include <linux/platform_device.h>
27 #include <linux/mfd/mc13783.h>
28 #include <linux/spi/spi.h>
29 #include <linux/regulator/machine.h>
30 #include <linux/fsl_devices.h>
32 #include <mach/hardware.h>
33 #include <asm/mach-types.h>
34 #include <asm/mach/arch.h>
35 #include <asm/mach/time.h>
36 #include <asm/memory.h>
37 #include <asm/mach/map.h>
38 #include <mach/common.h>
39 #include <mach/board-mx31_3ds.h>
40 #include <mach/imx-uart.h>
41 #include <mach/iomux-mx3.h>
42 #include <mach/mxc_nand.h>
49 * @brief This file contains the board-specific initialization routines.
54 static int mx31_3ds_pins[] = {
60 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
62 MX31_PIN_CSPI2_SCLK__SCLK,
63 MX31_PIN_CSPI2_MOSI__MOSI,
64 MX31_PIN_CSPI2_MISO__MISO,
65 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
66 MX31_PIN_CSPI2_SS0__SS0,
67 MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
69 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
71 IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
73 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
74 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
75 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
76 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
77 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
78 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
79 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
80 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
81 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
82 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
83 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
84 MX31_PIN_USBOTG_STP__USBOTG_STP,
88 static struct regulator_init_data pwgtx_init = {
95 static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
97 .id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */
98 .init_data = &pwgtx_init,
100 .id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */
101 .init_data = &pwgtx_init,
106 static struct mc13783_platform_data mc13783_pdata __initdata = {
107 .regulators = mx31_3ds_regulators,
108 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
109 .flags = MC13783_USE_REGULATOR,
113 static int spi1_internal_chipselect[] = {
118 static struct spi_imx_master spi1_pdata = {
119 .chipselect = spi1_internal_chipselect,
120 .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
123 static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
125 .modalias = "mc13783",
126 .max_speed_hz = 1000000,
128 .chip_select = 1, /* SS2 */
129 .platform_data = &mc13783_pdata,
130 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
138 static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
141 #ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
150 #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
151 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
153 #define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
155 static void mx31_3ds_usbotg_init(void)
157 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
158 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
159 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
160 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
161 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
162 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
163 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
164 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
165 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
166 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
167 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
168 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
170 gpio_request(USBOTG_RST_B, "otgusb-reset");
171 gpio_direction_output(USBOTG_RST_B, 0);
173 gpio_set_value(USBOTG_RST_B, 1);
176 static struct fsl_usb2_platform_data usbotg_pdata = {
177 .operating_mode = FSL_USB2_DR_DEVICE,
178 .phy_mode = FSL_USB2_PHY_ULPI,
181 static struct imxuart_platform_data uart_pdata = {
182 .flags = IMXUART_HAVE_RTSCTS,
186 * Support for the SMSC9217 on the Debug board.
189 static struct smsc911x_platform_config smsc911x_config = {
190 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
191 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
192 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
193 .phy_interface = PHY_INTERFACE_MODE_MII,
196 static struct resource smsc911x_resources[] = {
198 .start = LAN9217_BASE_ADDR,
199 .end = LAN9217_BASE_ADDR + 0xff,
200 .flags = IORESOURCE_MEM,
202 .start = EXPIO_INT_ENET,
203 .end = EXPIO_INT_ENET,
204 .flags = IORESOURCE_IRQ,
208 static struct platform_device smsc911x_device = {
211 .num_resources = ARRAY_SIZE(smsc911x_resources),
212 .resource = smsc911x_resources,
214 .platform_data = &smsc911x_config,
219 * Routines for the CPLD on the debug board. It contains a CPLD handling
220 * LEDs, switches, interrupts for Ethernet.
223 static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
229 imr_val = __raw_readw(CPLD_INT_MASK_REG);
230 int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
232 expio_irq = MXC_EXP_IO_BASE;
233 for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
234 if ((int_valid & 1) == 0)
236 generic_handle_irq(expio_irq);
241 * Disable an expio pin's interrupt by setting the bit in the imr.
242 * @param irq an expio virtual irq number
244 static void expio_mask_irq(uint32_t irq)
247 uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
249 /* mask the interrupt */
250 reg = __raw_readw(CPLD_INT_MASK_REG);
252 __raw_writew(reg, CPLD_INT_MASK_REG);
256 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
257 * @param irq an expanded io virtual irq number
259 static void expio_ack_irq(uint32_t irq)
261 uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
263 /* clear the interrupt status */
264 __raw_writew(1 << expio, CPLD_INT_RESET_REG);
265 __raw_writew(0, CPLD_INT_RESET_REG);
266 /* mask the interrupt */
271 * Enable a expio pin's interrupt by clearing the bit in the imr.
272 * @param irq a expio virtual irq number
274 static void expio_unmask_irq(uint32_t irq)
277 uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
279 /* unmask the interrupt */
280 reg = __raw_readw(CPLD_INT_MASK_REG);
281 reg &= ~(1 << expio);
282 __raw_writew(reg, CPLD_INT_MASK_REG);
285 static struct irq_chip expio_irq_chip = {
286 .ack = expio_ack_irq,
287 .mask = expio_mask_irq,
288 .unmask = expio_unmask_irq,
291 static int __init mx31_3ds_init_expio(void)
296 /* Check if there's a debug board connected */
297 if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
298 (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
299 (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
300 /* No Debug board found */
304 pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
305 __raw_readw(CPLD_CODE_VER_REG));
308 * Configure INT line as GPIO input
310 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
312 pr_warning("could not get LAN irq gpio\n");
314 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
316 /* Disable the interrupts and clear the status */
317 __raw_writew(0, CPLD_INT_MASK_REG);
318 __raw_writew(0xFFFF, CPLD_INT_RESET_REG);
319 __raw_writew(0, CPLD_INT_RESET_REG);
320 __raw_writew(0x1F, CPLD_INT_MASK_REG);
321 for (i = MXC_EXP_IO_BASE;
322 i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
324 set_irq_chip(i, &expio_irq_chip);
325 set_irq_handler(i, handle_level_irq);
326 set_irq_flags(i, IRQF_VALID);
328 set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
329 set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
335 * This structure defines the MX31 memory map.
337 static struct map_desc mx31_3ds_io_desc[] __initdata = {
339 .virtual = MX31_CS5_BASE_ADDR_VIRT,
340 .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
341 .length = MX31_CS5_SIZE,
347 * Set up static virtual mappings.
349 static void __init mx31_3ds_map_io(void)
352 iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
356 * Board specific initialization.
358 static void __init mxc_board_init(void)
360 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
363 mxc_register_device(&mxc_uart_device0, &uart_pdata);
364 mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata);
366 mxc_register_device(&mxc_spi_device1, &spi1_pdata);
367 spi_register_board_info(mx31_3ds_spi_devs,
368 ARRAY_SIZE(mx31_3ds_spi_devs));
370 mx31_3ds_usbotg_init();
371 mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
373 if (!mx31_3ds_init_expio())
374 platform_device_register(&smsc911x_device);
377 static void __init mx31_3ds_timer_init(void)
379 mx31_clocks_init(26000000);
382 static struct sys_timer mx31_3ds_timer = {
383 .init = mx31_3ds_timer_init,
387 * The following uses standard kernel macros defined in arch.h in order to
388 * initialize __mach_desc_MX31_3DS data structure.
390 MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
391 /* Maintainer: Freescale Semiconductor, Inc. */
392 .phys_io = MX31_AIPS1_BASE_ADDR,
393 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
394 .boot_params = MX3x_PHYS_OFFSET + 0x100,
395 .map_io = mx31_3ds_map_io,
396 .init_irq = mx31_init_irq,
397 .init_machine = mxc_board_init,
398 .timer = &mx31_3ds_timer,